S8380

S8380_10 HAMAMATSU | Alldatasheet

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Technical content

Features

/K6C High sensitivity in the IR and soft X-ray regions /K6C Wide active area Pixel pitch: 50 µm (S8380 series) 25 µm (S8381 series) Pixel height: 2.5 mm /K6C High UV sensitivity with good stability /K6C Low dark current and high saturation charge allow a long integration time and a wide dynamic range at room temperature /K6C Excellent output linearity and sensitivity spatial uniformity /K6C Lower power consumption: 1 mW max. /K6C Start pulse and clock pulses are CMOS logic compatible

Applications

/K6C Multichannel spectrophotometry /K6C Image readout system IMAGE SENSOR NMOS linear image sensor NMOS linear image sensors with high IR sensitivity S8380/S8381 series 2.5 mm1.0 µm1.0 µm 400 µm Oxidation silicon N type silicon P type silicon S8380 series: a=50 µm, b=45 µm S8381 series: a=25 µm, b=20 µm b a KMPDC0020EA I çEquivalent circuit Vss Start st Clock Clock Active photodiode Saturation control gate Saturation control drain Dummy diode Dummy video Active video End of scanDigital shift register (MOS shift register) I Active area structure KMPDA0125EA I Absolute maximum ratings Parameter Symbol Value Unit Input pulse (φ1, φ2, φst) voltage V φ 15 V Power consumption*1 P 1 mW Operating temperature*2 Topr -40 to +65 °C Storage temperature Tstg -40 to +85 °C *1: Vφ=5.0 V *2: No condensation

NMOS linear image sensor S8380/S8381 series I Shape specifications Parameter S8380-128Q S8380-256Q S8380-512Q S8381-256Q S8381-512Q S8381-1024Q Unit Number of pixels 128 256 512 256 512 1024 - Package length 31.75 40.6 31.75 40.6 mm Number of pin 22 22 - Window material*3 Quartz Quartz - Weight 3.0 3.5 3.0 3.5 g *3: Fiber optic plate is available (excluding the S8380-128Q, S8381-256Q). I Specifications (Ta=25 °C) Pixel pitch - - 50 - - 25 - µm Pixel height - - 2.5 - - 2.5 - mm Spectral response range (10 % of peak) λ 200 to 1000 200 to 1000 nm Peak sensitivity wavelength λp - 750 - - 750 - nm Photodiode dark current* 4 ID - 0.2 0.6 - 0.1 0.3 pA Photodiode capacitance* 4 Cph - 20 - - 10 - pF Saturation exposure* 4 *5 Esat - 90 - - 90 - mlx · s Saturation output charge* 4 Qsat - 50 - - 25 - pC Photo response non-uniformity* 6 PRNU - - ±3 - - ±3 % *4: Vb=2.0 V, Vφ=5.0 V *5: 2856 K, tungsten lamp *6: 50% of saturation, excluding the start pixel and last pixel I Electrical characteristics (Ta=25 °C) High Vφ1, Vφ2 (H) 4.5 5 10 4.5 5 10 V Clock pulse (φ1, φ2) voltage Low Vφ1, Vφ2 (L) 0 - 0.4 0 - 0.4 V High Vφs (H) 4.5 Vφ1 10 4.5 Vφ1 10 V Start pulse (φst) voltage Low Vφs (L) 0 - 0.4 0 - 0.4 V Saturation control gate voltage Vscg - 0 - - 0 - V Saturation control drain voltage Vscd - Vb - - Vb - V Clock pulse ( φ1, φ2) rise / fall time *8 trφ1, trφ2 tfφ1, tfφ2 - 20 - - 20 - ns Clock pulse (φ1, φ2) pulse width tpw φ1, tpwφ2 200 - - 200 - - ns Start pulse (φst) rise / fall time trφs, tfφs - 20 - - 20 - ns Start pulse (φst) pulse width tpw φs 200 - - 200 - - ns Start pulse (φst) and clock pulse (φ2) overlap tφov 200 - - 200 - - ns Clock pulse space* 8 X1, X2 trf - 20 - - trf - 20 - - ns Data rate*9 f 0.1 - 2000 0.1 - 2000 kHz - 120 (-256 Q) - - 150 (-512 Q) - ns Video delay time tvd 50% of saturation - 36 (-256 Q) - - 50 (-512 Q) - pF Clock pulse (φ1, φ2) line capacitance Cφ 5 V bias - 20 (-256 Q) - - 24 (-512 Q) - pF Saturation control gate (Vscg) line capacitance Cscg 5 V bias - 11 (-256 Q) - - 16 (-512 Q) - pF Video line capacitance CV 2 V bias *7: Vφ is input pulse voltage (refer to “I Video bias voltage margin”). *8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 20 ns (refer to “I Timing chart for driver circuit ”). *9: Vb=2.0 V, Vφ=5.0 V *10: Measured with C7883 driver circuit.

NMOS linear image sensor S8380/S8381 series I Dimensional outlines (unit: mm) S8380-128Q, S8381-256Q S8380-256Q, S8381-512Q 0.51 ± 0.05 25.4 ± 0.13 2.54 ± 0.13 3.0 ± 0.3 31.75 ± 0.3 10.4 ± 0.25 5.2 ± 0.2 3.2 ± 0.3 0.25 10.16 ± 0.25 1.3 ± 0.2*1 5.0 ± 0.5 Chip surface Active area 6.4 × 2.5 1 ch Direction of scan *1: Distance from upper surface of quartz window to chip surface *2: Distance from chip surface to bottom of package *3: Window thickness 1.4 ± 0.2*2 0.5 ± 0.05*3 0.51 ± 0.05 25.4 ± 0.13 2.54 ± 0.13 3.0 ± 0.3 Active area 12.8 × 2.5 6.4 ± 0.3 31.75 ± 0.3 Direction of scan 10.4 ± 0.25 5.2 ± 0.2 0.25 10.16 ± 0.25 1.3 ± 0.2*1 *1: Distance from upper surface of quartz window to chip surface *2: Distance from chip surface to bottom of package *3: Window thickness 1.4 ± 0.2*2 0.5 ± 0.05*3 5.0 ± 0.5 1 ch Chip surface KMPDA0060ED KMPDA0061ED S8380-512Q, S8381-1024Q 0.51 ± 0.05 25.4 ± 0.13 3.0 ± 0.3 40.6 ± 0.3 10.4 ± 0.25 5.2 ± 0.2 12.8 ± 0.3 Active area 25.6 × 2.5 0.25 10.16 ± 0.25 1.3 ± 0.2*1 2.54 ± 0.13 1 ch5.0 ± 0.5 Direction of scan *1: Distance from upper surface of quartz window to chip surface *2: Distance from chip surface to bottom of package *3: Window thickness 1.4 ± 0.2*2 0.5 ± 0.05*3 Chip surface KMPDA0062ED NC NC NC NC NC NC NC NC NC NC End of scan st Vss Vscg NC Vscd Vss Active video Dummy video Vsub Vss, Vsub and NC should be grounded. KMPDC0056EA I Pin connection

NMOS linear image sensor S8380/S8381 series HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, www.hamamatsu.com Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. Type numbers of products listed inthe specification sheets or supplied as samples may have a suffix "(X)" which means tentative specifications or a suffix "(Z)" which means developmental specifications. ©2010 Hamamatsu Photonics K.K. Cat. No. KMPD1045E02 Jul. 2010 DN tvd tpw 1 tpw 2 tpw s st V s (H) V s (L) V 1 (H) V 1 (L) V 2 (H) V 2 (L) End of scan st tr s tf s tr 1 tf 1 X1 X2 t ov tf 2 tr 2 Active video output I Timing chart for driver circuit I Video bias voltage margin 45678 1 0 Clock pulse amplitude (V) Video bias voltage (V) Min. Video bias range M ax. Recommended bias 0.5 0.4 0.3 0.2 0.1 200 400 600 800 1000 1200 Wavelength (nm) Photo sensitivity (A/W) (Ta=25 ˚C) Standard type IR high-sensitivity type S8380/S8381 series I Recommended operating conditions Terminal Input or output Description φ1, φ2 Input (CMOS logic compatible) Pulses for operating the MOS shift register. The video data rate is equal to the clock pulse frequency since the video output signal is obtained synchronously with the rise of φ2 pulse. φst Input (CMOS logic compatible) Pulse for starting the MOS shift register operation. The time interval between start pulses is equal to the signal accumulation time. Vss - Connected to the anode of each photodiode. This should be grounded. Vscg Input Used for restricting blooming. This should be grounded. Vscd Input Used for restricting blooming. This should be biased at a voltage equal to the video bias voltage. Active video Output Video output signal. Connects to photodiode cathodes when the address is on. A positive voltage should be applied to the video line in order to use photodiodes with a reverse voltage. When the amplitude of φ1 and φ2 is 5 V, a video bias voltage of 2 V is recommended. Dummy video Output This has the same structure as the active video, but is not connected to photodiodes, so only spike noise is output. This should be biased at a voltage equal to the active video or left as an open-circuit when not needed. Vsub - Connected to the silicon substrate. This should be grounded. End of scan Output (CMOS logic compatible) This should be pulled up at 5 V by using a 10 k Ω resistor. This is a negative going pulse that appears synchronously with the φ2 timing right after the last photodiode is addressed. NC - Should be grounded. 10-5 102 101 100 10-1 10-2 10-3 10-4 10-3 10-2 10-1 100 Output charge (pC) Exposure (lx · s) (Typ. Vb=2 V, V =5 V, light source: 2856 K) S8380 series S8381 series Saturation exposure Saturation charge I Spectral response (typical example) I Output charge vs. exposure KMPDB0043EA KMPDB0161EA KMPDB0162EB KMPDC0022EA