S8380 HAMAMATSU | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 4

Technical content

NMOS linear image sensor S8380/S8381 series I Shape specifications Parameter S8380-128Q S8380-256Q S8380-512Q S8381-256Q S8381-512Q S8381-1024Q Unit Number of pixels 128 256 512 256 512 1024 - Package length 31.75 40.6 31.75 40.6 mm Number of pin 22 22 - Window material *3 Quartz Quartz - Weight 3.0 3.5 3.0 3.5 g *3: Fiber optic plate is available. I Specifications (Ta=25 °C) P i x e l p i t ch - -5 0- -2 5- µm Pixel height - - 2.5 - - 2.5 - mm Spectral response range (10 % of peak) λ 200 to 1000 200 to 1000 nm Peak sensitivity wavelength λp - 750 - - 750 - nm Photodiode dark current * 4 ID - 0.2 0.6 - 0.1 0.3 pA Photodiode capacitance * 4 Cph - 20 - - 10 - pF Saturation exposure * 4, *5 E s a t -9 0- -9 0-m lx · s Saturation output charge * 4 Qsat - 50 - - 25 - pC Photo response non-uniformity * 6 P R N U -- ± 3 -- ± 3% *4: Vb=2.0 V, Vφ=5.0 V *5: 2856 K, tungsten lamp *6: 50 % of saturation, excluding the start pixel and last pixel I Electrical characteristics (Ta=25 °C) High Vφ1, Vφ2 (H) 4.5 5 10 4.5 5 10 VClock pulse (φ1, φ2) voltage Low Vφ1, Vφ2 (L) 0- 0 . 4 0- 0 . 4 V High Vφs (H) 4.5 Vφ1 10 4.5 Vφ1 10 VStart pulse (φst) voltage Low Vφs (L) 0 - 0.4 0 - 0.4 V Saturation control gate voltage Vscg - 0 - - 0 - V Saturation control drain voltage Vscd - Vb - - Vb - V Clock pulse ( φ1, φ2) rise / fall time *8 trφ1, trφ2 tfφ1, tfφ2 - 20 - - 20 - ns Clock pulse (φ1, φ2) pulse width tpw φ1, tpwφ2 200 - - 200 - - ns Start pulse (φst) rise / fall time trφs, tfφs - 20 - - 20 - ns Start pulse (φst) pulse width tpw φs 200 - - 200 - - ns Start pulse (φst) and clock pulse (φ2) overlap tφov 200 - - 200 - - ns Clock pulse space *8 X1, X2 trf - 20 - - trf - 20 - - ns Data rate *9 f 0.1 - 2000 0.1 - 2000 kHz - 120 (-256 Q) -- 150 (-512 Q) -n sVideo delay time tvd 50 % of saturation - 36 (-256 Q) - - 50 (-512 Q) - pFClock pulse (φ1, φ2) line capacitance Cφ 5 V bias - 20 (-256 Q) -- 24 (-512 Q) -p FSaturation control gate (Vscg) line capacitance Cscg 5 V bias - 11 (-256 Q) - - 16 (-512 Q) - pFVideo line capacitance CV 2 V bias *7: Vφ is input pulse voltage (refer to figure 8). *8: trf is the clock pulse rise or fall time. A clock pulse space of “rise time/fall time - 20 ” ns (nanoseconds) or more should be input if the clock pulse rise or fall time is longer than 20 ns (refer to figure 7). *9: Vb=2.0 V, Vφ=5.0 V *10: Measured with C7883 driver circuit.