S7017-1008

S7017 HAMAMATSU | Alldatasheet

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S7017 series is a family of FFT-CCD area image sensors specifically designed for low-light-level detection in scientific applications. By using the binning operation, S7017 series can be used as a linear image sensor having a long aperture in the direction of the device length. This makes S7017 series ideally suited for use in spectrophotometry. The binning operation offers significant improvement in S/N and signal processing speed compared with conventional methods by which signals are digitally added by an external circuit. S7017 series also features low noise and low dark signal (MPP mode operation). These enable low-light-level detection and long integration time, thus achieving a wide dynamic range. A four-stage Peltier element is built into the same package for thermoelectric cooling. At room temperature operation, the device can be cooled down to -70 ˚C with using forced air cooling. In addition, since both the CCD chip and Peltier element are hermetically sealed, no dry air is required, thus allowing easy handling. Features Applications IMAGE SENSOR CCD area image sensor Four-stage TE-cooled, front-illuminated FFT-CCDs S7017 series I Selection and order guide Type No. Cooling Number of total pixels Number of active pixels Active area [mm (H) × mm (V)] S7017-1007 1044 × 128 1024 ×124 24.576 × 2.976 S7017-1008 Four-stage TE-cooled 1044 × 256 1024 × 252 24.576 × 6.048 S7017 series has a hermetically-sealed package with AR-coated sapphire window. I General ratings Parameter Specification CCD structure Full frame transfer Fill factor 100 % Number of active pixels S7017-1007: 1024 (H) × 124 (V) S7017-1008: 1024 (H) × 252 (V) Pixel size 24 (H) × 24 (V) µm Active area S7017-1007: 24.576 (H) × 2.976 (V) mm S7017-1008: 24.576 (H) × 6.048 (V) mm Vertical clock phase 2 phase Horizontal clock phase 2 phase Output circuit One-stage MOSFET source follower Package 28 pin metal package Window AR coated Sapphire G 1024 (H) × 124 (V) and 1024 (H) × 252 (V) pixel format G Pixel size: 24 × 24 µm G 100 % fill factor G Wide dynamic range G Low dark current G Low readout noise G MPP operation G Four-stage TE-cooled G Astronomy G Scientific measuring instrument G Fluorescence spectrometer G Raman spectrophotometer G Optical and spectrophotometric analyzer G For low-light-level detection requiring

CCD area image sensor S7017 series I Absolute maximum ratings (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Operating temperature Topr -50 - +30 °C Storage temperature Tstg -100 - +70 °C OD voltage V OD -0.5 - +25 V RD voltage VRD -0.5 - +18 V ISV voltage V ISV -0.5 - +18 V ISH voltage VISH -0.5 - +18 V IGV voltage V IG1V, VIG2V -10 - +15 V IGH voltage VIG1H, VIG2H -10 - +15 V SG voltage V SG -10 - +15 V OG voltage VOG -10 - +15 V RG voltage V RG -10 - +15 V TG voltage VTG -10 - +15 V Vertical clock voltage V P1V, VP2V -10 - +15 V Horizontal clock voltage VP1H, VP2H -10 - +15 V I Operating conditions (MPP mode, Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Output transistor drain voltage V OD 18 20 22 V Reset drain voltage VRD 11.5 12 12.5 V Output gate voltage V OG 135 V Substrate voltage VSS - 0 - V Test point (vertical input source) V ISV -V RD -V Test point (horizontal input source) VISH - VRD - V Test point (vertical input gate) V IG1V, VIG2V -8 0 - V Test point (horizontal input gate) VIG1H, VIG2H -8 0 - V High V P1VH, VP2VH 468Vertical shift register clock voltage Low V P1VL, VP2VL -9 -8 -7 V High VP1HH, VP2HH 4 6 8Horizontal shift register clock voltage Low VP1HL, VP2HL -9 -8 -7 V High V SGH 468Summing gate voltage Low V SGL -9 -8 -7 V High VRGH 4 6 8Reset gate voltage Low VRGL -9 -8 -7 V High V TGH 468Transfer gate voltage Low V TGL -9 -8 -7 V I Electrical characteristics (Ta=25 °C) Parameter Symbol Remark Min. Typ. Max. Unit Signal output frequency fc - - 80 2,000 kHz Reset clock frequency frg - - 80 2,000 kHz S7017-1007 - - 3,200 -Vertical shift register capacitance S7017-1008 CP1V, CP2V - - 6,400 - pF Horizontal shift register capacitance CP1H, CP2H - - 300 - pF Summing gate capacitance C SG --7- p F Reset gate capacitance CRG - - 7 - pF Transfer gate capacitance C TG - - 150 - pF Transfer efficiency CTE *1 0.99995 0.99999 - - DC output level Vout * 2 12 15 18 V Output impedance Zo *2 - 3 - kΩ Power dissipation P * 2, *3 -1 5- m W *1: Charge transfer efficiency per pixel, measured at half of the full well capacity. *2: VOD=20 V , Load resistance=22 kΩ *3: Power dissipation of the on-chip amplifier.

CCD area image sensor S7017 series I Electrical and optical characteristics (Ta=25 °C, unless otherwise noted) Parameter Symbol Remark Min. Typ. Max. Unit Saturation output voltage Vsat - - Fw × Sv - V Vertical 150 300 -Full well capacity Horizontal Fw *4 300 600 - ke- CCD conversion efficiency Sv *5 1.8 2.2 - µV/e- +25 °C - 400 3,000 0 °C - 20 150Dark current (MPP mode) -70 °C DS *6 - 0.0015 0.01 e-/pixel/s Readout noise Nr *7 -6 1 2 e-rms Line binning 25,000 75,000 -Dynamic range Area scanning DR *8 12,500 37,500 - - Spectral response range λ - - 400 to 1,100 - nm Photo response non-uniformity PRNU *9 - - ±10 % Point defects *10 --0 Cluster defects *11 --0Blemish Column defects *12 --0 *4: Large horizontal full well for line binning operation. *5: VOD=20 V , Load resistance=22 kΩ *6: Dark current nearly doubles for every 5 to7 °C increase in temperature. *7: -40 °C, operating frequency is 80 kHz. *8: DR = Fw / Nr *9: Measured at half of the full well capacity. PRNU (%) = noise / signal × 100, noise: fixed pattern noise (peak to peak) *10: White spots > 3 % of full well at 0 °C after Ts=1 s, Black spots > 50 % reduction in response relative to adjacent pixels *11: continuous 2 to 9 point defects *12: continuous >10 point defects I PIN connections Pin No. Symbol Description Remark

1 P- TE-cooler-

3S S Substrate (GND) 4 NC 5I S V Test point (vertical input source) Shorted to RD

6 IG2V Test point (vertical input gate-2) Shorted to 0 V

7 IG1V Test point (vertical input gate-1) Shorted to 0 V

8 RG Reset gate

9 RD Reset drain

10 OS Output transistor source

11 OD Output transistor drain

12 OG Output gate

13 SG Summing gate Same timin g as P2H

14 P+ TE-cooler+

15 TSH1 Temperature sensor (hot side)

16 TSC1 Temperature sensor (cool side)

17 TSC2 Temperature sensor (cool side)

18 P2H CCD horizontal register clock-2

19 P1H CCD horizontal register clock-1

20 IG2H Test point (horizontal input gate-2) Shorted to 0 V

21 IG1H Test point (horizontal input gate-1) Shorted to 0 V

22 ISH Test point (horizontal input source) Shorted to RD

23 P2V CCD vertical register clock-2

24 P1V CCD vertical register clock-1

25 TG Transfer gate Same timing as P2V *13

28 TSH2 Temperature sensor (hot side)

*13: TG is an isolation gate between vertical register and horizontal resister. In st andard operation, the same pulse of P2V should be applied to the TG.

CCD area image sensor S7017 series 400 500 600 700 WAVELENGTH (nm) 800 900 1000 1100 1200 QUANTUM EFFICIENCY (%) (Typ. Ta=25 ˚C) KMPDB0051EA I Spectral response without window 100 (Typ. Ta=25 ˚C) 400 500 600 700 800 WAVELENGTH (nm) TRANSMITTANCE (%) 900 1000 1100 1200 AR COATED SAPPHIRE KMPDB0106EA KMPDA0098EA I Dimensional outline (unit: mm) 4.0 7.0 5.0PINCHED OFF TUBE S7017-1007 TYPE No. 24.576 (H) a S7017-1008 24.576 (H) 2.976 (V) b ACTIVE AREA 6.048 (V) 2.54 27.94 0.46 20.0 b 36.0 44.0 50.0 35.0 6.4 ± 0.5 18.5 ± 0.5 47.0 50.8 0.25 2627 a 1.0PIN No. 1 1st PIN INDEX MARK AR-COATED SAPPHIRE WINDOW I Spectral transmittance characteristic of window material

CCD area image sensor S7017 series KMPDC0085EA I Device structure, line output format V IG1V IG2V ISV SS RG RD OS OD OG SG D1 D10 S1023 S1024 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 11 12 13 36 57 25 24 V=124, 252 H=1024 ISH IG1H IG2HP1HP2H 201918

4 BLANK4 BLANK

4 OPTICAL

2 ISOLATOIN 2 ISOLATOIN

G Area scanning 1 (low dark current mode) INTEGRATION PERIOD (Shutter must be open) P1V RG OS P2V, TG P1H P2H, SG READOUT PERIOD (Shutter must be closed) ENLARGED VIEW 4..127 4..255 128← 124+4 (ISOLATION) 256← 252+4 (ISOLATION) : S7017-1007 : S7017-1008 Tpwv Tovr Tpwr D1 D2 D3 D4 D18 D19 D20 P2V, TG P1H P2H, SG RG OS Tpwh, Tpws 123 Pixel format Left ← Horizontal Direction → Right Blank Optical Black Isolation Effective Isolation Optical Black Blank 442 1 0 2 4 244 Top ← Vertical Direction → Bottom Isolation Effective Isolation 21 2 4 o r 2 5 22

CCD area image sensor S7017 series Parameter Symbol Remark Min. Typ. Max. Unit Pulse width Tpwv 6 *15 --µ sP1V, P2V, TG Rise and fall time Tprv, Tpfv *14 200 - - ns Pulse width Tpwh 250 - - ns Rise and fall time Tprh, pfh 10 - - nsP1H, P2H Duty ratio - *14 - 50 - % Pulse width Tpws 250 - - ns Rise and fall time Tprs, Tpfs 10 - - nsSG Duty ratio - -5 0- % Pulse width Tpwr 100 - - nsRG Rise and fall time Tprr, Tpfr - 5 - - ns TG – P1H Overlap time Tovr - 3 - - µs *14: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. *15: In case of S7017-1007. KMPDC0100EA G Area scanning 2 (large full well mode) INTEGRATION PERIOD (Shutter must be open) P1V RG OS P2V, TG P1H P2H, SG READOUT PERIOD (Shutter must be closed) ENLARGED VIEW 4..127 4..255 128← 124+4 (ISOLATION) 256← 252+4 (ISOLATION) : S7017-1007 : S7017-1008 Tpwv Tovr Tpwr D1 D2 D3 D4 D18 D19 D20 P2V, TG P1H P2H, SG RG OS Tpwh, Tpws 123 Parameter Symbol Remark Min. Typ. Max. Unit Pulse width Tpwv 6 *17 --µ sP1V, P2V, TG Rise and fall time Tprv, Tpfv *16 200 - - ns Pulse width Tpwh 250 - - ns Rise and fall time Tprh, Tpfh 10 - - nsP1H, P2H Duty ratio - *16 - 50 - % Pulse width Tpws 250 - - ns Rise and fall time Tprs, Tpfs 10 - - nsSG Duty ratio - -5 0- % Pulse width Tpwr 100 - - nsRG Rise and fall time Tprr, Tpfr - 5 - - ns TG - P1H Overlap time Tovr - 3 - - µs *16: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. *17: In case of S7017-1007.

CCD area image sensor S7017 series KMPDC0087EA G Line binning Parameter Symbol Remark Min. Typ. Max. Unit Pulse width Tpwv 6 *19 --µ sP1V, P2V, TG Rise and fall time Tprv, Tpfv *18 200 - - ns Pulse width Tpwh 250 - - ns Rise and fall time Tprh, Tpfh 10 - - nsP1H, P2H Duty ratio - *18 - 50 - % Pulse width Tpws 250 - - ns Rise and fall time Tprs, Tpfs 10 - - nsSG Duty ratio - -5 0- % Pulse width Tpwr 100 - - nsRG Rise and fall time Tprr, Tpfr - 5 - - ns TG – P1H Overlap time Tovr - 3 - - µs *18: Symmetrical pulses should be overlapped at 50 % of maximum amplitude. *19: In case of S7017-1007. I Specifications of built-in TE-cooler Parameter Symbol Condition Min. Typ. Max. Unit Internal resistance Rint Ta=27 °C - 1.6 - Ω Maximum current *20 Imax Th *21=27 °C ∆T *22=∆ Tmax - - 4.4 A Maximum voltage Vmax Th*21=27 °C ∆T=∆Tmax I=Imax -- 7 . 4 V Maximum heat absorption *23 Qmax Tc *24=Th *21=27 °C I=Imax - - 3.0 W Maximum temperature at hot side - - - 50 °C CCD temperature - Ta=25 °C - -70 -50 °C *20: If the current is greater than Imax, the heat absorption begins to decrease due to the Joule heat. It should be noted that this value is not a damage threshold. To protect the thermoelectric cooler (Peltier element) and maintain stable operation, the supply current should be less than 60 % of this maximum current. *21: Temperature at hot side of thermoelectric cooler. *22: ∆T=Th - Tc *23: This is a theoretical heat absorption level that offsets the temperature difference in the Peltier element when the maximu m current is supplied to the unit. *24: Temperature at cool side of thermoelectric cooler. INTEGRATION PERIOD (Shutter must be open) VERTICAL BINNING PERIOD (Shutter must be closed) 3..126 3..254 127 255 128← 256← P1V P2V, TG P1H P2H, SG READOUT PERIOD (Shutter must be closed) 124+4 (ISOLATION): S7017-1007 252+4 (ISOLATION): S7017-1008 Tpwv Tovr Tpwh, Tpws Tpwr 123 1043 1044 4..1042 D19D2D1 D20 RG OS

CCD area image sensor S7017 series KMPDB0107EA V - I CCD TEMPERATURE - I VOLTAGE (V) CCD TEMPERATURE ( ˚C) -80 3.02.52.01.5 CURRENT (A) 1.00.50 -60 -40 -20 (Typ. Ta=25 ˚C) I Specifications of built-in temperature sensors Parameter Symbol Condition Min. Typ. Max. Unit Resistance at cool side Rc T=0 °C - 1,000 - Ω Temperature coefficient of resistance at cool side - - - 0.00375 - Ω /Ω Resistance at hot side Rh T=0 °C - 1,000 - Ω Temperature coefficient of resistance at hot side - - - 0.00385 - Ω /Ω KMPDB0108EA -100 -80 -60 -40 -20 0 20 40 RESISTANCE ( Ω ) 1400 1200 1000 800 600 400 200 TEMPERATURE ( ˚C) (Typ. Ta=25 ˚C) I Precaution for use (electrostatic countermeasures) G Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. G Avoid directly placing these sensors on a work-desk or work-bench that may carry an electrostatic charge. G Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. G Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. I Element cooling/heating temperature incline rate Element cooling/heating temperature incline rate should be set at less than 5 K/min. HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184, http://www.hamamatsu.com Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2005 Hamamatsu Photonics K.K. Cat. No. KMPD1030E07 Apr. 2005 DN8