IS43R32800 ISSI | Alldatasheet
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Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. A 01/14/09 Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat- est version of this device specification before relying on any published information and before placing orders for products. IS43R32800 8Mx32 256Mb DDR Synchronous DRAM FEBUARY 2009 DESCRIPTION: IS43R32800 is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The IS43R32800 achieves very high speed clock rate up to 200 MHz . It is packaged in 144-ball FBGA.
FEATURES
Double data rate architecture; two data transfers • per clock cycle Bidirectional, data strobe (DQS) is transmitted/ • received with data Differential clock input (CLK and /CLK)• DLL aligns DQ and DQS transitions with CLK • transitions edges of DQS Commands entered on each positive CLK edge;• Data and data mask referenced to both edges of • DQS 4 bank operation controlled by BA0, BA1 (Bank • Address) /CAS latency –2.0/2.5/3.0 (programmable)• Burst length - 2/4/8 (programmable) • Burst type - Sequential/ Interleave (program-• mable) Auto precharge / All bank precharge controlled • by A8 4096 refresh cycles/ 64ms (4 banks concurrent • refresh) Auto refresh and Self refresh• Row address A0-11/ Column address A0-7, A9-• SSTL_2 Interface Package 144-ball FBGA• Available in Industrial Temperature• Temperature Range: • Commercial (0 oC to +70oC) ADDRESS TABLE Parameter 8M x 32 Configuration 2M x 32 x 4 banks Bank Address Pins BA0, BA1 Autoprecharge Pins A8/AP Row Addresses A0 – A11 Column Addresses A0 – A7, A9 Refresh Count 4096 / 64ms KEY TIMING PARAMETERS Parameter -5 -6 -75 Unit Clk Cycle Time CAS Latency = 3 5 6 7.5 ns CAS Latency = 2.5 5 6 7.5 ns CAS Latency = 2 7.5 7.5 7.5 ns Clk Frequency CAS Latency = 3 200 167 143 MHz CAS Latency = 2.5 200 167 143 MHz CAS Latency = 2 143 143 143 MHz Access Time from Clock CAS Latency = 3 +0.70 +0.70 +0.70 ns CAS Latency = 2.5 +0.70 +0.70 +0.70 ns CAS Latency = 2 +0.75 +0.75 +0.70 ns
2 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 /CS/ RAS /CAS /WED M0-3 Memory Array Ba nk #0 DQ 0- 31 I/OB uffer Memory Array Ba nk #1 Memory Array Ba nk #2 Memory Array Ba nk #3 Mode Re gister ControlC ircu itry Addres sB uffer A0-11 BA 0,1 Cl ockB uffer ControlS ignalB uffer DQ SB uffer DQS0 -3 DLL CLK /CLK CKE FUNCTIONAL BLOCK DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. A 01/14/09 IS43R32800 CLK, /CLK : Ma ster Cl ock CKE: Clock En able /CS: Ch ip Select /RAS : Ro w Address Strobe /CAS : Column A ddress Strobe /WE: Wr ite Enab le A0-11 : Address Input BA 0,1: Ba nk A ddress Input VDD : Power Supply VDDQ : Power Supply for Output Vs s: Ground VssQ : Ground for Output DQ 0-31 : Data I/O DM 0-3 : Write Mask VREFCK EA8 /APA7A6A4A3A1A0BA 0NC/CS M NC/CLKCL KNCA5A9A1 1A2BA 1NCNC/R AS L NCNCVD DVSSNCVD DVD DA1 0VSSVD D/WE/CASK DQ 8DQ 9VDDQVSSQVSSVSSVSSVSSVSSQVDDQDQ 23DQ 22J DQ 10DQ 11VDDQVSSQVSSVSSVSSVSSVSSQVDDQDQ 20DQ 21H DQS1DM1NCVSSQVSSVSSVSSVSSVSSQNCDM2DQS2G DQ 12DQ 13VDDQVSSQVSSVSSVSSVSSVSSQVDDQDQ 18DQ 19F DQ 14DQ 15VDDQVSSQVSSVSSVSSVSSVSSQVDDQDQ 16DQ 17E DQ 24VDDQVD DVSSVSSQVSSVSSVSSQVSSVD DVDDQDQ 7D DQ 25DQ 26VSSQVSSQVSSQVD DVD DVSSQVSSQVSSQDQ 5DQ 6C DQ 27VDDQNCVDDQDQ 30VDDQVDDQDQ 1VDDQNCVDDQDQ 4B DQS3DM3VSSQDQ 28DQ 29DQ 31DQ 0DQ 2DQ 3VSSQDM0DQS0A 121110987654321 DQ S0-3 : Data Strobe VREF : Reference Voltage PIN CONFIGURATION Package Code: B 144-ball FBGA (Top View) (12.00mm x 12.00mm Body, 0.8mm Ball Pitch PIN DESCRIPTIONS
4 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 CL K, /CLK Inpu t Cl ock: CL Ka nd /CLK aredifferentialc lock inputs.A ll addressa nd cont rol inputs ignals ares ampled on thec rossingo ft he positive edge of CL Ka nd negative edgeof /CLK .O utput( read)d atai sr eferencedt ot he crossingso f CL Ka nd /CLK (bothd irections of crossing). CK EI nput Cl ockE nable: CK Ec ontrolsi nternalc lock.W henC KE is low, internal clock fort he followingc ycle is ceased.C KE is also used to select auto/s elfr efresh. Af ters elfr efresh mode is started, CK Eb ecomes asynchronous input. Self refresh is maintained as long as CK Ei sl ow. /CSI nput Ch ip Select:W hen/ CS is high,a ny commandm eans No Operation. /RAS ,/ CAS, /WEI nput Comb inationo f/ RA S, /CAS ,/ WE definesb asic commands. A0-11I nput A0-11s pecify theR ow /C olumnA ddress in conjunctionw ithB A0,1.T he RowA ddressi ss pecified by A0-11. TheC olumnA ddress is specified by A0-7,A 9. A8 is also used to indicate precharge option.W henA 8i s high at ar ead/ writec ommand,a na utoprecharge is performed. When A8 is high at ap recharge command, allb anks areprecharge d. BA 0,1 Inpu t DQ0-31 Input/O utput DQS0- 3 VDD, Vs s PowerS upply PowerS upply fort he me mory arraya nd peripheral circuitry. VDDQ ,V ssQ PowerS upply VDDQ andV ssQa re suppliedt othe Output Bufferso nly. Bank Address: BA 0,1s pecifies oneo ff ourb anks to whicha command is applied. BA 0,1m ustbes et with ACT, PR E, READ, WR IT Ec ommands. Data Input/Out put:D atab us Data Strobe:O utputwith read data,i nputwith write data.E dge-aligned with read data,c enteredi nw rite data.U sedt oc apture writedata. DQS 0f or DQ0- DQ7, DQS 1f or DQ8- DQ15, DQS2 forD Q16- DQ23, DQS3 for DQ24- DQ31. SYMBOL TYPE DESCRIPTION DM0- 3 Inpu t InputD ataM ask: DM is an inputmask signal forw rite data.I nput data is masked when DM is samp ledH IG Ha long with that inputd ata duringa WR IT Ea ccess. DM is samp ledo n bothe dgeso fD QS. Al thoughDM pins arei nput only,t he DM loadingm atches theD Q and DQS loading. DM 0f or DQ0 - DQ7,D M1 for DQ8 - DQ15, DM 2f or DQ16- DQ23, DM 3f or DQ24- DQ31. Input/ Output Vref Input SST L_ 2r eferencevoltage. PIN FUNCTIONS
Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. A 01/14/09 IS43R32800 ISSI's 256-Mbit DDR SDRAM provides basic functions, bank (row) activate, burst read / write, bank (row) precharge,a nd auto /s elfr efresh.E achc ommand is definedb yc ontrol signalso f/ RA S, /CAS and /WEa tC LK rising edge.I na dditiont o3s ignals,/ CS ,C KE andA 8a re usedas chip select,r efresh option,a nd prechargeoption,r espectively. To know thed etailedd efinitiono fc ommands, please seet he commandt ruthtable. /CS Chip Select :L =select, H=deselect /RAS Command /CAS Command /WE Command CK E RefreshO ption@ refreshc ommand A8 PrechargeO ption@ prechargeo rr ead/writec ommand CL K define basicc ommands /CLK Activate( ACT) [/RA S= L, /CAS =/WE =H] AC Tc ommand activatesa rowi na ni dleb anki ndicatedby BA . Read (R EAD) [/RAS =H,/ CA S= L, /WE= H] RE AD commands tartsb urst read from thea ctiveb anki ndicatedby BA .F irst output data appearsa fter /CAS latency. When A8 =H at this command, theb anki sd eactivatedaftert he burstr ead( auto- precharge READ A ) Write( WRITE) [/RA S= H, /CAS =/WE =L ] WR IT Ec ommand starts burstw rite to thea ctiveb anki ndicatedby BA .T otal data length to be written is setb yb urst length.W henA 8= Ha tt hisc ommand,t he bankis deactivateda fter theb urst write (auto-precharge ,WRITEA ) Precharge (PRE )[ /RAS =L ,/ CA S= H, /W E= L] PR Ec ommand deactivatest he activeb anki ndicated by BA .T hisc ommand also terminates burstr ead /write operation. When A8 =H at this command, allb anks ared eactivated(precharge all, PREA ). Auto-Ref resh( REFA )[ /RAS =/CA S= L, /WE= CK E= H] RE FA commands tartsa uto-refreshc ycle.R efresh addressi ncluding bankaddressa re generated internally.A fter this command,t he banksa re precharged automatically. FUNCTIONAL DESCRIPTION
6 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 H=High Level, L=LowL evel,V =Valid,X =Don't Care,n =CLK cyclenumber NOTE: 1. Appliesonlyt or eadb urstsw itha utoprecharge disabled;t hiscommand is undefined( andshouldn ot beused)f or read bursts with autoprecha rgeenabled,a nd forw rite bursts. 2. BA0-BA1s electe ithert he Baseor theE xtendedM odeR egister( BA0= 0, BA1= 0s elects Mode Register;BA0=1 , BA1= 0selects Extended Mode Register;o ther combinations of BA0-BA1a re reserved;A 0-A11p rovide the op-codet ob ew rittent ot he selectedMode Register. COMMAND MNEMONIC CKE n-1 CKE n /CS/ RAS/ CAS/ WE BA0,1 A8 /AP A0-7, A9-11 Deselect DESELH XHXXX XX X No Operation NOP HXL HHHXX X RowA ddressE ntry & Bank Activate ACT HHL LH HV VV Single Bank Precha rge PRE HHL LH LV LX Prech argeAllB anks PREA HHL LH LH X ColumnAddressEntry &W rite WRITE HHL HL LV LV ColumnAddressEntry &W rite with Auto-Precharge WRITEA HHL HL LV HV ColumnAddressEntry &R ead READ HHL HL HV LV ColumnAddressEntry &R eadw ith Auto-Precharge READA HHL HL HV HV Auto-Refresh REFA HHL LL HX XX Self-RefreshEntryR EFSH LL LL HX XX Self-RefreshExit REFSX LH HX XX XX X LH LH HHXX X BurstT erminate TERM HHL HHLX XX ModeRegisterSetM RS HHL LL LL LV X note COMMAND TRUTH TABLE
Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. A 01/14/09 IS43R32800 CurrentS tate /C S/ RAS/ CAS/ WE AddressC ommand Action Notes IDLE HX XX XD ES EL NO P LH HH XN OP NO P LH HL BA TERMI LLEGAL 2 LH LX BA ,C A, A8 RE AD /W RITE ILLEGAL 2 LL HH BA ,R AA CT Bank Active,L atch RA LL HL BA ,A 8P RE /P RE AN OP 4 LL LH XR EF AA uto-Refresh LL LL Op-C ode, Mode- Add MR SM odeR egisterS et 5 ROWA CT IV EH XX XX DESE LN OP LH HH XN OP NO P LH HL BA TER MI LLEGA L LH LH BA ,C A, A8 RE AD /R EADA BeginR ead,L atch CA ,D et ermine Auto-Prech arge LH LL BA ,C A, A8 WR ITE/ WR ITEA BeginW rite,L atch CA ,D etermine Auto-Prech arge LL HH BA ,R AA CT Bank Active /I LLEG AL 2 LL HL BA ,A 8P RE /P RE AP rech arge/P rech argeAll LL LH XR EF AI LLE GA L LL LL Op-C ode, Mode- Add MR SI LLE GA L HX XX XD ES EL NOP (C ontinueBursttoE ND ) LH HH X NOP NO P( ContinueBursttoE ND ) LH HL BA TER MT erminateBurst LH LH BA ,C A, A8 RE AD /R EA DA TerminateB urst,L atch CA ,B egin NewR ead,D etermineAuto- Precharge LH LL BA ,C A, A8 WR IT E/ WR ITEA ILLE GA L LL HH BA ,R AA CT Bank Active /I LLE GAL 2 LL HL BA ,A 8P RE /P RE AT erminateBurst, Precharge LL LH XR EF AI LLEGAL LL LL Op-C ode, Mode- Add MR SI LLEGAL RE AD(Auto- Prech arge Disabled) FUNCTIONAL TRUTH TABLE
8 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 CurrentS tate /C S/ RAS/ CAS/ WE AddressC ommand Action Notes HX XX XD ES EL NO P( ContinueBursttoE ND ) LH HH XN OP NO P( ContinueBursttoE ND ) LH HL BA TERM IL LE GAL LH LH BA ,C A, A8 READ /R EADA TerminateB urst,L atchCA ,B egin Read,D etermineAuto-Prech arge 3 LH LL BA ,C A, A8 WR ITE/ WR IT EA TerminateB urst,L atchCA ,B egin Write, DetermineA uto-Precharge 3 LL HH BA ,R AA CT Bank Active /I LLE GAL 2 LL HL BA ,A 8P RE /P RE AT erminateBurst, Precharge LL LH XR EF AI LL EGAL LL LL Op-C ode, Mode- Add MR SI LL EGAL HX XX XD ES EL NO P( ContinueBursttoE ND ) LH HH XN OP NO P( ContinueBursttoE ND ) LH HL BA TERM ILLEGAL LH LH BA ,C A, A8 READ /R EADA ILLEGAL LH LL BA ,C A, A8 WRIT E/ WR IT EA IL LEGAL LL HH BA ,R AA CT Bank Active /I LLEGAL 2 LL HL BA ,A 8P RE /P RE AP recharge/I LLEGAL 2 LL LH XR EF AI LLEGAL LL LL Op-C ode,M ode- Add MR SI LLEGAL HX XX XD ES EL NOP (ContinueB urst to END) LH HH XN OP NOP (ContinueB urst to END) LH HL BA TERM ILLEGAL LH LH BA ,C A, A8 READ /R EADA ILLEGAL LH LL BA ,C A, A8 WR IT E/ WR ITEA ILLEGAL LL HH BA ,R AA CT Bank Active /I LLEGAL 2 LL HL BA ,A 8P RE /P RE AP recharge/I LLEGAL 2 LL LH XR EF AI LLEGAL LL LL Op-C ode, Mode- Add MRSI LLEGAL WR IT E(Auto- Precharge Disabled) READ with Auto-P rech arge WRITEw ith Auto-P rech arge FUNCTIONAL TRUTH TABLE (continued)
Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. A 01/14/09 IS43R32800 CurrentState/ CS /RAS /CAS /WEA ddressC ommand Action Notes HX XX XD ES EL NOP (I dlea fter tRP) LH HH X NOP NOP (I dlea fter tRP) LH HL BA TERM IL LEGAL 2 LH LX BA ,C A, A8 READ /W RITE IL LEGAL 2 2LL HH BA ,R AA CT IL LE GA L LL HL BA ,A 8P RE /P RE A NOP (I dlea fter tRP) 4 LL LH XR EF AI LLEGAL LL LL Op-C ode,M ode- Add MRSI LLEGAL HX XX XD ES EL NOP (R ow Active aftert RC D) LH HH X NOP NOP (R ow Active aftert RC D) LH HL BA TERM IL LEGAL 2 LH LX BA ,C A, A8 READ /W RITE IL LEGAL 2 2LL HH BA ,R AA CT IL LEGA L LL HL BA ,A 8P RE /P RE AI LLEGAL 2 LL LH XR EF AI LLEGAL LL LL Op-C ode,M ode- Add MR SI LLEGAL HX XX XD ES EL NOP LH HH X NOP NOP LH HL BA TERM IL LE GA L LH LX BA ,C A, A8 READ /W RITE IL LEGA L LL HH BA ,R AA CT IL LEGA L LL HL BA ,A 8P RE /P RE AI LLEGAL 2 LL LH XR EF AI LLEGAL LL LL Op-C ode,M ode- Add MRSI LLEGA L ROW ACTI VATING WRITER E- COVERING PR E- C HARGI NG FUNCTIONAL TRUTH TABLE (continued)
10 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 ABBREVIATIONS : H=Hi gh Level, L= LowL evel,X =Don't Care BA =BankA ddress,R A=RowA ddress, CA =ColumnA ddress, NOP =NoO peration NOTES : 1. Al le ntries assume that CK Ew as Hi gh during thep receding clockc ycle andt he currentc lock cycle. 2. ILLEGAL to bank in specifieds tate;f unctionm ay be legali nt he bank indicatedb yB A, de pendingo nt he stateo f that bank. 3. Must satisfyb us contention,b us turn around,w rite recovery requirements. 4. NOP to bank precharging or in idle state. Mayp recharge bank indicatedb yB A. 5. ILLEGAL if anyb anki sn ot idle. ILLEGA L= Device operationa nd/ord ata-integrity aren ot guaranteed. CurrentState/ CS /RAS /CAS /WEA ddress Command Action REFRESHING HX XX XD ES EL NO P( Idle aftert RC ) LH HH XN OP NO P( Idle aftert RC ) LH HL BA TERM ILLEGAL LH LX BA ,C A, A8 READ /W RI TE ILLEGAL LL HH BA ,R AA CT ILLEGAL LL HL BA ,A 8P RE /P RE A ILLEGAL LL LH XR EF A ILLEGAL LL LL Op-C ode, Mode- Add MRS ILLEGAL HX XX XD ES EL NO P( RowA ctivea fter tRSC ) LH HH XN OP NO P( RowA ctivea fter tRSC ) LH HL BA TERM ILLEGAL LH LX BA ,C A, A8 READ /W RI TE ILLEGAL LL HH BA ,R AA CT ILLEGAL LL HL BA ,A 8P RE /P RE A ILLEGAL LL LH XR EF A ILLEGAL LL LL Op-C ode,M ode- Add MR S ILLEGAL MODE REGISTER SETTING FUNCTIONAL TRUTH TABLE (continued) Notes
Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. A 01/14/09 IS43R32800 ABBR EVIATI ONS : H=Hi gh Level, L= LowL evel,X =Don't Care NOTES : 1. CKEL ow to Hi gh transition will re-enableC LK ando ther inputs asynchronously. Am inimum setupt imem ustb es atisfied before anyc ommand othert hanE XIT. 2. Power-Down andS elf-Refreshc an be enteredo nlyf romt he Al lB anks Idle State. 3. Must be legalc ommand. CurrentState CKEn-1 CKEn /CS/ RAS/ CAS/ WE AddressA ctionN otes HX XX XX XI NV ALID 1 LH HX XX XE xitS elf-Refresh( Idle aftert RC )1 LH LH HH XE xitS elf-Refresh( Idle aftert RC )1 LH LH HL XI LL EGAL 1 LH LH LX XI LL EGAL 1 LH LL XX XI LL EGAL 1 LL XX XX XN OP (MaintainS elf-Refresh) 1 HX XX XX XI NV AL ID LH XX XX XE xitP ower Downto Idle LL XX XX XN OP (MaintainS elf-Refresh) HH XX XX XR eferto FunctionTruthT able 2 HL LL LH XE nter Self-R efresh 2 HL HX XX XE nter PowerD own2 HL LH HH XE nter PowerD own2 HL LH HL XI LL EGAL 2 HL LH LX XI LL EGAL 2 HL LL XX XI LL EGAL 2 LX XX XX XR eferto CurrentState= PowerD own2 HH XX XX XR eferto FunctionTruthT able HL XX XX XB egin CL KS uspendat Next Cycle3 LH XX XX XE xitC LK Suspenda tN extC ycle 3 LL XX XX XM aintainC LK Suspend ANYS TATE othert hanlisted above SELF - REFR ESHING POWER DOWN ALLB ANKS IDLE CKE TRUTH TABLE
12 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 RO W AC TI VE ID LE PR E CH AR GE POWER DOW N RE AD RE ADA WR IT E WR IT EA POWER ON AC T REFA REFS REFSX CKEL CKEH MR S CKEL CKEH WR IT E RE AD WR IT EA WR IT EA RE AD A RE AD PR E RE AD A RE AD A PR E PR E PREA POWE R APPL IE D MODE REGISTER SE T SE LF RE FR ES H AU TO RE FR ES H Active Power Down AutomaticS equence Command Sequence WR IT E RE AD PR E CH AR GE AL L MR S BU RS T ST OP TE RM STATE DIAGRAM
Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. A 01/14/09 IS43R32800 DC OPERATINGC ONDITIONS (Ta=0~70oC Min. Typ. Max. SupplyV oltage 2.3 2.5 2.5 2.7 V SupplyV oltage forO utput 2.3 2.7 V High-LevelI nput Voltage VREF+0.15V DD+0.3 V Low-LevelI nputVoltage -0.3 VREF-0.15 V InputL eak ageC urrent Anyi nput0V<VIN< VDD (A ll otherp insn ot undert est= 0V ) -2 2 uA OutputL eak ageC urrent:DQa re disabled:0V< Vout<VDDQ -5 5 uA 2.4 V 0.4 V NotesLimits Unit OutputLevels: Output Hi ghVoltage( Iout=-4mA) OutputLowV oltage(I out=4mA) Parameter Symbol Parameter ConditionsR atings Unit VDD SupplyV oltage with respectt oV ss -0.5 ~3 .7 V VDDQ Supply Voltagef or Output with respectt oV ssQ- 0.5~ 3.7V VI InputV oltage with respectt oV ss -0.5 ~V dd+0.5V VO Output Voltagew ithr espect toVs sQ -0.5 ~V ddQ+0.5V IO Output Current5 Pd PowerD issipation Ta =2 5 o C 2000 mW Topr Op Commercial I eratingT emperature 0 to +70 o C Ts tg StorageT emperature -65~ 150 o C ABSOLUTE MAXIMUM RATINGS CAPACITANCE CHARACTERISTICS VDD = VDDQ =2 .5V+ 0.2V,V ss =V ssQ= 0V ,u nlesso therwise noted) Min. Max. CI (A )I np utCapacitance, addressp in VI =1.25V 1.2 2.2 pF CI (C )I nputC ap acitance, controlp in f=100MHz 1.2 2.2 pF CI (K )I np utCapacitance, CL Kp in VI= 25mVr ms 1.2 2.2 2.2 0.25 pF 4.2 1.3 pFCI /O I/OC ap acitance, I/O, DQ S, DM pin 0.75 Note sLimitsSymbol Parameter TestCondition UnitDelta Cap.(Max.) 50 mA -5, -6, -75 -5, -6, -75
14 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 -5 -6 -7 5 IDD1 OPER ATINGC URRENT :O neBank;A ctive-Read-Precharge ;Burst =2 ; tRC=t RC MI N; tC K= tC KM IN;I OUT =0 mA;A ddressa ndcontrol inputsc hangingoncep er clockc ycle 250 230 230 IDD5 AUTO REFRESH C URRENT :t RC =t RF C( MI N) 250 240 240 IDD6 SELF REFRESH C URRENT :C KE < 0.2V 5 5 5 ACTIVE STANDB YC URRE NT:/ CS > VI H( MI N) ;C KE > VI H( MI N) ; Oneb ank; Active-Precharge;t RC =t RA SM AX ;t CK =t CK MI N; DQ,DM andDQS inputsc hangingt wice perc lock cycle; addressa ndother controli nputsc hanging once per clockc ycle IDD3N IDD2P IDD2N IDLE STANDB YC URRENT :/ CS > VI H( MI N) ;A ll banksi dle; CK E> VI H( MI N) ;t CK =t CK MI N; Addressa ndotherc ontrol inputs changingonce perc lock cycl e IDD3P ACTIVE POWE R DOW NS TANDB YC URRENT :O ne bankactive;power downmode;CKE < VI L( MAX) ;t CK =t CK MI N 360 360 Limits(Max.) 100 40 35 360 NotesSymbol Parameter/TestConditions mA Unit IDD4W OPER ATINGC URRENT :B urst =2;W rite ;C ontinuous burst;Allb anks active; Addressa ndcontroli nputsc hangi ngonce perc lock cycle; tC K= t CK MI N; DQ andDQS inputs changingtw icep er clockc ycle PR ECHA RG EP OW ER- DOW NS TANDB YC URRENT :A ll banksi dle; power-downmode; CK E< VI L( MA X) ;t CK =t CK MI N 400 6570 105 IDD4R OPER ATINGC URRENT :B urst =2;R ead; Continuous burst;Allb anks active; Addressa ndcontroli nputsc hangingo ncep er clockc ycle;t CK =t CK MI N; IOUT =0 mA 400 360 100 50 50 VDD = VDDQ =2 .5V+ 0.2V ,V ss =V ssQ= 0V ,O utputO pen, unless otherwisen oted AVERAGE SUPPLY CURRENT FROM VDD
Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. A 01/14/09 IS43R32800 Min. MaxM in.M ax Min. Max CL =3.0 57 .5 61 27 .5 12 ns CL =2.5 51 261 27 .5 12 ns CL =2.0 7. 51 27 .5 12 7. 51 2n s tDSI nputSetuptime( DQ,DM) 0.40 .450 .5 ns tDHI nputHold time(DQ, DM) 0.4 0.45 0.5n s tIPW Control& addressi nputpulsew idth(for eachinput) 2.22 .2 2.2n s tDIPWD Qa ndDM inputpulse width( fore achinput) 1.751 .751 .75n s tHZD ata-out-highimpedancet imef romC LK //CL K +0.70 +0.70+ 0.75 ns 14 tDQS QD QV alid data delayt imef romDQS 0.40 0.45 0.5n s tHPC lock half period tCLminor tCHmin tCLminor tCHmin tCLminor tCHmin ns 20 tQHD Qo utputholdt imef romD QS (per access) tHP-tQHS tHP-tQHS tHP-tQHS ns tQHS Datahold skew factor (for DQS&a ssociat edDQ signals) 0.50 0.55 0.75 tDQS HD QS inputH ighlevelwidth 0.350 .350 .35t CK tDQS LD QS inputL ow levelw idth 0.35 0.35 0.35 tCK tDSS DQSf allingedget oC LK setuptime 0.2 0.20 .2 tCK tDSH DQSf allingedgeholdt imef romC LK 0.20 .2 0.2t CK tMRD Mode Register Setc ommandcyclet ime 222 tCK tWPR ES Writep reambles etuptime 000 ns 16 tWPR EW rite preamble 0.25 0.25 0.25 tCK tISI nputSetuptime( addressa ndcontrol) 0.60 .750 .9 ns 19 tIHI nputHold time(addressa ndcontrol) 0.60 .750 .9 ns 19 tCK Symbol AC Char acteristicsPar am et er -5 Notes-6 CL Kc ycle time -75 Unit AC TIMING REQUIREMENTS
16 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 Output Load Condition DQ OutputTi ming Measurement ReferenceP oint VRE F VRE F DQS V OUT V RE F30pF V TT =V REF Zo=50 Min. MaxM in.M ax Min. Max tRAS RowA ctivet ime 120,000 4240 120,000 45 120, 000n s tRCR ow Cyclet ime(operation) 55 60 65 ns tRFC Auto Ref. to Active/AutoR ef.c ommandperiod 70 72 75 ns tRCD Rowt oC olumnD elay 15 18 20 ns tRPR ow Prechargetime ns tRRD ActtoA ct Delayt ime ns tWRW rite Recovery time 15 15 15 ns tDAL Auto Prech argewriter ecovery +p rech argetime tWR+tRPt WR +tRP tWR+tRPn s tWTR Internal Writet oR eadCommandD elay 21 1t CK tXSN RE xitS elfR ef.t onon-R eadc ommand 75 75 75 ns tXSR DE xitS elfR ef.t o- Read command 200 200 200 tCK tXPN RE xitP ower downtoc ommand 11 1t CK tXPR DE xitP ower downto- Readcommand1 11 tCK1 8 tREF IA veragePeriodic Refreshinterval 15.6 15.6 15.6 - 17 -75 Unit NotesSymbol AC Char act eristicsParameter -5 -6 AC TIMING REQUIREMENTS (Continued) 15 18 20 10 12 15 ms W W
Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. A 01/14/09 IS43R32800 Notes 1. Al l voltagesr eferencedto Vss. 2. Testsf or AC timing,I DD, ande lectrical, AC andD Cc haracteristics,m ay be conducteda tn ominal reference/supply voltage levels,b ut ther elatedspecifications andd eviceo perationa re guaranteed fort he full voltage ranges pecified. 3. AC timing andI DD testsm ay usea VI Lt oV IH swingo fu pt o1 .5Vi nt he test environment, buti nputtimingi ss till referenced to VR EF (ort ot he crossing pointf or CK //CK), andp arameter specific ations are guaranteedfort he specified AC inputl evelsu nder normal usec onditions. Them inimum slew rate fort he inputsignalsi s1 V/ns in the rangebetweenV IL (AC) andV IH (AC) . 4. TheA Ca nd DC inputl evel specifications area sd efined in theS ST L_ 2S tandard (i.e.t he receiver will effectively switcha sa result of thes ignalc rossingthe AC inputl evel,a nd will remain in that statea sl onga st he signal does not ring back above( below) theD Ci nput LO W( HI GH )l evel. 5. VR EF is expected to be equalt o0 .5*VDDQ of thet ransmittingd evice, andt ot rack variations in theD Cl evel of the same.P eak-to-peakn oise on VR EF mayn ot exceed+2% of theD Cv alue. 6. VT Ti sn ot appliedd irectly to thed evice. VT Ti sa system supplyf or signal terminationr esistors,i se xpectedto be sete qualt oV RE F, andm ustt rack variations in theD Cl evel of VR EF . 7. VI Di st he magnitude of thed ifferenceb etween thei nput levelo nC LK andt he inputlevelo n/ CL K. 8. Thev alue of VI Xi se xpectedto equal0 .5*VDDQo ft he transmitting device andm ustt rack variations in theD Cl evel of thes ame. 9. Enableso n-chip refresha nd addressc ounters. 10. ID Ds pecifications aret esteda fter thed evicei sp roperlyi nitialized. VDDQ /2,V OUT( PE AK TO PE AK )= 25mV .D Mi nputsa re groupedw ithI /O pins -r eflectingthe fact that they are matchedi nl oading (tof acili tatetracem atchinga tt he boardl evel). 12. TheC LK// CL Ki nput referencel evel (for timingr eferencedto CL K //CLK )i st he pointa tw hich CL Ka nd /CLK cross; thei nputreferencel evel fors ignals othert hanC LK// CL K, is VR EF . 13. Inputsa re notr ecognized as valid untilV RE Fs tabili zes. Ex ception: during thep eriodb eforeV RE Fs tabilizes, CKE< 0.3VDDQ is recognized as LOW. 14. tH Za nd tLZt ransitions occuri nt he same access time windowsa sv alid data transitions.T hese parameters aren ot referenced to as pecificv oltagelevel, buts pecify when thed eviceo utputis no longer driving( HZ), or begins driving (LZ) . 15. Them aximum limit fort hisp arameteris nota device limit. Thed evicew ill operatew itha greaterv alue fort his parameter, buts ystemp erformance (bus turnaround) will de gradea ccordingly. 16. Thes pecificr equirement is that DQS be vali d( HI GH ,L OW ,o ra ts omep oint on av alid transition)o no rb efore this CL Ke dge.A validt ransitioni sd efined as monotonic, andm eetingt he inputslew rate specifications of thed evice. When no writesw erep reviouslyi np rogresso nt he bus, DQSw il lb et ransitioning from Hi gh-Z to logicL OW .I fa previous write wasi np rogress, DQS couldb eH IG H, LOW, or transitioning from HI GH to LO Wa tt hist ime, de pendingo nt DQSS. 17. Am aximum of eightA UT OR EF RE SH commands can beposted to anyg iven DDR SD RA Md evice. 18. tX PR Ds houldb e 200 tCLK in thec onditiono ft he unstable CL Ko peration during thep ower down mode. 19. Forc ommand/addressa nd CK &/ CK slew rate >1 .0V/ns. 20. Mi n( tCL, tCH) refers to thes mallero ft he actual clockl ow timea nd thea ctualc lock high timea sp rovidedt ot he device. Ti ming patterns: tCK= min,tRRD =2*tCK,B L= 4,tRCD=3 *tCK ,R eadw ith Autoprecharge Read:A 0N A1 R0 A2 R1 NR 3A 0N A1 R 0–r ep eatt he same timing with randoma ddressc ha nging *100% of datachangi ngat everyb urst Legend:A =Activate,R= Read,P=Precharge,N =NOP
18 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 FUNCTIONAL DESCRIPTION The IS43R32800 is a 256Mb DDR SDRAM internally configured as a quad--bank DRAM. These 256Mb device contains 4 banks x 2,097,152 x32 bits. The DDR SDRAM uses a double--data--rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation. INITIALIZATION DDR SDRAMs must be powered up and initialized in a predefined manner. POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a DDR SDRAM from damaged or multi functioning. 1. Apply VDD before or the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL 4. Issue precharge command for all banks of the device 5. Issue EMRS 6. Issue MRS for the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable condition for 200cycles After these sequence, the DDR SDRAM is idle state and ready for normal operation.
Integrated Silicon Solution, Inc. — www.issi.com 19 Rev. A 01/14/09 IS43R32800 /CS /RAS /CAS /WE A11-A0 /CLK V CL K BA 0 BA 1 R: Re served forF utureU se 0N O 1Y ES DL LR eset 0S equential 1I nterleav ed BurstT ype BT =0 BT =1 00 0R R 00 12 2 01 04 4 01 18 8 10 0R R 10 1R R 11 0R R 11 1R R BL Burst Length /CAS La tency 00 0R 00 1R 01 02 01 13 10 0R 10 1R 11 02 .5 11 1R CL Latency Mode BA 1B A0 A1 1A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0000 0D R0 BTLT MODE BL MODE REGISTER DEFINITION REGISTER DEFINITION MODE REGISTER The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure “MODE REGISTER DEFINITION”. The Mode Register is programmed via the MODE REGISTER SET (MRS) command (with BA0 = 0 and BA1 = 0) and will retain stored information until it is programmed again or the device loses power. Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode. The Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. After tMRD from a MRS command the DDR SDRAM is ready for a new command. Violating either of these requirements will result in unspecified operation.
20 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure “CAS LATENCY”. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1--Ai when the burst length is set to two, by A2--Ai when the burst length is set to four and by A3--Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both read and write bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table “BURST DEFINITION”. Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation, or incompatibility with future versions may result.
Integrated Silicon Solution, Inc. — www.issi.com 21 Rev. A 01/14/09 IS43R32800 /CAS La tency Burst Length CL =2 BL =4 Burst Length A2 A1 A0 InitialA ddress BL Sequential Interleaved Column Addressing 00 0 00 1 01 0 01 1 10 0 10 1 11 0 11 1 -0 0 -0 1 -1 0 -1 1 -- 0 01 23 45 67 0123 4 567 12 34 567 01 03 25 476 23 45 670 12 30 16 745 34 56 701 23 21 07 654 45 67 012 34 56 70 12 3 56 70 123 45 47 61 03 2 67 01 234 56 74 52 30 1 70 12 01 23 12 30 23 01 7654 0123 1032 2301 -- 1 345 63 21 0 Command Address DQ YY Read Write DQS Q0 Q1 Q2 Q3 D0 D1 D2 D3 /CLK CL K CAS LATENCY BURST DEFINITION
22 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 /CS /RAS /CAS /WE A11-A0 V BA 0 BA 1 /CLK CL K BA 1B A0 A1 1A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 010000 0000 00 DS DD 0N ormal 1W eak Drive Strength 0D LL Enable 1D LL DisableDL LD isable EXTENDED MODE REGISTER EXTENDED MODE REGISTER The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output drive strength selection (optional). These functions are controlled via the bits shown in Figure EXTENDED MODE REGISTER. The Extended Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. After tMRD from a MRS command the DDR SDRAM is ready for a new command. Violating either of these requirements will result in unspecified operation. DLL Enable/Disable The DLL must be enabled for normal operation. DLL enable is required during power-up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation (upon exiting Self Refresh Mode, the DLL is enabled automatically). Any time the DLL is enabled a DLL Reset must follow and 200 clock cycles must occur before any executable command can be issued. Output Drive Strength The normal drive strength for all outputs is specified to be SSTL_2, Class II. The ISSI DDR SDRAM also supports a weak driver strength option, intended for lighter load and/or point-to-point environments.
Integrated Silicon Solution, Inc. — www.issi.com 23 Rev. A 01/14/09 IS43R32800 /CLK DQ S tIS tIH VREF CL K Va lid Da ta tAC tDQS CK tCLtCHtCK tDQS QtQH tR PR E tR PS T DQ S /CLK CL K tDQS S tDSt DH tDQS L tDQS HtWPR E WriteO peration /t DQSS=max. tDSStWPR ES tWPS T DQ S /CLK CL K tDQS S tDSt DH tDQS Lt DQ SHtWPR E WriteO peration /t DQSS=min. tDSH tWPR ES tWPS T DQ DQ DQ Cm d& Add. Read Operation
24 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 The DDR SDRAMh as four independentb anks.E achb anki sa ctivatedby theA CT co mmandw ith theb anka ddresses( BA 0,1).A rowi si ndicatedby ther ow addressA 0-11. Them inimum activation interval betweenoneb anka nd theo ther bank is tRRD . BANK ACTIVATE TheP RE co mmand deactivates theb anki ndicated by BA 0,1. When multiple banksa re active,t he prechargeallc ommand (PRE A, PRE+ A8=H)i sa vailable to deactivatet hema tt he same time.A fter tRPf romt he precharge, an AC Tc ommand to thes ameb ankc an be issued. PRECHARG E Bank Activation andP rechargeAll( BL=8,C L=2) Ap recharge command canb ei ssueda tB L/2f roma read commandw ithout data loss. Prechargea ll Command A0-7 ,9-11 BA 0,1 DQ AC T Xa Xa RE AD Y AC T Xb Xb PR E tRRD tRCD AC T Xb Xb tRAS tRP tRCmin 2A CT command /t RCmi n DQS Qa0 BL /2 Qa1Q a2 Qa3Q a4 Qa5Q a6 Qa7 /CLK CL K OPERATIONAL DESCRIPTION
Integrated Silicon Solution, Inc. — www.issi.com 25 Rev. A 01/14/09 IS43R32800 Af tert RCD from theb ank activation, aR EA Dc ommand canb ei ssued. 1stO utputd atai sa vailable aftert he /CAS Latencyf romt he RE AD ,f ollowedb y( BL-1 )c onsecutive data when theB urst Length is BL .T he starta ddressi ss pecified by A0-7,9,a nd thea ddresss equenceo fb urst data is definedb y theB urst Ty pe.A RE AD command mayb ea pplied to anya ctiveb ank, so ther ow precharget ime (tRP ) can be hiddenb ehindc ontinuouso utputd atab yi nterleavingt he multiple banks. When A8 is high at aR EA Dc ommand, thea uto-precharge (READA )i sp erformed.A ny command(RE AD ,W RI TE,P RE ,A CT )t ot he same bank is inhibitedt illt he internal prechargei s complete.T he internal precharges tartsa tB L/2a fter RE AD A. Then extA CT co mmandc an be issued after( BL/2+t RP )f romt he previous RE AD A. READ Mu ltiB ankI nterleavingR EA D( BL =8,C L=2) /CLK Command A0-7 ,9-11 BA 0,1 DQ AC T Xa Xa RE AD Y RE AD Y AC T Xb Xb PR E tRCD /CAS latency BurstL ength DQS Qa0 CL K Qa1Q a2 Qa3Q a4 Qa5Q a6 Qa7Q b0 Qb1Q b2 Qb3Q b4 Qb5Q b7 Qb8
26 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 tRCD tRPBL /2 BL /2 +t RP READ withAuto-Precharge(BL=8, CL=2,2.5,3.0) Command A0-7 ,9-11 BA 0,1 DQ AC T Xa Xa RE AD Y DQS /CLK CL K Internal Precharge StartT iming Qa0Q a1 Qa2Q a3 Qa4Q a5 Qa6Q a7 DQ DQS Qa0Q a1 Qa2Q a3 Qa4Q a5 Qa6Q a7 CL =2 CL =2.5 01 234 56 78 91 01 11 2 DQ DQS Qa0Q a1 Qa2Q a3 Qa4Q a5 Qa6Q a7 CL =3.0
Integrated Silicon Solution, Inc. — www.issi.com 27 Rev. A 01/14/09 IS43R32800 Af tert RCD from theb ank activation, aW RI TE command canb ei ssued. 1sti nput data is setf rom theW RI TE command with data strobe input,f ollowing (B L- 1) da ta arew ritten into RA M, when theB urst Length is BL .T he starta ddressi ss pecified by A0-7,9,a nd thea ddresss equenceo fb urst data is definedb yt he BurstT ype. AW RI TE commandm ay be appliedt oa ny active bank,s ot he rowp recharge time (tRP )c an be hiddenb ehindc ontinuousi nput data by interleaving them ultiple banks. From thel astd atat ot he PR Ec ommand, thew rite recovery time (tWR P) is required.W hen A8 is high at aW RI TE command,t he auto-precharge(WRI TE A) is performed. Any command(RE AD ,W RI TE,P RE ,A CT )t ot he same bank is inhibitedt illt he internal prechargei s complete.T he nextAC Tc ommand canb ei ssueda fter tDAL from thel asti nput data cycle. WRITE MultiB ankI nterleavingW RITE (B L=8) Command A0-7 ,9-11 BA 0,1 DQ AC T Xa WR IT E WR IT E 0 0 AC T Xb tRCD D tRCD D PR E Xa 0 PR E DQS /CLK CL K Da0D a1 Da2D a3 Da4D a5 Da6D a7 Db0D b1 Db2D b3 Db4D b5 Db6D b7 Xa Ya YbXb
28 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 WRITEw ithA uto-Precharge (B L=8) Command A0-7 ,9-11 BA 0,1 DQ AC T Xa WR IT E AC T Xb tRC D Da0 DQS /CLK CL K Da1D a2 Da3D a4 Da5D a6 Da7 tDAL Xa Y Xb 01 23 45 67 89 10 11 12
Integrated Silicon Solution, Inc. — www.issi.com 29 Rev. A 01/14/09 IS43R32800 ReadI nterrupted by Read Burstr eado peration canb ei nterrupted by newr eado fa ny bank.R andomc olumna ccessi sa llowed. RE AD to RE AD interval is minimum1 CL K. Read Int err upted by Read (B L=8, CL=2 ) Command A0-7 ,9-11 BA 0,1 DQ Yi RE AD RE AD RE AD RE AD Yj Yk Yl 00 00 00 1000 01 DQS Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Qak0 Qak1 Qak2 Qak3 Qak4 Qak5 Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7 /CLK CL K R eadI nterrupted by precharge Burstr eado peration canb ei nterrupted by prechargeo ft he same bank.R EA Dt oP RE interval is minimum1 CL K. AP RE co mmand to output disablel aten cyis equivalent to the/ CA SL atency. As ar esult, RE AD to PR Ei ntervald eterminesv alid data length to be output.T he figureb elow showse xampleso fB L=8. Read Int err upted by Prechar ge (B L=8) CL=2 .0 /CLK CL K Command DQS Command DQ Command DQ Q0 Q1 Q2 Q3 Q0 Q1 DQ Q0 Q1 Q2 Q3 Q4 Q5 PR ERE AD RE AD PR E RE AD PR E DQS DQS BURST INTERRUPTION
30 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 Read Int err upted by Prechar ge (B L=8) CL=2 .5 Command DQS Command DQ Command DQ Q0 Q1 Q2 Q3 Q0 Q1 /CLK CL K DQ Q0 Q1 Q2 Q3 Q4 Q5 PR ERE AD RE AD PR E RE AD PR E DQS DQS Read Int err upted by Prechar ge (B L=8) CL=3 .0 /CLK CL K Command DQS Command DQ Command DQ DQ PR ERE AD RE AD PR E Q0 Q1 Q2 Q3 Q4 Q5 RE AD PR E DQS Q0 Q1 Q2 Q3 DQS Q0 Q1
Integrated Silicon Solution, Inc. — www.issi.com 31 Rev. A 01/14/09 IS43R32800 Burstr eado peration canb ei nterrupted by ab urst stop command(TE RM). RE AD to TE RM interval is minimum1 CL K. AT ER Mc ommand to output disablel aten cyis equivalent to the/ CA SL aten cy. As ar esult, RE AD to TE RM interval determines validd atal engtht ob eo utput. Thef igureb elow showse xampleso fB L=8. ReadI nterrupted by BurstS top Read Int err upted by TERM( BL =8) /CLK CL K CL=2 .5 Command DQS Command DQ Command DQ Q0 Q1 Q2 Q3 Q0 Q1 DQ Q0 Q1 Q2 Q3 Q4 Q5 TE RMRE AD RE AD TE RM RE AD TE RM DQS DQS CL=2 .0 Command DQS Command DQ Command DQ Q0 Q1 Q2 Q3 Q0 Q1 DQ Q0 Q1 Q2 Q3 Q4 Q5 TE RMRE AD RE AD TE RM RE AD TE RM DQS DQS
32 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 R eadI nterrupted by Wr itew ithT ERM Read Int err upted by TER M( BL =8) /CLK CL K CL=2 .5 Command DQ Q0 Q1 Q2 Q3 RE AD TER M DQS WR IT E D0 D1 D2 D3 D4 D5 CL=2 .0 Command DQ Q0 Q1 Q2 Q3 RE AD TER M DQS WR IT E D0 D1 D2 D3 D4 D5 D6 D7 Read Int err upted by TERM( BL =8) /CLK CL K CL=3 .0 Command DQS Command DQ Command DQ DQ TE RMRE AD RE AD TE RM Q0 Q1 Q2 Q3 Q4 Q5 RE AD TE RM DQS Q0 Q1 Q2 Q3 DQS Q0 Q1 CL=3 .0 Command DQ Q0 Q1 Q2 Q3 RE AD TER M DQS WR IT E D0 D1 D2 D3 D4 D5
Integrated Silicon Solution, Inc. — www.issi.com 33 Rev. A 01/14/09 IS43R32800 Burstw rite operationc an be interrupted by writeo fa ny bank.R andomc olumna ccess is allowed. WRIT Et oW RI TE interval is minimum1 CL K. Write interruptedby Write Write interr uptedb yR ead Burstw rite operationc an be interrupted by read of thes ameo rt he otherb ank. Ra ndom column accessi sa llowed.I nternalW RI TE to RE AD command interval(tWT R) is minimum1 CL K. The inputdata on DQ at thei nterruptingR EA Dc ycle is "don't care". tWTR is referenced from thef irst positive edgeaftert he last data input. Wr iteI nterrupted by Read (BL=8, CL=2 .5) Command A0-7 ,9-11 BA 0,1 DQ WR IT E Yi RE AD Yj Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 QS Qaj4 Qaj5 Qaj6 Qaj7 DM tWTR /CLK CL K Wr iteI nterrupted by Wr ite( BL=8) Command A0-7 ,9-11 BA 0,1 WR IT E Yi WR IT E Yk WR IT E Yj WR IT E Yl DQ Dai1 Daj1 Daj3 Dak1 Dak3 Dak5 Dal1 DQS Dal2 Dal3 Dal5 Dal6 Dal7Dal4Dal0Dak4Dak2Dak0Dai0 Daj0 Daj2 /CLK CL K
34 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 Burstw rite operationc an be interrupted by prechargeo ft he same or allb ank. Ra ndom column accessi sa llowed.t WR is referenced from thef irst positive CL Ke dgeaftert he last data input. W rite interrupted by Pr echarge Wr iteI nterr upted by Precharge (B L=8, CL=2 .5) Command A0-7 ,9-11 BA 0,1 DQ WR IT E Yi PR E Dai0 Dai1 QS DM tWR /CLK CL K
Integrated Silicon Solution, Inc. — www.issi.com 35 Rev. A 01/14/09 IS43R32800 I nitial izea nd Mode Registersets Command /CLK CL K EM RSPR ENOP MR S PR E AR AR MR S AC T Code Code Xa Code Xa 10 Xa A0-7 ,9-11 A8 Code1 BA 0,1 DQS DQ 00 00 Code tMRD tMRD tRP tRFC tRFC tMRD Mode Register Set, ResetD LL Ex tendedMode Register Set AUTOR EFRESH Single cycleo fa uto-refreshi si nitiatedwith aR EF A( /CS=/R AS =/CA S=L, /WE= CK E= H) command. Ther efresh addressi sg enerat edinternally. 4096 RE FA cycles within 64ms refresh 256Mbits memory cells. Thea uto-refreshi sp erformed on 4b anks concurrently.B eforep erforming an auto refresh, allb anks must be in thei dles ta te.A uto-refresht oa uto-refreshi ntervali sm inimum tRFC .A ny command must notb es upplied to thed eviceb eforet RF Cf romt he RE FA command. Auto-Ref resh /RAS CK E /CS /CAS /WE A0-1 1 BA 0,1 NOPo rD ESEL EC T tRFC Auto Refresh on Al lB anks Auto Refresho nA ll Ba nks /CLK CL K CK E In itialize andM RS
36 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 SELF REFRESH Self -refresh mode is enteredb yi ssuing aR EF Sc ommand (/CS=/RA S=/CAS =L ,/WE =H,C KE =L ). Once thes elf-refreshi si nitiated,i ti sm aintaineda sl onga sC KE is kept low. During thes elf- refreshm ode, CK Ei sa synchron ousa nd theo nlye nablei nput,a ll otheri nputsi ncluding CL Ka re disabled andi gn ored,s ot hatp ower consumption due to synchron ousi nputsi ss aved.T oe xitt he self-refresh, supplyings tableC LK inputs, assertingD ESEL or NOPc ommand andt hena sserting CK Ef or longer than tX SNR/ tX SRD. Self-R efresh /RAS CK E /CS /CAS /WE A0-1 1 BA 0,1 tX SN R Self RefreshE xit /CLK CL K XY XY tX SR D
Integrated Silicon Solution, Inc. — www.issi.com 37 Rev. A 01/14/09 IS43R32800 The purpose of CL Ks uspend is powerd own. CK Ei ss ynchronous input exceptduringt he self- refreshm ode. Ac ommand at cyclei si gn ored.F romC KE =H to normal function,D LL recovery time is NOT required in thec on dition of thes tableC LK operation duringt he powerd ownm ode. Power DOWN /CLK CL K PowerD ownb yC KE Command PR E CK E Command AC T CK E StandbyP ower Down NOP NOP Va lid NOP NOP Va lid ActiveP ower Down DM is defineda st he data mask forw rites. During writes,D Mm asks inputdata word by word.D M to writem askl atency is 0. DMC ONTROL DM Function(B L=8, CL=2 ) Command DQS DQ DM WR IT E RE AD D0 D1 D3 D4 D5 D6 D7 masked by DM=H Don'tC are Q2 Q3 Q4 Q5 /CLK CL K Q0 Q1 Q6 tX PNR /tXPR D
38 Integrated Silicon Solution, Inc. — www.issi.com Rev. A 01/14/09 IS43R32800 Frequency Speed (ns) Order Part No. Organization Package
200 MHz 5 IS43R32800-5BL 8Mx32 144-ball fBGA, Lead-free
166 MHz 6 IS43R32800-6BL 8Mx32 144-ball fBGA, Lead-free
133 MHz 7.5 IS43R32800-75BL 8Mx32 144-ball fBGA, Lead-free ORDERING INFORMATION - Vd d = 2.5V Commercial Range: 0oC to +70oC
Integrated Silicon Solution, Inc. — www.issi.com 39 Rev. A 01/14/09 IS43R32800 Mini Ball Grid Array Package Code: B (144-Ball) mBGA - 12mm x 12mm MILLIMETERS INCHES N0. Leads 144 Notes: 1. Controlling dimensions are in millimeters. 2. 0.8 mm Ball Pitch 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M A B C D E F G H J K L M D e e SEATING PLANE A E 12 11 10 9 8 7 6 5 4 3 2 1