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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 PRELIMINARY INFORMATION Rev. 00B 03/11/03 IS24C128 ISSI Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. 131,072-bit 2-WIRE SERIAL CMOS EEPROM
FEATURES
- Organization: – 16K-bit x 8-bit 64-Byte Page Write Buffer Two-Wire Serial Interface – Bi-directional data transfer protocol Low Power CMOS Technology – Active Current less than 2 mA (5V) – Standby Current less than 5 µA (5V) – Standby Current less than 2 µA (2.5V) Low Voltage Operation – IS24C128-2: Vcc = 1.8V to 5.5V – IS24C128-3: Vcc = 2.5V to 5.5V 400 KHz (I 2C Protocol) Compatibility PRELIMINARY INFORMATION MARCH 2003 Hardware Data Protection – Write Protect pin Sequential Read Feature Filtered Inputs for Noise Suppression Self time Write cycle with auto clear – 5 ms @ 2.5V High Reliability – Endurance: 100,000 Cycles – Data Retention: 40 Years Commercial and Industrial temperature ranges 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP The IS24C128 is an electrically erasable PROM device that uses the standard 2-wire interface for communications. The IS24C128 contains a memory array of 128K-bits (16,384 x 8), and is further subdivided into 256 pages of 64 bytes each for page- write mode. This EEPROM is offered in wide operating voltages of 1.8V to 5.5V (IS24C128-2) and 2.5V to 5.5V (IS24C128-3) to be compatible with most application voltages. ISSI designed the IS24C128 to be a low-cost and low-power 2-wire EEPROM solution. The devices are packaged in 8-pin PDIP, 8-pin SOIC, and 14-pin TSSOP. The IS24C128 maintains compatibility with the popular 2-wire bus protocol, so it is easy to design into applications implementing this bus type. The simple bus consists of the Serial Clock wire (SCL) and the Serial Data wire (SDA). Using the bus, a Master device such as a microcontroller is usually connected to one or more Slave devices such as the IS24C128. The bit stream over the SDA line includes a series of bytes, which identifies a particular Slave device, an instruction, an address within that Slave device, and a series of data, if appropriate. The IS24C128 has a Write Protect pin (WP) to allow blocking of any write instruction transmitted over the bus.
DESCRIPTION
2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 03/11/03 IS24C128 ISSI FUNCTIONAL BLOCK DIAGRAM CONTROL LOGIC X DECODER SLAVE ADDRESS REGISTER & COMPARATOR WORD ADDRESS COUNTER HIGH VOLTAGE GENERATOR, TIMING & CONTROL EEPROM ARRAY Y DECODER DATA REGISTER Clock DI/O ACKGND WP SCL SDA Vcc nMOS NC
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3 PRELIMINARY INFORMATION Rev. 00A 03/11/03 IS24C128 ISSI PIN DESCRIPTIONS A0-A1 Address Inputs SDA Serial Address/Data I/O SCL Serial Clock Input WP Write Protect Input Vcc Power Supply NC No Connect GND Ground SCL This input clock pin is used to synchronize the data transfer to and from the device. SDA The SDA is a Bi-directional pin used to transfer addresses and data into and out of the device. The SDA pin is an open PIN CONFIGURATION 8-Pin DIP and SOIC drain output and can be wire Or'ed with other open drain or open collector outputs. The SDA bus requires a pullup resistor to Vcc. A0, A1 The A0, and A1 are the device address inputs that are hardwired or left not connected for hardware compatibility with the 24C32/64. When pins are hardwired, as many as four 128K devices may be addressed on a single bus system. When the pins are not hardwired, the default A0 and A1 are zero. WP WP is the Write Protect pin. If the WP pin is tied to Vcc the entire array becomes Write Protected (Read only). When WP is tied to GND or left floating, normal read/write operations are allowed to the device. 14-pin TSSOP NC NC NC NC VCC WP NC NC NC SCL SDA GND NC GND VCC WP SCL SDA
4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 03/11/03 IS24C128 ISSI DEVICE OPERATION The IS24C128 features a serial communication and supports a bi-directional 2-wire bus transmission protocol. 2-WIRE BUS The two-wire bus is defined as a Serial Data line (SDA), and a Serial Clock line (SCL). The protocol defines any device that sends data onto the SDA bus as a transmitter, and the receiving devices as a receiver. The bus is controlled by Master device which generates the SCL, controls the bus access and generates the Stop and Start conditions. The IS24C128 is the Slave device on the bus. The Bus Protocol: – Data transfer may be initiated only when the bus is not busy – During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. The state of the data line represents valid data after a Start condition. The data line must be stable for the duration of the High period of the clock signal. The data on the SDA line may be changed during the Low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. Start Condition The Start condition precedes all commands to the device and is defined as a High to Low transition of SDA when SCL is High. The IS24C128 monitors the SDA and SCL lines and will not respond until the Start condition is met. Stop Condition The Stop condition is defined as a Low to High transition of SDA when SCL is High. All operations must end with a Stop condition. Acknowledge (ACK) After a successful data transfer, each receiving device is required to generate an ACK. The Acknowledging device pulls down the SDA line. Reset The IS24C128 contains a reset function in case the 2- wire bus transmission is accidentally interrupted (eg. a power loss), or needs to be terminated mid-stream. The reset is caused when the Master device creates a Start condition. To do this, it may be necessary for the Master device to monitor the SDA line while cycling the SCL up to nine times. (For each clock signal transition to High, the Master checks for a High level on SDA.) Standby Mode Power consumption in reduced in standby mode. The IS24C128 will enter standby mode: a) At Power-up, and remain in it until SCL or SDA toggles; b) Following the Stop signal if no write operation is initiated; or c) Following any internal write operation DEVICE ADDRESSING The Master begins a transmission by sending a Start condition. The Master then sends the address of the particular Slave devices it is requesting. The Slave (Fig. 5) address is 8 bits. The four most significant bits of the address are fixed as 1010 for the IS24C128. This device has two address bits (A1 and A0), which allows up to four IS24C128 devices to share the 2-wire bus. Upon receiving the Slave address, the device compares the two address bits with the hardwired A1 and A0 input pins to determine if it is the appropriate Slave. If the A1 and A0 pins are not biased to High nor Low, then internal circuitry defaults the value to Low. The last bit of the Slave address specifies whether a Read or Write operation is to be performed. When this bit is set to 1, a Read operation is selected, and when set to 0, a Write operation is selected. After the Master transmits the Start condition and Slave address byte (Fig. 5), the appropriate 2-wire Slave (eg. IS24C128) will respond with ACK on the SDA line. The Slave will pull down the SDA on the ninth clock cycle, signaling that it received the eight bits of data. The selected IS24C128 then prepares for a Read or Write operation by monitoring the bus. WRITE OPERATION Byte Write In the Byte Write mode, the Master device sends the Start condition and the Slave address information (with the R/ W set to Zero) to the Slave device. After the Slave generates an ACK, the Master sends two byte addresses that are to be written into the address pointer of the IS24C128. After receiving another ACK from the Slave, the Master device transmits the data byte to be written into the address memory location. The IS24C128 acknowledges once more and the Master generates the Stop condition, at which time the device begins its internal programming cycle. While this internal cycle is in progress, the device will not respond to any request from the Master device.
followed by a Stop condition. Figure 8. Current Address Read Diagram.)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9 PRELIMINARY INFORMATION Rev. 00A 03/11/03 IS24C128 ISSI ABSOLUTE MAXIMUM RATINGS (1) Symbol Parameter Value Unit VS Supply Voltage +0.5 to +6.25 V VP Voltage on Any Pin –0.5 to Vcc +0.5 V TBIAS Temperature Under Bias –40 to +85 °C TSTG Storage Temperature –65 to +150 °C IOUT Output Current 5 mA Notes: 1. Stresses violating the conditions listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only. Functional operation of the device outside these conditions or those indicated in the operational sections of this specification is not implied. Exposure to these conditions for extended periods may affect reliability. CAPACITANCE (1,2) Symbol Parameter Conditions Max. Unit C IN Input Capacitance V IN = 0V 6 pF C OUT Output Capacitance V OUT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V. OPERATING RANGE (IS24C128-3) Range Ambient Temperature V CC Commercial 0°C to +70°C 2.5V to 5.5V Industrial –40°C to +85°C 2.5V to 5.5V OPERATING RANGE (IS24C128-2) Range Ambient Temperature V CC Commercial 0°C to +70°C 1.8V to 5.5V Industrial –40°C to +85°C 1.8V to 5.5V
10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 03/11/03 IS24C128 ISSI DC ELECTRICAL CHARACTERISTICS Commercial (TA = 0 O C to +70 O C) Industrial (TA = -40 O C to +85 O Symbol Parameter Test Conditions Min. Max. Unit VOL 1 Output Low Voltage V CC = 1.8V, IOL = 0.15 mA — 0.2 V VOL 2 Output Low Voltage V CC = 2.5V, IOL = 1.0 mA — 0.4 V V IH Input High Voltage V CC X 0.7 VCC + 0.5 V VIL Input Low Voltage –1.0 V CC X 0.3 V ILI Input Leakage Current V IN = VCC max. — 3 µA ILO Output Leakage Current — 3 µA Notes: VIL min and VIH max are reference only and are not tested. POWER SUPPLY CHARACTERISTICS Commercial (TA = 0 O C to +70 O C) Industrial (TA = -40 O C to +85 O Symbol Parameter Test Conditions Min. Max. Unit ICC 1 Vcc Operating Current Read at 100 KHz (Vcc = 5V) — 2.0 mA ICC 2 Vcc Operating Current Write at 100 KHz (Vcc = 5V) — 3.0 mA ISB 1 Standby Current Vcc = 1.8V, Vcc = 2.5V — 2 µA ISB 2 Standby Current Vcc = 5.0V — 5 µA AC ELECTRICAL CHARACTERISTICS Commercial (TA = 0 O C to +70 O C) Industrial (TA = -40 O C to +85 O fSCL SCL Clock Frequency 0 100 0 400 0 1000 KHz T Noise Suppression Time (1) — 100 — 50 — 50 ns tLow Clock Low Period 4.7 — 1.3 — 0.6 — µs tHigh Clock High Period 4 — 0.6 — 0.4 — µs tBUF Bus Free Time Before New Transmission(1) 4.7 — 1.2 — 0.5 — µs tSU:STA Start Condition Setup Time 4.7 — 0.6 — 0.25 — µs tSU:STO Stop Condition Setup Time 4.7 — 0.6 — 0.25 — µs tHD:STA Start Condition Hold Time 4 — 0.6 — 0.25 — µs tHD:STO Stop Condition Hold Time 4 — 0.6 — 0.6 — µs tSU:DAT Data In Setup Time 200 — 100 — 100 — ns tHD:DAT Data In Hold Time 0 — 0 — 0 — ns tSU :WP WP pin Setup Time 4 — 0.6 — 0.6 — µs tHD :WP WP pin Hold Time 4.7 — 1.3 — 1.3 — µs tDH Data Out Hold Time (SCL Low to SDA Data Out Change) 200 — 200 — 200 — ns tAA Clock to Output (SCL Low to SDA Data Out Valid) 200 3500 200 900 200 550 ns tR SCL and SDA Rise Time(1) — 1000 — 300 — 300 ns tF SCL and SDA Fall Time(1) — 300 — 300 — 300 ns tWR Write Cycle Time — 10 — 5 — 5 ms Note: 1. This parameter is characterized but not 100% tested. 2. Preliminary only.
12 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 PRELIMINARY INFORMATION Rev. 00B 03/11/03 IS24C128 ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C Voltage Frequency Range Part Number Package 400 KHz 2.5V IS24C128-3P 300-mil Plastic DIP (8-pin) to 5.5V IS24C128-3G Small Outline (JEDEC STD) (8-pin) IS24C128-3Z TSSOP (14-pin) Industrial Range: –40°C to +85°C Voltage Frequency Range Part Number Package 400 KHz 2.5V IS24C128-3PI 300-mil Plastic DIP (8-pin) to 5.5V IS24C128-3GI Small Outline (JEDEC STD) (8-pin) IS24C128-3ZI TSSOP (14-pin) ISSI Integrated Silicon Solution, Inc. Tel: 1-800-379-4774
2231 Lawson Lane Fax: (408) 588-0806
Santa Clara, CA 95054 E-mail: sales@issi.com www.issi.com