Memory

128Kx36

Integrated Silicon Solu...

128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

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Document: 29 Pages / 528Kb

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IS61NLP12832B ISSI | Alldatasheet

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Technical content

Integrated Silicon Solution, Inc. — www.issi.com 1 Rev. D 09/10/07 Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A

FEATURES

100 percent bus utilization
No wait cycles between Read and Write
Internal self-timed write cycle
Individual Byte Write Control
Single R/W (Read/Write) control pin
Clock controlled, registered address, data and control
Interleaved or linear burst sequence control us- ing MODE input
Three chip enables for simple depth expansion and address pipelining
Power Down mode
Common data inputs and data outputs
CKE pin to enable clock and suspend operation
JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages
Power supply: NVP: V NLP: Vd d 3.3V (± 5%), Vd d q 3.3V/2.5V (± 5%)
Industrial temperature available
Lead-free available

DESCRIPTION

The 4 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 128K words by 32 bits, 128K words by 36 bits, and 256K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. 128K x 32, 128K x 36, and 256K x 18 4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2007 FAST ACCESS TIME Symbol Parameter -250 -200 Units t k q Clock Access Time 2.6 3.1 ns t k c Cycle Time 4 5 ns Frequency 250 200 MHz

2 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A BLOCK DIAGRAM ADV WE }BWŸX (X=a,b,c,d or a,b) CE CE2 CE2 CONTROL LOGIC 128Kx32; 128Kx36; 256Kx18 MEMORY ARRAY WRITE ADDRESS REGISTER WRITE ADDRESS REGISTER CONTROL LOGIC OUTPUT REGISTER BUFFER ADDRESS REGISTER x 32/x 36: A [0:16] or x 18: A [0:17] CLK CKE A2-A16 or A2-A17 A0-A1 A'0-A'1 BURST ADDRESS COUNTER MODE DATA-IN REGISTER DATA-IN REGISTER CONTROL REGISTER OE ZZ 32, 36 or 18 K K DQx/DQPx K K

Integrated Silicon Solution, Inc. — www.issi.com 3 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A Bottom View 165-Ball, 13 mm x 15mm BGA 1 mm Ball Pitch, 11 x 15 Ball Array Bottom View 119-Ball, 14 mm x 22 mm BGA 1 mm Ball Pitch, 7 x 17 Ball Array

4 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIgURATION — 128K x 36, 165-Ball PBgA (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 CKE ADV NC A NC B NC A CE2 BWd BWa CLK WE OE NC A NC C DQPc NC V d d q VSS VSS VSS VSS VSS V d d q NC DQPb D DQc DQc V d d q V d d VSS VSS VSS V d d V d d q DQb DQb E DQc DQc V d d q V d d VSS VSS VSS V d d V d d q DQb DQb F DQc DQc V d d q V d d VSS VSS VSS V d d V d d q DQb DQb G DQc DQc V d d q V d d VSS VSS VSS V d d V d d q DQb DQb H NC NC NC V d d VSS VSS VSS V d d NC NC ZZ J DQd DQd V d d q V d d VSS VSS VSS V d d V d d q DQa DQa K DQd DQd V d d q V d d VSS VSS VSS V d d V d d q DQa DQa L DQd DQd V d d q V d d VSS VSS VSS V d d V d d q DQa DQa M DQd DQd V d d q V d d VSS VSS VSS V d d V d d q DQa DQa N DQPd NC V d d q V SS NC NC NC VSS V d d q NC DQPa P NC NC A A NC A1* NC A A A NC R MODE NC A A NC A0* NC A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection VDD 3.3V/2.5V Power Supply NC No Connect DQx Data Inputs/Outputs DQPx Parity Data I/O V DDQ Isolated output Power Supply 3.3V/2.5V VS S G round

Integrated Silicon Solution, Inc. — www.issi.com 5 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION 128K x 36 (TOP VIEW) 1 2 3 4 5 6 7 A A BWb B NC C NC D DQc DQPc Vss E DQc DQc Vss F VDDQ DQc G DQc DQc H DQc DQc J VDDQ VDD K DQd DQd L DQd DQd M VDDQ DQd N DQd DQd VssP NC DQPd R A CE2 MODE A0* A A A VSS VSS VSS VSS BWd VSS VSS VSS NC NC VDD VDD VDD VDD NC Vss Vss Vss Vss Vss NC CE2 NCA NC T U VDDQ NC VDDQ DQd A NC NC NC A A BWc NC A1* CKE NC CLK NC WE NC OE CE NC ADV NC A NC BWa A A A DQPa DQa DQa DQa DQa DQb DQb DQb DQb DQPb A A VDDQ ZZ DQa DQa VDDQ DQa DQa VDDQ DQb DQb VDDQ DQb DQb NC VDDQ VSS Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE Synchronous Chip Select CE2 Synchronous Chip Select CE2 Synchronous Chip Select BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection Vd d Power Supply VS S Ground NC No Connect DQa-DQd Data Inputs/Outputs DQPa-Pd Parity Data I/O V d d q Output Power Supply

6 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 165-PIN PBgA PACKAgE CONFIGURATION 256K x 18 (TOP VIEW) PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode 1 2 3 4 5 6 7 8 9 10 11 A A BWb CKE B N C A WE OE C N C NC Vss Vss D N C DQb Vss Vss NC E N C DQb Vss Vss Vss F NC DQb NC G N C DQb NC NC H N C NC VDDQ J DQb NC DQa K DQb NC L DQb NC Vss M DQb NC Vss N DQPb NC Vss Vss NC P N C NC A1* N C R MODE A NC CE2 Vss Vss Vss Vss Vss Vss Vss Vss NC NC A A A A A A A A A A ANC NC A ACE VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC NC VDD VDD VDD VDD VDD VDD VDD VDD VDD NC BWa Vss Vss Vss Vss Vss Vss Vss Vss NC NC NC CE2 CLK Vss NC A0* NC Vss Vss Vss Vss Vss Vss ADV VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ NC NC NC DQa DQa DQa NC NC NC NC NC NC NC ZZ DQa DQa DQa DQa DQPa Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. MODE Burst Sequence Selection VDD 3.3V/2.5V Power Supply NC No Connect DQx Data Inputs/Outputs DQPx Parity Data I/O V DDQ Isolated output Power Supply 3.3V/2.5V VS S G round

Integrated Silicon Solution, Inc. — www.issi.com 7 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 119-PIN PBgA PACKAgE CONFIGURATION 256K x 18 (TOP VIEW) PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV Synchronous Burst Address Advance/ Load WE Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE Synchronous Chip Select CE2 Synchronous Chip Select CE2 Synchronous Chip Select BWx (x=a,b) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE Burst Sequence Selection Vd d Power Supply VS S Ground NC No Connect DQa-DQb Data Inputs/Outputs DQPa-Pb Parity Data I/O V d d q Output Power Supply 1 2 3 4 5 6 7 A A B NC C NC D DQb Vss E DQb Vss F VDDQ G DQb H DQb J VDDQ VDD K DQb L DQb M VDDQ DQb N DQb NC VssP NC DQPb R A CE2 MODE A A0* A A VSS VSS VSS VSS NC VSS VSS NC NC VDD VDD VDD VDD NC Vss Vss Vss Vss Vss NC CE2 NCA NC T U VDDQ NC VDDQ A NC NC NC A A BWb NC A1* CKE NC CLK NC WE NC OE CE NC ADV NC A NC BWa A A A DQPa DQa DQa DQa DQa A A VDDQ ZZ DQa DQa VDDQ DQa DQa VDDQ VDDQ NC VDDQ NC NC NC NC NC NC NC NC A VSS VSS NC NC NC NC NC NC NC NC NC Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.

8 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP 128K x 32 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DQPb DQb DQb V DDQ Vss DQb DQb DQb DQb Vss V DDQ DQb DQb Vss NC V DD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss V DDQ DQa DQa DQPa DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd A A CE CE2 BWd BWc BWb BWa CE2 V DD Vss CLK WE CKE OE ADV NC NC A A MODE A A A A NC NC Vss V DD NC NC A A A A A A A 128K x 36 PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection V d d +3.3V/2.5V Power Supply VS S Ground for output Buffer Vd d q Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC DQb DQb V DDQ Vss DQb DQb DQb DQb Vss V DDQ DQb DQb Vss NC V DD ZZ DQa DQa VDDQ Vss DQa DQa DQa DQa Vss V DDQ DQa DQa NC NC DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc NC VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd NC A A CE CE2 BWd BWc BWb BWa CE2 V DD Vss CLK WE CKE OE ADV NC NC A A MODE A A A A NC NC Vss VDD NC NC A A A A A A A

Integrated Silicon Solution, Inc. — www.issi.com 9 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A PIN CONFIGURATION 100-Pin TQFP 256K x 18 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A NC NC VDDQ Vss NC DQPa DQa DQa Vss V DDQ DQa DQa Vss NC VDD ZZ DQa DQa V DDQ Vss DQa DQa NC NC Vss V DDQ NC NC NC NC NC NC VDDQ Vss NC NC DQb DQb Vss VDDQ DQb DQb NC VDD NC Vss DQb DQb VDDQ Vss DQb DQb DQPb NC Vss VDDQ NC NC NC A A CE CE2 NC NC BW b BWa CE2 VDD Vss CLK WE CKE OE ADV NC NC A A MODE A A A A NC NC Vss V DD NC NC A A A A A A A PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. A Synchronous Address Inputs CLK Synchronous Clock ADV Synchronous Burst Address Advance BWa-BWd Synchronous Byte Write Enable WE Write Enable CKE Clock Enable Vss Ground for Core NC Not Connected CE, CE2, CE2 Synchronous Chip Enable OE Output Enable DQa-DQd Synchronous Data Input/Output DQPa-DQPd Parity Data I/O MODE Burst Sequence Selection V d d +3.3V/2.5V Power Supply VS S Ground for output Buffer Vd d q Isolated Output Buffer Supply: +3.3V/2.5V ZZ Snooze Enable

10 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SYNCHRONOUS TRUTH TABLE(1) Address Operation Used CE CE2 CE2 ADV WE BWx OE CKE CLK Not Selected N/A H X X L X X X L ↑ Not Selected N/A X L X L X X X L ↑ Not Selected N/A X X H L X X X L ↑ Not Selected Continue N/A X X X H X X X L ↑ Begin Burst Read External Address L H L L H X L L ↑ Continue Burst Read Next Address X X X H X X L L ↑ NOP/Dummy Read External Address L H L L H X H L ↑ Dummy Read Next Address X X X H X X H L ↑ Begin Burst Write External Address L H L L L L X L ↑ Continue Burst Write Next Address X X X H X L X L ↑ NOP/Write Abort N/A L H L L L H X L ↑ Write Abort Next Address X X X H X H X L ↑ Ignore Clock Current Address X X X X X X X H ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). BURST READ DESELECT BURST WRITE BEGIN READ BEGIN WRITE READ WRITE READ WRITE BURSTBURST BURSTDS DSDS READ DSDS READ WRITE WRITE BURST BURST WRITEREAD STATE DIAGRAM

Integrated Silicon Solution, Inc. — www.issi.com 11 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ASYNCHRONOUS TRUTH TABLE(1) Operation ZZ OE I/O STATUS Sleep Mode H X High-Z Read L L DQ L H High-Z Write L X Din, High-Z Deselected L X High-Z Notes: 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation WE BWa BWb READ H X X WRITE BYTE a L L H WRITE BYTE b L H L WRITE ALL BYTEs L L L WRITE ABORT/NOP L H H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

12 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A INTERLEAVED BURST ADDRESS TABLE (MODE = Vd d or NC) External Address 1st Burst Address 2nd Burst Address 3rd Burst Address A1 A0 A1 A0 A1 A0 A1 A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 WRITE TRUTH TABLE (x32/x36) Operation WE BWa BWb BWc BWd READ H X X X X WRITE BYTE a L L H H H WRITE BYTE b L H L H H WRITE BYTE c L H H L H WRITE BYTE d L H H H L WRITE ALL BYTEs L L L L L WRITE ABORT/NOP L H H H H Notes: 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK.

Integrated Silicon Solution, Inc. — www.issi.com 13 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A LINEAR BURST ADDRESS TABLE (MODE = VS S) ABSOLUTE MAXIMUM RATINgS(1) Symbol Parameter Value Unit TS T G Storage Temperature –65 to +150 °C Pd Power Dissipation 1.6 W Io uT Output Current (per I/O) 100 mA VIn, Vo uT Voltage Relative to VS S for I/O Pins –0.5 to Vd d q + 0.5 V VIn Voltage Relative to VS S for –0.5 to 4.6 V for Address and Control Inputs Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reli- ability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precau- tions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. This device contains circuitry that will ensure the output devices are in High-Z at power up. 0,0 1,0 0,1A1', A0' = 1,1 OPERATINg RANgE (IS61NLPx) Range Ambient Temperature VD D VD Dq Commercial 0°C to +70°C 3.3V ± 5% 3.3V / 2.5V ± 5% Industrial -40°C to +85°C 3.3V ± 5% 3.3V / 2.5V ± 5% OPERATINg RANgE (IS61NVPx) Range Ambient Temperature VD D VD Dq Commercial 0°C to +70°C 2.5V ± 5% 2.5V ± 5% Industrial -40°C to +85°C 2.5V ± 5% 2.5V ± 5%

14 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) -250 -200 MAX MAX Symbol Parameter Test Conditions Temp. range x18 x32/x36 x18 x32/x36 Unit Ic c AC Operating Device Selected, Com. 225 225 200 200 mA Supply Current OE = VIh, ZZ ≤ VIl, Ind. 250 250 210 210 All Inputs ≤ 0.2V or ≥ Vd d – 0.2V, Cycle Time ≥ tk c min. ISb Standby Current Device Deselected, Com. 90 90 90 90 mA TTL Input Vd d = Max., Ind. 100 100 100 100 All Inputs ≤ VIl or ≥ VIh, ZZ ≤ VIl, f = Max. ISbI Standby Current Device Deselected, Com. 70 70 70 70 mA cMoS Input V d d = Max., Ind. 75 75 75 75 VIn ≤ VS S + 0.2V or ≥Vd d – 0.2V typ.(2) 40 f = 0 I Sb2 Sleep Mode ZZ>V Ih Com. 30 30 30 30 mA Ind. 35 35 35 35 typ.(2) 20 Note: 1. MODE pin has an internal pullup and should be tied to Vd d or VS S. It exhibits ±100µA maximum leakage current when tied to ≤ VS S + 0.2V or ≥ Vd d – 0.2V. 2. Typical values are measured at Vd d = 3.3V, TA = 25oC and not 100% tested. DC ELECTRICAL CHARACTERISTICS (Over Operating Range) 3.3V 2.5V Symbol Parameter Test Conditions Min. Max. Min. Max. Unit Vo h Output HIGH Voltage Io h = –4.0 mA (3.3V) 2.4 — 2.0 — V Io h = –1.0 mA (2.5V) Vo l Output LOW Voltage Io l = 8.0 mA (3.3V) — 0.4 — 0.4 V Io l = 1.0 mA (2.5V) VIh(1) Input HIGH Voltage 2.0 Vd d + 0.3 1.7 Vd d + 0.3 V VIl(1) Input LOW Voltage –0.3 0.8 –0.3 0.7 V IlI Input Leakage Current V S S ≤ VIn ≤ Vd d(1) –5 5 –5 5 µA I l o Output Leakage Current VS S ≤ Vo uT ≤ Vd d q, OE = VIh –5 5 –5 5 µA Note: 1. Overshoot: VIh (AC) < Vd d + 2.0V (Pulse width less than tk c/2). Undershoot: VIl (AC) > -2V (Pulse width less than tk c/2).

Integrated Silicon Solution, Inc. — www.issi.com 15 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 3.3V I/O AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 3.0V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.5V and Reference Level Output Load See Figures 1 and 2 317 Ω 5 pF Including jig and scope 351 Ω OUTPUT +3.3V Figure 1 Figure 2 CAPACITANCE(1,2) Symbol Parameter Conditions Max. Unit cIn Input Capacitance VIn = 0V 6 pF co uT Input/Output Capacitance Vo uT = 0V 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25°c, f = 1 MHz, Vd d = 3.3V. 3.3V I/O OUTPUT LOAD EQUIVALENT 1.5V OUTPUT Zo= 50Ω 50Ω

16 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A 2.5V I/O AC TEST CONDITIONS Parameter Unit Input Pulse Level 0V to 2.5V Input Rise and Fall Times 1.5 ns Input and Output Timing 1.25V and Reference Level Output Load See Figures 3 and 4 ZO = 50Ω 1.25V 50Ω OUTPUT 1,667 Ω 5 pF Including jig and scope 1,538 Ω OUTPUT +2.5V Figure 3 Figure 4 2.5V I/O OUTPUT LOAD EQUIVALENT

Integrated Silicon Solution, Inc. — www.issi.com 17 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ/WRITE CYCLE SWITCHINg CHARACTERISTICS(1) (Over Operating Range) -250 -200 Symbol Parameter Min. Max. Min. Max. Unit fmax Clock Frequency — 250 — 200 MHz t k c Cycle Time 4.0 — 5 — ns t k h Clock High Time 1.7 — 2 — ns t k l Clock Low Time 1.7 — 2 — ns t k q Clock Access Time — 2.6 — 3.1 ns t k q x(2) Clock High to Output Invalid 0.8 — 1.5 — ns t k q lZ(2,3) Clock High to Output Low-Z 0.8 — 1 — ns t k q hZ(2,3) Clock High to Output High-Z — 2.6 — 3.0 ns t o e q Output Enable to Output Valid — 2.8 — 3.1 ns t o e lZ(2,3) Output Enable to Output Low-Z 0 — 0 — ns t o e hZ(2,3) Output Disable to Output High-Z — 2.6 — 3.0 ns t A S Address Setup Time 1.2 — 1.4 — ns t wS Read/Write Setup Time 1.2 — 1.4 — ns t c eS Chip Enable Setup Time 1.2 — 1.4 — ns t Se Clock Enable Setup Time 1.2 — 1.4 — ns t AdV S Address Advance Setup Time 1.2 — 1.4 — ns t dS Data Setup Time 1.2 — 1.4 — ns t Ah Address Hold Time 0.3 — 0.4 — ns t h e Clock Enable Hold Time 0.3 — 0.4 — ns t w h Write Hold Time 0.3 — 0.4 — ns t c e h Chip Enable Hold Time 0.3 — 0.4 — ns t AdVh Address Advance Hold Time 0.3 — 0.4 — ns t d h Data Hold Time 0.3 — 0.4 — ns t PdS ZZ High to Power Down — 2 — 2 cyc t PuS ZZ Low to Power Down — 2 — 2 cyc Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2.

18 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SLEEP MODE TIMINg SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit ISb2 Current during SLEEP MODE ZZ ≥ VIh 35 mA t PdS ZZ active to input ignored 2 cycle t PuS ZZ inactive to input sampled 2 cycle t Z Z I ZZ active to SLEEP current 2 cycle t rZ Z I ZZ inactive to exit SLEEP current 0 ns Don't Care Deselect or Read Only Deselect or Read Only tRZZI CLK ZZ Isupply All Inputs (except ZZ) Outputs (Q) ISB2 ZZ setup cycle ZZ recovery cycle Normal operation cycle tPDS tPUS tZZI High-Z

Integrated Silicon Solution, Inc. — www.issi.com 19 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A READ CYCLE TIMINg tKQX CLK ADV Address WRITE CKE CE OE Data Out A1 A2 tKH tKL tKC Q3-3 Q3-4Q3-2Q3-1Q2-4Q2-3Q2-2Q2-1 Don't Care Undefined NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L tOEHZ tSE tHE tAS tAH tWS tWH tCES tCEH tADVS tADVH tKQHZ tKQtOEQ tOEHZ Q1-1

20 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A WRITE CYCLE TIMINg tDS tDH CLK ADV Address WRITE CKE CE OE Data In Data Out A1 A2 tKH tKL tKC tSE tHE D3-3 D3-4D3-2D3-1D2-4D2-3D2-2D2-1D1-1 Don't Care Undefined NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L tOEHZ Q0-3 Q0-4

Integrated Silicon Solution, Inc. — www.issi.com 21 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A SINgLE READ/WRITE CYCLE TIMINg CLK CKE Address WRITE CE ADV OE Data Out Data In D5 tSE tHE tKH tKL tKC Don't Care Undefined NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L tOELZ tOEQ A1 A2 A3 A4 A5 A6 A7 A8 A9 Q1 Q3 Q4 Q6 Q7 tDS tDH

22 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CKE OPERATION TIMINg A1 A2 A3 A4 A5 A6 Q1 Q3 Q4 CLK CKE Address WRITE CE ADV OE Data Out Data In D2 tSE tHE tKH tKL tKC tKQLZ tKQHZ tKQ tDHtDS Don't Care Undefined NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L C E = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L

Integrated Silicon Solution, Inc. — www.issi.com 23 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A CE OPERATION TIMINg Don't Care Undefined CLK CKE Address WRITE CE ADV OE Data Out Data In tSE tHE tKH tKL tKC NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L D5D3 tDHtDS tOELZ tOEQ Q1 Q2 Q4 tKQHZ tKQLZ tKQ A1 A2 A3 A4 A5

24 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VD D = 3.3V/VD Dq = 2.5V/3.3V) Commercial Range: 0°C to +70°C Access Time Order Part Number Package 128Kx32

250 IS61NLP12832B-250TQ 100 TQFP

IS61NLP12832B-250B3 165 PBGA IS61NLP12832B-250B2 119 PBGA

200 IS61NLP12832B-200TQ 100 TQFP

IS61NLP12832B-200B3 165 PBGA IS61NLP12832B-200B2 119 PBGA 128Kx36

250 IS61NLP12836B-250TQ 100 TQFP

IS61NLP12836B-250B3 165 PBGA IS61NLP12836B-250B2 119 PBGA

200 IS61NLP12836B-200TQ 100 TQFP

IS61NLP12836B-200B3 165 PBGA IS61NLP12836B-200B2 119 PBGA 256Kx18

250 IS61NLP25618A-250TQ 100 TQFP

IS61NLP25618A-250B3 165 PBGA IS61NLP25618A-250B2 119 PBGA

200 IS61NLP25618A-200TQ 100 TQFP

IS61NLP25618A-200B3 165 PBGA IS61NLP25618A-200B2 119 PBGA

Integrated Silicon Solution, Inc. — www.issi.com 25 Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VD D = 3.3V/VD Dq = 2.5V/3.3V) Industrial Range: -40°C to +85°C Access Time Order Part Number Package 128Kx32

250 IS61NLP12832B-250TQI 100 TQFP

IS61NLP12832B-250B3I 165 PBGA IS61NLP12832B-250B2I 119 PBGA

200 IS61NLP12832B-200TQI 100 TQFP

IS61NLP12832B-200TQLI 100 TQFP, Lead-free IS61NLP12832B-200B3I 165 PBGA IS61NLP12832B-200B2I 119 PBGA 128Kx36

250 IS61NLP12836B-250TQI 100 TQFP

IS61NLP12836B-250B3I 165 PBGA IS61NLP12836B-250B2I 119 PBGA

200 IS61NLP12836B-200TQI 100 TQFP

IS61NLP12836B-200TQLI 100 TQFP, Lead-free IS61NLP12836B-200B3I 165 PBGA IS61NLP12836B-200B2I 119 PBGA IS61NLP12836B-200B2LI 119 PBGA, Lead-free 256Kx18

250 IS61NLP25618A-250TQI 100 TQFP

IS61NLP25618A-250B3I 165 PBGA IS61NLP25618A-250B2I 119 PBGA

200 IS61NLP25618A-200TQI 100 TQFP

IS61NLP25618A-200TQLI 100 TQFP, Lead-free IS61NLP25618A-200B3I 165 PBGA IS61NLP25618A-200B3LI 165 PBGA, Lead-free IS61NLP25618A-200B2I 119 PBGA

26 Integrated Silicon Solution, Inc. — www.issi.com Rev. D 09/10/07 IS61NLP12832B IS61NLP12836B/IS61NVP12836B IS61NLP25618A/IS61NVP25618A ORDERINg INFORMATION (VD D = 2.5V/VD Dq = 2.5V) Commercial Range: 0°C to +70°C Access Time Order Part Number Package 128Kx36

250 IS61NVP12836B-250TQ 100 TQFP

IS61NVP12836B-250B3 165 PBGA IS61NVP12836B-250B2 119 PBGA

200 IS61NVP12836B-200TQ 100 TQFP

IS61NVP12836B-200B3 165 PBGA IS61NVP12836B-200B2 119 PBGA 256Kx18

250 IS61NVP25618A-250TQ 100 TQFP

IS61NVP25618A-250B3 165 PBGA IS61NVP25618A-250B2 119 PBGA

200 IS61NVP25618A-200TQ 100 TQFP

IS61NVP25618A-200B3 165 PBGA IS61NVP25618A-200B2 119 PBGA Industrial Range: -40°C to +85°C Access Time Order Part Number Package 128Kx36

250 IS61NVP12836B-250TQI 100 TQFP

IS61NVP12836B-250B3I 165 PBGA IS61NVP12836B-250B2I 119 PBGA

200 IS61NVP12836B-200TQI 100 TQFP

IS61NVP12836B-200B3I 165 PBGA IS61NVP12836B-200B2I 119 PBGA 256Kx18

250 IS61NVP25618A-250TQI 100 TQFP

IS61NVP25618A-250B3I 165 PBGA IS61NVP25618A-250B2I 119 PBGA

200 IS61NVP25618A-200TQI 100 TQFP

IS61NVP25618A-200B3I 165 PBGA IS61NVP25618A-200B2I 119 PBGA

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 02/12/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci fication and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services desc ribed herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. PACKAGING INFORMATION Plastic Ball Grid Array Package Code: B (119-pin) Notes: 1. Controlling dimension: millimeters, unless otherwise specified. 2. BSC = Basic lead spacing between centers. 3. Dimensions D1 and E do not include mold flash protrusion and should be measured from the bottom of the package. 4. Formed leads shall be planar with respect to one another within 0.004 inches at the seating plane. MILLIMETERS INCHES N0. Leads 119 A — 2.41 — 0.095 A1 0.50 0.70 0.020 0.028 A2 0.80 1.00 0.032 0.039 A3 1.30 1.70 0.051 0.067 A4 0.56 BSC 0.022 BSC b 0.60 0.90 0.024 0.035 D 21.80 22.20 0.858 0.874 D1 20.32 BSC 0.800 BSC D2 19.40 19.60 0.764 0.772 E 13.80 14.20 0.543 0.559 E1 7.62 BSC 0.300 BSC E2 11.90 12.10 0.469 0.476 e 1.27 BSC 0.050 BSC E1A1 76543 21 A B C D E F G H J K L M N P R T U E SEATING PLANE e D2D A 30ϒ φ b (119X)

Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this speci fication and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services desc ribed herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. PACKAGING INFORMATION A B C D E F G H J K L M N P R A B C D E F G H J K L M N P R 11 10 9 8 7 6 5 4 3 2 1 A1 CORNER BOTTOM VIEW D D1 e e E 1 2 3 4 5 6 7 8 9 10 11 A1 CORNER TOP VIEW A2 A φ b (165X) Ball Grid Array Package Code: B (165-pin) Notes: 1. Controlling dimensions are in millimeters. BGA - 13mm x 15mm MILLIMETERS INCHES N0. Leads 165 165

Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ Thin Quad Flat Pack (TQ) Millimeters Inches Millimeters Inches Symbol Min Max Min Max Min Max Min Max Ref. Std. No. Leads (N) 100 128 e 0.65 BSC 0.026 BSC 0.50 BSC 0.020 BSC C0 o 7o 0o 7o 0o 7o 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters. D E E1 N A2 A e b SEATING PLANE C L1 L

Product Information

128Kx36 specifications and overview.

Summary

128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

Description

128K x 32, 128K x 36, and 256K x 18 STATE BUS SRAM

Source title 128Kx36 Datasheet(PDF) - Integrated Silicon Solution, Inc

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