S3F82NB

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Copyright ©2013 Zilog®, Inc. All rights reserved. www.zilog.com Product Specification S3 Family 8-Bit Microcontrollers S3F82NB

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ii DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS. LIFE SUPPORT POLICY ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROV AL OF THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION. As used herein Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti- cal component is any component in a life support device or system whose failure to perform can be reason- ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. Document Disclaimer ©2013 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG , INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. S3 and Z8 are trademarks or registered trademarks of Zilog, Inc. All other product or service names are the property of their respective owners. Warning:

Revision History

Each instance in this document’s revision history reflects a change from its previous edi- tion. For more details, refer to the corresponding page(s) or appropriate links furnished in the table below. Date Revision Level Description Page Aug 2013 01 Original Zilog issue. A table of cont ents and PDF bookmarks will appear in the next edition, due to be published on or before Winter 2013. All

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

1 PRODUCT OVERVIEW

S3C8-SERIES MICROCONTROLLERS Samsung's S3C8 series of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Among the major CPU features are: — Efficient register-oriented architecture — Selectable CPU clock sources — Idle and Stop power-down mode release by interrupts — Built-in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum of four CPU clocks) can be assigned to specific interrupt levels. S3F82NB MICROCONTROLLER The S3F82NB single-chip CMOS microcontrollers are fabricated using the highly advanced CMOS process, based on Samsung’s newest CPU architecture. The S3F82NB is a microcontroller with a 64K-byte Flash ROM embedded. Using a proven modular design approach, Samsung engineers have successfully developed the S3F82NB by integrating the following peripheral modules with the powerful SAM8 core: — Eleven programmable I/O ports, including ten 8- bit ports, and one 3-bit port, for a total of 83 pins — Twelve bit-programmable pins for external interrupts — One 8-bit basic timer for oscillation stabilization and watchdog functions (system reset) — One 8-bit timer/counter and One 16-bit timer/counter with selectable operating modes — Watch timer for real time — LCD Controller/driver — A/D converter with 8 selectable input pins — Synchronous SIO modules — Comparator They are currently available in 128-pin QFP package

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

FEATURES

• SAM88 RC CPU core Memory
• Program Memory (ROM) - 64K /g117 8 bits program memory - Internal flash memory (program memory) ˲ Sector size: 128 bytes ˲ 10 years data retention ˲ Fast programming time: ˲ User program and sector erase available ˲ Endurance: 10,000 erase/program cycles ˲ External serial programming support ˲ Expandable OBP TM (on board program) s e c t o r
• Data Memory (RAM) - Including LCD display data memory - 4,112 /g117 8 bits data memory Instruction Set
• 78 instructions
• Idle and stop instructions added for power-down modes

83 I/O Pins

• I/O: 19 pins (Sharing with other signal pins)
• I/O: 64 pins (Sharing with LCD signal outputs) Interrupts
• 8 interrupt levels and 19 interrupt sources
• Fast interrupt processing feature 8-Bit Basic Timer
• Watchdog timer function
• 4 kinds of clock source 8-Bit Timer/Counter 0
• Programmable 8-bit internal timer
• External event counter function
• PWM and capture function Timer/Counter 1
• Programmable 16-bit internal timer
• Two 8-bit timer/counters A/B mode
• PWM and capture function
• External event counter function Watch Timer
• Interval time: 3.91mS, 0.125S, 0.25S, and 0.5S at 32.768 kHz
• 0.5/1/2/4 kHz Selectable buzzer output LCD Controller/Driver
• 80 segments and 16 common terminals
• 1/8 and 1/16 duty selectable
• Internal resistor bias selectable
• 16 level LCD contrast control by software Analog to Digital Converter
• 8-channel analog input
• 10-bit conversion resolution
• 25uS conversion time 8-bit Serial I/O Interface
• 8-bit transmit/receive mode
• 8-bit receive mode
• LSB-first or MSB-first transmission selectable
• Internal or External clock source Comparator
• 3-Channel mode: Internal reference (4-bit resolution); 16-step variable reference voltage
• 2-Channel mode: External reference Low Voltage Reset (LVR)
• Criteria voltage: 2.0V
• En/Disable by smart option (ROM address: 3FH) Two Power-Down Modes
• Idle: only CPU clock stops
• Stop: selected system clock and CPU clock stop Oscillation Sources
• Crystal, ceramic, or RC for main clock
• Main clock frequency: 0.4 MHz /g16 12.0 MHz
• 32.768 kHz crystal oscillation circuit for sub clock Instruction Execution Times
• 333nS at 12.0 MHz fx (minimum)
• 122.1uS at 32.768 kHz fxt (minimum)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FEATURES (Continued) Operating Voltage Range

• 1.8 V to 5.5 V at 0.4 /g16 4.2 MHz
• 2.2 V to 5.5 V at 0.4 /g16 12.0 MHz Operating Temperature Range
• /g16/g340/g113C to + 85/g113C Package Type
• 128-QFP-1420 Smart Option
• Low Voltage Reset (LVR) enable/disable and AV REF or P1.0/INT0 selection are at your hardwired option (ROM address 3FH)
• ISP related option selectable (ROM address 3EH)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BLOCK DIAGRAM nRESETVDD Port I/O and Interrupt Control SAM88RC CPU

64 K-byte

4,112 byte Register File XIN Basic Timer 8-Bit Timer/Counter0 Comparator SIO LCD Controller/ Driver VSS XOUT XTIN XTOUT Watchdog Timer T0CLK/AD1/P0.1 T0OUT/T0PWM/T0CAP/AD3/P0.3 8-Bit TimerA 8-Bit TimerB Timer 1 T1CLK/AD0/P0.0 T1OUT/T1PWM/T1CAP/AD2/P0.2 10-bit ADC AD0-AD7/P0.0-P0.7 CIN0/P6.0 CIN1/P6.1 CIN2/P6.2 SCK/INT7/P1.7 SO/INT6/P1.6 SI/INT5/P1.5 VLC0-VLC4 COM0-COM7 COM8-COM15/SEG0-SEG7 SEG56-SEG87/P3.0-P5.7 SEG8-SEG55 Port 0 P0.0/AD0/T1CLK P0.1/AD1/T0CLK P0.2/AD2/T1OUT/T1PWM/T1CAP P0.3/AD3/T0OUT/T0PWM/T0CAP P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 Port 1 P1.0/INT0/VREF P1.1/INT1 P1.2/INT2 P1.3/INT3 P1.4/INT4/BUZ P1.5/INT5/SI P1.6/INT6/SO P1.7/INT7/SCK P10.0-P10.7/SEG24-SEG31Port 10 Port 2 P2.0-P2.7/SEG56-SEG63 Port 5 P5.0/SEG80 P5.1/SEG81 P5.2/SEG82 P5.3/SEG83 P5.4/SEG84/INT8 P5.5/SEG85/INT9 P5.6/SEG86/INT10 P5.7/SEG87/INT11 Port 4 P4.0-P4.7/SEG72-SEG79 TEST Main OSC. Sub OSC. Low Voltage Reset Watch TimerBUZ/INT4/P1.4 AVREF/INT0/P1.0 Port 3 P3.0-P3.7/SEG64-SEG71 Port 9 P9.0-P9.7/SEG32-SEG39 Port 8 P8.0-P8.7/SEG40-SEG47 Port 7 P7.0-P7.7/SEG48-SEG55 P6.0-P6.2/CIN1-CIN2Port 6 Figure 1-1. Block Diagram

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PIN ASSIGNMENT S3F82NB 128-QFP-1420 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 VLC4 VLC3 VLC2 VLC1 VLC0 P1.7/SCK/INT7 P1.6/SO/INT6 P1.5/SI/INT5 P1.4/BUZ/INT4 VDD VSS XOUT XIN TEST XTIN XTOUT nRESET P1.3/INT3 P1.2/INT2 P1.1/INT1 P1.0/AV REF/INT0 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/T0OUT/T0PWM/T0CAP/AD3 P0.2/T1OUT/T1PWM/T1CAP/AD2 P0.1/T0CLK/AD1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 P10.4/SEG28 P10.5/SEG29 P10.6/SEG30 P10.7/SEG31 P9.0/SEG32 P9.1/SEG33 P9.2/SEG34 P9.3/SEG35 P9.4/SEG36 P9.5/SEG37 P9.6/SEG38 P9.7/SEG39 P8.0/SEG40 P8.1/SEG41 P8.2/SEG42 P8.3/SEG43 P8.4/SEG44 P8.5/SEG45 P8.6/SEG46 P8.7/SEG47 P7.0/SEG48 P7.1/SEG49 P7.2/SEG50 P7.3/SEG51 P7.4/SEG52 P7.5/SEG53 P7.6/SEG54 P7.7/SEG55 P2.0/SEG56 P2.1/SEG57 P2.2/SEG58 P2.3/SEG59 P2.4/SEG60 P2.5/SEG61 P2.6/SEG62 P2.7/SEG63 P3.0/SEG64 P3.1/SEG65 102 101 100 P0.0/T1CLK/AD0 P6.2/CIN2 P6.1/CIN1 P6.0/CIN0 P5.7/INT11/SEG87 P5.6/INT10/SEG86 P5.5/INT9/SEG85 P5.4/INT8/SEG84 P5.3/SEG83 P5.2/SEG82 P5.1/SEG81 P5.0/SEG80 P4.7/SEG79 P4.6/SEG78 P4.5/SEG77 P4.4/SEG76 P4.3/SEG75 P4.2/SEG74 P4.1/SEG73 P4.0/SEG72 P3.7/SEG71 P3.6/SEG70 P3.5/SEG69 P3.4/SEG68 P3.3/SEG67 P3.2/SEG66 COM10/SEG2 COM11/SEG3 COM12/SEG4 COM13/SEG5 COM14/SEG6 COM15/SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 P10.0/SEG24 P10.1/SEG25 P10.2/SEG26 P10.3/SEG27 Figure 1-2. S3F82NB Pin Assignments (128-QFP-1420)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PIN DESCRIPTIONS Table 1-1. S3F82NB Pin Descriptions Pin Names Pin Type Pin

Description

P0.0 P0.1 F-4 39 AD0/T1CLK AD1/T0CLK P0.2 P0.3 P0.4–P0.7 I/O I/O port with 1-bit-programmable pins; Input (P0.0 and P0.1: Schmitt trigger input) or push-pull, open-drain output and software assignable pull-ups. F-3 37 35–32 AD2/T1OUT/ T1PWM/T1CAP AD3/T0OUT/ T0PWM/T0CAP AD4–AD7 P1.0 E-5 31 INT0/ AVREF P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 I/O I/O port with 1-bit-programmable pins; Schmitt trigger Input or push-pull, open- drain output and software assignable pull- ups. Alternately used for external interrupt input (noise filters, interrupt enable and pending control). The P1.0 is configured as one of the P1.0/INT0 and AVREF by “Smart option”. E-4 30 INT1 INT2 INT3 INT4/BUZ INT5/SI INT6/SO INT7/SCK P2.0–P2.7 I/O I/O port with 1-bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. H-8 74–67 SEG56–SEG63 P3.0–P3.7 I/O I/O port with 1-bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. H-8 66–59 SEG64–SEG71 P4.0–P4.7 I/O I/O port with 1-bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. H-8 58–51 SEG72–SEG79 P5.0–P5.3 I/O I/O port with 1-bit-programmable pins; Input or push-pull, open-drain output and software assignable pull-ups. H-8 50–47 SEG80–SEG83 P5.4–P5.7 I/O I/O port with 1-bit-programmable pins; Schmitt trigger Input or push-pull, open- drain output and software assignable pull- ups. Alternately used for external interrupt input (noise filters, interrupt enable and pending control). H-9 46–43 SEG84–SEG87 INT8–INT11 P6.0–P6.1 H-26 42–41 CIN0–CIN1 P6.2 I/O I/O port with 1-bit-programmable pins; Schmitt trigger Input or push-pull output and software assignable pull-ups. H-27 40 CIN2

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 1-1. S3F82NB Pin Descriptions (Continued) Pin Names Pin Type Pin P7.0–P7.7 I/O I/O port with 4-bit-programmable pins; Input or push-pull output and software assignable pull-ups. H-10 82–75 SEG48–SEG55 P8.0–P8.7 I/O I/O port with 4-bit-programmable pins; Input or push-pull output and software assignable pull-ups. H-10 90–83 SEG40–SEG47 P9.0–P9.7 I/O I/O port with 4-bit-programmable pins; Input or push-pull output and software assignable pull-ups. H-10 98–91 SEG32–SEG39 P10.0–P10.7 I/O I/O port with 4-bit-programmable pins; Input or push-pull output and software assignable pull-ups. H-10 106–99 SEG24–SEG31 COM0–COM7 COM8–COM15 O LCD common signal output. H-4 10–3 2–123 SEG0–SEG7 SEG0–SEG7 SEG8–SEG23 O H-4 2–123 122–107 COM8–COM15 SEG24–SEG31 SEG32–SEG39 SEG40–SEG47 SEG48–SEG55 H-10 106–99 98–91 90–83 82–75 P10.0–P10.7 P9.0–P9.7 P8.0–P8.7 P7.0–P7.7 SEG56–SEG63 SEG64–SEG71 SEG72–SEG79 SEG80–SEG83 H-8 74–67 66–59 58–51 50–47 P2.0–P2.7 P3.0–P3.7 P4.0–P4.7 P5.0–P5.3 SEG84–SEG87 I/O LCD segment signal output. INT8–INT11 VLC0– VLC4 – LCD power supply pins. – 15–11 – AD0 AD1 F-4 39 P0.0/T1CLK P0.1/T0CLK AD2 AD3 AD4–AD7 I/O A/D converter analog input channels. F-3 37 35–32 P0.2/T1OUT/ T1PWM/T1CAP P0.3/T0OUT/ T0PWN/T0CAP P0.4–P0.7 AVREF – A/D converter reference voltage. The AVREF is configured as one of the P1.0/INT0 and AVREF by “Smart option”. E-5 31 P1.0/INT0

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 1-1. S3F82NB Pin Descriptions (Continued) Pin Names Pin Type Pin CIN0–CIN1 H-26 42–41 P6.0–P6.1 CIN2 I/O 3-channel comparator input CIN0, CIN1: comparator input only CIN2: comparator input or external reference input. H-27 40 P6.2 SCK I/O Serial interface clock. E-4 16 P1.7/INT7 SO I/O Serial interface data output. E-4 17 P1.6/INT6 SI I/O Serial interface data input. E-4 18 P1.5/INT5 BUZ I/O Output pin for buzzer signal. E-4 19 P1.4/INT4 T0OUT/T0PWM I/O Timer 0 clock output and PWM output. F-3 36 P0.3/AD3/ T0CAP T0CAP I/O Timer 0 capture input. F-3 36 P0.3/AD3/ T0OUT/T0PWM T0CLK I/O Timer 0 external clock input. F-4 38 P0.1/AD1 T1OUT/T1PWM I/O Timer 1 clock output and PWM output. F-3 37 P0.2/AD2/ T1CAP T1CAP I/O Timer 1 capture input. F-3 37 P0.2/AD2/ T1OUT/T1PWM T1CLK I/O Timer 1 external clock input. F-4 39 P0.0/AD0 INT0 E-5 31 P1.0/AVREF INT1–INT3 INT4 INT5 INT6 INT7 E-4 30–28 P1.1–P1.3 P1.4/BUZ P1.5/SI P1.6/SO P1.7/SCK INT8–INT11 I/O External interrupts input pins. The INT0 is configured as one of the P1.0/INT0 and AVREF by “Smart option”. SEG84–SEG87 nRESET I System reset pin B 27 – XIN XOUT – Main oscillator pins. – 23 XTIN XTOUT – Crystal oscillator pins for sub clock. – 25 TEST I Test input: it must be connected to VSS – 24 – VDD – Power supply input pins. – 20 – VSS – Ground pins. – 21 –

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OutCOM/SEG VLC1 VLC2 VLC3 Output Disable VLC0 VLC4 VSS Figure 1-10. Pin Circuit Type H-4

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Data Resistor Enable VDD I/OOutput Disable Pull-up Resistor CIRCUIT TYPE C Analog Input SEL Digital In Analog In External REF SEL External VREF In Figure 1-15. Pin Circuit Type H-27 (P6.2)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

2 ADDRESS SPACES

The S3F82NB microcontroller has two types of address space: — Internal program memory (ROM) — Internal register file A 16-bit address bus supports program memory operations. A separate 8-bit register bus carries addresses and data between the CPU and the register file. The S3F82NB has an internal 64-Kbyte Flash ROM. The 256-byte physical register space is expanded into an addressable area of 320 bytes using addressing modes. A 176-byte LCD display register file is implemented.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PROGRAM MEMORY (ROM) Program memory (ROM) stores program codes or table data. The S3F82NB has 64K bytes internal Flash program memory. The first 256 bytes of the ROM (0H–0FFH) are reserved for interrupt vector addresses. Unused locations in this address range can be used as normal program memory. If you use the vector address area to store a program code, be careful not to overwrite the vector addresses stored in these locations. The ROM address at which a program execution starts after a reset is 0100H in the S3F82NB. The reset address of ROM can be changed by a smart option only in the S3F82NB (Full-Flash Device). Refer to the chapter 18. Embedded Flash Memory Interface for more detail contents. (Decimal) 65,535 255 (Hex) FFFFH 00H0 64K-bytes Internal Program Memory Area Available ISP Sector Area Interrupt Vector Area Smart Option 3CH 3FH FFH 8FFH Figure 2-1. Program Memory Address Space

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SMART OPTION ISP reset vector change selection bit:(1) 0 = OBP reset vector address 1 = Normal vector (address 0100H) ISP reset vector address selection bits:(2) 00 = 200H(ISP area size: 256 byte) 01 = 300H(ISP area size: 512 byte) 10 = 500H(ISP area size: 1024 byte) 11 = 900H(ISP area size: 2048 byte) Not used ISP protection size selection bits:(4)(5) 00 = 256 bytes 01 = 512 bytes 10 = 1024 bytes 11 = 2048 bytes ISP protection enable/disable bit:(3) 0 = Enable (not erasable by LDC) 1 = Disable (Erasable by LDC) ROM Address: 003EH LVR enable/disable bit (Criteria Voltage: 2.0V) 0 = Disable LVR 1 = Enable LVR ROM Address: 003FH ROM Address: 003CH Not used ROM Address: 003DH Not used NOTES: 1. By setting ISP reset vector change selection bit (3E.7) to '0', user can have the available ISP area. If ISP reset vector change selection bit (3EH.7) is '1', 3EH.6 and 3EH.5 are meaningless. 2. If ISP reset vector change selection bit (3EH.7) is '0', user must change ISP reset vector address from 0100H to some address which user want to set reset address (0200H, 0300H, 0500H or 0900H). If the reset vector address is 0200H, the ISP area can be assigned from 0100H to 01FFH (256bytes). If 0300H, the ISP area can be assigned from 0100H to 02FFH (512bytes). If 0500H, the ISP area can be assigned from 0100H to 04FFH (1024bytes). If 0900H, the ISP area can be assigned from 0100H to 08FFH (2048bytes). 3. If ISP protection enable/disable bit is '0', user can't erase or program the ISP area selected by 3EH.1 and 3EH.0 in flash memory. 4. User can select suitable ISP protection size by 3EH.1 and 3EH.0. If ISP protection enable/disable bit (3EH.2) is '1', 3EH.1 and 3EH.0 are meaningless. 5. After selecting ISP reset vector address in selecting ISP protection size, don't select upper than ISP area size. These bits should be always logic "111111b". AVREF or P1.0/INT0 selection bit: 0 = AVREF 1 = P1.0/INT0 Figure 2-2. Smart Option

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Smart option is the ROM option for start condition of the chip. The ROM address used by smart option is from 003CH to 003FH. The S3F82NB only use 003EH to 003FH. When any values are written in the Smart Option area (003CH-003FH) by LDC instruction, the data of the area may be changed but the Smart Option is not affected. The data for Smart Option should be written in the Smart Option area (003CH-003FH) by OTP/MTP programmer (Writer tools).

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification REGISTER ARCHITECTURE In the S3F82NB implementation, the upper 64-byte area of register files is expanded two 64-byte areas, called set 1 and set 2. The upper 32-byte area of set 1 is further expanded two 32-byte register banks (bank 0 and bank 1), and the lower 32-byte area is a single 32-byte common area. In case of S3F82NB the total number of addressable 8-bit registers is 4,193. Of these 4,193 registers, 13 bytes are for CPU and system control registers, 68 bytes are for peripheral control and data registers, 16 bytes are used as a shared working registers, and 4,096 registers are for general-purpose use, page 0-page15 (including 176 bytes for LCD display registers and 1 byte for peripheral control register). You can always address set 1 register locations, regardless of which of the ten register pages is currently selected. Set 1 locations, however, can only be addressed using register addressing modes. The extension of register space into separately addressable areas (sets, banks, and pages) is supported by various addressing mode restrictions, the select bank instructions, SB0 and SB1, and the register page pointer (PP). Specific register types and the area (in bytes) that they occupy in the register file are summarized in Table 2-1. Table 2-1. S3F82NB Register Type Summary Register Type Number of Bytes General-purpose registers (including the 16-byte common working register area, sixteen 192-byte prime register area (including LCD data registers and peripheral control register), and sixteen 64-byte set 2 area) CPU and system control registers Mapped clock, peripheral, I/O control, and data registers 4,112 Total Addressable Bytes 4,193

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification System Registers (Register Addressing Mode) General Purpose Register (Register Addressing Mode) Bank 1 System and Peripheral Control Registers Bank 0 System and Peripheral Control Registers (Register Addressing Mode) Set1 FFH Bytes E0H DFH D0H CFH C0H Prime Data Registers (All addressing modes) LCD Display Reigster 176 Bytes Bytes Peripheral Control Register (All addressing modes) Page 15 00H B0H

1 Byte

(All Addressing Modes) Page 0 Set 2 General-Purpose Data Registers (Indirect Register, Indexed Mode, and Stack Operations) FFH FFH FFH ~~~~ ~~~ 256 Bytes Figure 2-3. Internal Register File Organization (S3F82NB)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification REGISTER PAGE POINTER (PP) The S3C8-series architecture supports the logical expansion of the physical 256-byte internal register file (using an 8-bit data bus) into as many as 16 separately addressable register pages. Page addressing is controlled by the register page pointer (PP, DFH). In the S3F82NB microcontroller, a paged register file expansion is implemented for LCD data registers, and the register page pointer must be changed to address other pages. After a reset, the page pointer's source value (lower nibble) and the destination value (upper nibble) are always "0000", automatically selecting page 0 as the source and destination page for register addressing. Register Page Pointer (PP) DFH ,Set 1, R/W Destination register page selection bits:

0000 Destination: Page 0

0001 Destination: Page 1

0010 Destination: Page 2

0011 Destination: Page 3

0100 Destination: Page 4

0101 Destination: Page 5

0110 Destination: Page 6

0111 Destination: Page 7

1000 Destination: Page 8

1001 Destination: Page 9

1010 Destination: Page 10

1011 Destination: Page 11

1100 Destination: Page 12

1101 Destination: Page 13

1110 Destination: Page 14

1111 Destination: Page 15

Source register page selection bits:

0000 Source: page 0

0001 Source: page 1

0010 Source: page 2

0011 Source: page 3

0100 Source: page 4

0101 Source: page 5

0110 Source: page 6

0111 Source: page 7

1000 Source: page 8

1001 Source: page 9

1010 Source: page 10

1011 Source: page 11

1100 Source: page 12

1101 Source: page 13

1110 Source: page 14

1111 Source: page 15

NOTES: 1. In the S3F82NB microcontroller, the internal register file is configured as sixteen pages (Pages 0-15). 2. The page 0-14 are used for general purpose register file and page 15 is used for the LCD data register (00H-AFH) and peripheral control regiser (B0H). Figure 2-4. Register Page Pointer (PP) /g3

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification /g41 PROGRAMMING TIP — Using the Page Pointer for RAM Clear (Page 0, Page 1) LD PP,#00H ; Destination /g109 0, Source /g109 0 SRP #0C0H LD R0,#0FFH ; Page 0 RAM clear starts RAMCL0 CLR @R0 DJNZ R0,RAMCL0 CLR @R0 ; R0 = 00H LD PP,#10H ; Destination /g109 1, Source /g109 0 LD R0,#0FFH ; Page 1 RAM clear starts RAMCL1 CLR @R0 DJNZ R0,RAMCL1 CLR @R0 ; R0 = 00H NOTE: You should refer to page 6-39 and use DJNZ instruction properly when DJNZ instruction is used in your program.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file, locations C0H–FFH. The upper 32-byte area of this 64-byte space (E0H–FFH) is expanded two 32-byte register banks, bank 0 and bank 1. The set register bank instructions, SB0 or SB1, are used to address one bank or the other. A hardware reset operation always selects bank 0 addressing. The upper two 32-byte areas (bank 0 and bank 1) of set 1 (E0H–FFH) contains 68 mapped system and peripheral control registers. The lower 32-byte area contains 16 system registers (D0H–DFH) and a 16-byte common working register area (C0H–CFH). You can use the common working register area as a “scratch” area for data operations being performed in other areas of the register file. Registers in set 1 location are directly accessible at all times using Register addressing mode. The 16-byte working register area can only be accessed using working register addressing (For more information about working register addressing, please refer to Chapter 3, “Addressing Modes.”) REGISTER SET 2 The same 64-byte physical space that is used for set 1 location C0H–FFH is logically duplicated to add another 64 bytes of register space. This expanded area of the register file is called set 2. For the S3F82NB, the set 2 address range (C0H–FFH) is accessible on pages 0-15. The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions. You can use only Register addressing mode to access set 1 location. In order to access registers in set 2, you must use Register Indirect addressing mode or Indexed addressing mode. The set 2 register area of page 0 is commonly used for stack operations.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PRIME REGISTER SPACE The lower 192 bytes (00H–BFH) of the S3C82NB's sixteen 256-byte register pages is called prime register area. Prime registers can be accessed using any of the seven addressing modes (see Chapter 3, "Addressing Modes.") The prime register area on page 0 is immediately addressable following a reset. In order to address prime registers on pages 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 or 15 you must set the register page pointer (PP) to the appropriate source and destination values. Page15 Page 14 Page 13 Page 3 Page 2 Page 1 FFH FCH E0H D0H C0H Set 1 Bank 0 Peripheral and I/O General-purpose CPU and system control LCD data register FFH FFH FFH FFH C0H 00H BFH Page 0 Set 2 Page 0 Prime Space 00H AFH Bank 1 FFH FFH FFH Page15B0H LCD Data Register Area Figure 2-5. Set 1, Set 2, Prime Area Register, and LCD Data Register Map

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification WORKING REGISTERS Instructions can access specific 8-bit registers or 16-bit register pairs using either 4-bit or 8-bit address fields. When 4-bit working register addressing is used, the 256-byte register file can be seen by the programmer as one that consists of 32 8-byte register groups or "slices." Each slice comprises of eight 8-bit registers. Using the two 8-bit register pointers, RP1 and RP0, two working register slices can be selected at any one time to form a 16-byte working register block. Using the register pointers, you can move this 16-byte register block anywhere in the addressable register file, except the set 2 area. The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces: — One working register slice is 8 bytes (eight 8-bit working registers, R0–R7 or R8–R15) — One working register block is 16 bytes (sixteen 8-bit working registers, R0–R15) All the registers in an 8-byte working register slice have the same binary value for their five most significant address bits. This makes it possible for each register pointer to point to one of the 24 slices in the register file. The base addresses for the two selected 8-byte register slices are contained in register pointers RP0 and RP1. After a reset, RP0 and RP1 always point to the 16-byte common area in set 1 (C0H–CFH). Each register pointer points to one 8-byte slice of the register space, selecting a total 16-byte working register block. 1 1 1 1 1 X X X RP1 (Registers R8-R15) RP0 (Registers R0-R7) Slice 32 Slice 31 ~ ~ CFH C0H FFH F8H F7H F0H FH Slice 2 Slice 1 10H Set 1 Only 0 0 0 0 0 X X X Figure 2-6. 8-Byte Working Register Areas (Slices)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification USING THE REGISTER POINTS Register pointers RP0 and RP1, mapped to addresses D6H and D7H in set 1, are used to select two movable 8-byte working register slices in the register file. After a reset, they point to the working register common area: RP0 points to addresses C0H–C7H, and RP1 points to addresses C8H–CFH. To change a register pointer value, you load a new value to RP0 and/or RP1 using an SRP or LD instruction. (see Figures 2-7 and 2-8). With working register addressing, you can only access those two 8-bit slices of the register file that are currently pointed to by RP0 and RP1. You cannot, however, use the register pointers to select a working register space in set 2, C0H–FFH, because these locations can be accessed only using the Indirect Register or Indexed addressing modes. The selected 16-byte working register block usually consists of two contiguous 8-byte slices. As a general programming guideline, it is recommended that RP0 point to the "lower" slice and RP1 point to the "upper" slice (see Figure 2-7). In some cases, it may be necessary to define working register areas in different (non- contiguous) areas of the register file. In Figure 2-8, RP0 points to the "upper" slice and RP1 to the "lower" slice. Because a register pointer can point to either of the two 8-byte slices in the working register block, you can flexibly define the working register area to support program requirements. /g41 PROGRAMMING TIP — Setting the Register Pointers SRP #70H ; RP0 /g109 70H, RP1 /g109 78H SRP1 #48H ; RP0 /g109 no change, RP1 /g109 48H, SRP0 #0A0H ; RP0 /g109 A0H, RP1 /g109 no change CLR RP0 ; RP0 /g109 00H, RP1 /g109 no change LD RP1,#0F8H ; RP0 /g109 no change, RP1 /g109 0F8H FH (R15) 0H (R0) 16-Byte Contiguous Working Register block Register File Contains 32 8-Byte Slices RP0 RP1 8H 0 0 0 0 1 X X X 0 0 0 0 0 X X X 8-Byte Slice 8-Byte Slice Figure 2-7. Contiguous 16-Byte Working Register Block

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification 16-Byte Contiguous working Register block Register File Contains 32 8-Byte Slices 0 0 0 0 0 X X X RP1 1 1 1 1 0 X X X RP0 0H (R0) 7H (R15) F0H (R0) F7H (R7) 8-Byte Slice 8-Byte Slice Figure 2-8. Non-Contiguous 16-Byte Working Register Block /g41 PROGRAMMING TIP — Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H–85H using the register pointer. The register addresses from 80H through 85H contain the values 10H, 11H, 12H, 13H, 14H, and 15H, respectively: SRP0 #80H ; RP0 /g109 80H ADD R0,R1 ; R0 /g109 R 0 + R 1 ADC R0,R2 ; R0 /g109 R0 + R2 + C ADC R0,R3 ; R0 /g109 R0 + R3 + C ADC R0,R4 ; R0 /g109 R0 + R4 + C ADC R0,R5 ; R0 /g109 R0 + R5 + C The sum of these six registers, 6FH, is located in the register R0 (80H). The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles. If the register pointer is not used to calculate the sum of these registers, the following instruction sequence would have to be used: ADD 80H,81H ; 80H /g109 (80H) + (81H) ADC 80H,82H ; 80H /g109 (80H) + (82H) + C ADC 80H,83H ; 80H /g109 (80H) + (83H) + C ADC 80H,84H ; 80H /g109 (80H) + (84H) + C ADC 80H,85H ; 80H /g109 (80H) + (85H) + C Now, the sum of the six registers is also located in register 80H. However, this instruction string takes 15 bytes of instruction code rather than 12 bytes, and its execution time is 50 cycles rather than 36 cycles.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification REGISTER ADDRESSING The S3C8-series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time. With Register (R) addressing mode, in which the operand value is the content of a specific register or register pair, you can access any location in the register file except for set 2. With working register addressing, you use a register pointer to specify an 8-byte working register space in the register file and an 8-bit register within that space. Registers are addressed either as a single 8-bit register or as a paired 16-bit register space. In a 16-bit register pair, the address of the first 8-bit register is always an even number and the address of the next register is always an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register, and the least significant byte is always stored in the next (+1) odd-numbered register. Working register addressing differs from Register addressing as it uses a register pointer to identify a specific 8-byte working register space in the internal register file and a specific 8-bit register within that space. MSB Rn LSB Rn+1 n = Even address Figure 2-9. 16-Bit Register Pair

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RP1 RP0 Register Pointers 00H All Addressing Modes Page 0 Indirect Register, Indexed Addressing Modes Page 0 Register Addressing Only Can be Pointed by Register Pointer FFH E0H BFH Control Registers System Registers Special-Purpose Registers D0H C0H Bank 1 Bank 0 NOTE: In the S3F82NB microcontroller, pages 0-15 are implemented. Pages 0-15 contain all of the addressable registers in the internal register file. Each register pointer (RP) can independently point to one of the 24 8-byte "slices" of the register file (other than set 2). After a reset, RP0 points to locations C0H-C7H and RP1 to locations C8H-CFH (that is, to the common working register area). FFH C0H Set 2 Prime Registers CFH General-Purpose Register All Addressing Modes Can be Pointed to By register Pointer LCD Data Registers Peripheral Control Registers Figure 2-10. Register File Addressing

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COMMON WORKING REGISTER AREA (C0H–CFH) After a reset, register pointers RP0 and RP1 automatically select two 8-byte register slices in set 1, locations C0H–CFH, as the active 16-byte working register block: RP0 /g111 C0H–C7H RP1 /g111 C8H–CFH This 16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages. Page 15 FFH FCH E0H D0H C0H Set 1 Following a hardware reset, register pointers RP0 and RP1 point to the common working register area, locations C0H-CFH. RP0 = RP1 = 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 0 Page 14 Page 13 FFH FFH FFH C0H 00H Peripheral Control Register Area 00H AFH FFH FFH FFH Page 3 Page 2 Page 1 FFH Page 0 Set 2 BFH Page 0 Prime Space ~ Page 15 LCD Data Register Area B0H Figure 2-11. Common Working Register Area

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification /g41 PROGRAMMING TIP — Addressing the Common Working Register Area As the following examples show, you should access working registers in the common area, locations C0H–CFH, using working register addressing mode only. Examples 1. LD 0C2H,40H ; Invalid addressing mode! Use working register addressing instead: SRP #0C0H LD R2,40H ; R2 (C2H) /g111 the value in location 40H 2. ADD 0C3H,#45H ; Invalid addressing mode! Use working register addressing instead: SRP #0C0H ADD R3,#45H ; R3 (C3H) /g111 R3 + 45H 4-BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8-byte slice of working register space. The address information stored in a register pointer serves as an addressing "window" that makes it possible for instructions to access working registers very efficiently using short 4-bit addresses. When an instruction addresses a location in the selected working register area, the address bits are concatenated in the following way to form a complete 8-bit address: — The high-order bit of the 4-bit address selects one of the register pointers ("0" selects RP0, "1" selects RP1). — The five high-order bits in the register pointer select an 8-byte slice of the register space. — The three low-order bits of the 4-bit address select one of the eight registers in the slice. As shown in Figure 2-12, the result of this operation is that the five high-order bits from the register pointer are concatenated with the three low-order bits from the instruction address to form the complete address. As long as the address stored in the register pointer remains unchanged, the three bits from the address will always point to an address in the same 8-byte register slice. Figure 2-13 shows a typical example of 4-bit working register addressing. The high-order bit of the instruction "INC R6" is "0", which selects RP0. The five high-order bits stored in RP0 (01110B) are concatenated with the three low-order bits of the instruction's 4-bit address (110B) to produce the register address 76H (01110110B).

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification 8-bit address form instruction 'LD R11, R2' RP0 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 1 Selects RP1 R11 Register address (0ABH) RP1 1 0 1 0 1 0 0 0 1 0 1 0 1 0 1 1 Specifies working register addressing Figure 2-15. 8-Bit Working Register Addressing Example

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SYSTEM AND USER STACK The S3C8-series microcontrollers use the system stack for data storage, subroutine calls and returns. The PUSH and POP instructions are used to control system stack operations. The S3F82NB architecture supports stack operations in the internal register file. Stack Operations Return addresses for procedure calls, interrupts, and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address value is always decreased by one before a push operation and increased by one after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-16. Stack contents after a call instruction Stack contents after an interrupt Top of stack Flags PCH PCL PCL PCHTop of stack Low Address High Address Figure 2-16. Stack Operations User-Defined Stacks You can freely define stacks in the internal register file as data storage locations. The instructions PUSHUI, PUSHUD, POPUI, and POPUD support user-defined stack operations. Stack Pointers (SPL, SPH) Register locations D8H and D9H contain the 16-bit stack pointer (SP) that is used for system stack operations. The most significant byte of the SP address, SP15–SP8, is stored in the SPH register (D8H), and the least significant byte, SP7–SP0, is stored in the SPL register (D9H). After a reset, the SP value is undetermined. Because only internal memory space is implemented in the S3F82NB, the SPL must be initialized to an 8-bit value in the range 00H–FFH. The SPH register is not needed and can be used as a general-purpose register, if necessary. When the SPL register contains the only stack pointer value (that is, when it points to a system stack in the register file), you can use the SPH register as a general-purpose data register. However, if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations, the value in the SPL register will overflow (or underflow) to the SPH register, overwriting any other data that is currently stored there. To avoid overwriting data in the SPH register, you can initialize the SPL value to "FFH" instead of "00H".

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification /g41 PROGRAMMING TIP — Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions: LD SPL,#0FFH ; SPL /g109 FFH ; (Normally, the SPL is set to 0FFH by the initialization ; routine) PUSH PP ; Stack address 0FEH /g109 PP PUSH RP0 ; Stack address 0FDH /g109 R P 0 PUSH RP1 ; Stack address 0FCH /g109 R P 1 PUSH R3 ; Stack address 0FBH /g109 R 3 POP R3 ; R3 /g109 Stack address 0FBH POP RP1 ; RP1 /g109 Stack address 0FCH POP RP0 ; RP0 /g109 Stack address 0FDH POP PP ; PP /g109 Stack address 0FEH

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

3 ADDRESSING MODES

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RC instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory. The S3C8-series instruction set supports seven explicit addressing modes. Not all of these addressing modes are available for each instruction. The seven addressing modes and their symbols are: — Register (R) — Indirect Register (IR) — Indexed (X) — Direct Address (DA) — Indirect Address (IA) — Relative Address (RA) — Immediate (IM)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDIRECT REGISTER ADDRESSING MODE (IR) In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6). You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location. Please note, however, that you cannot access locations C0H–FFH in set 1 using the Indirect Register addressing mode. dst Address of Operand used by Instruction OPCODE ADDRESS 8-bit Register File Address Point to One Register in Register FileOne-Operand Instruction (Example) Sample Instruction: RL @SHIFT ; Where SHIFT is the label of an 8-bit register address Program Memory Register File Value used in Instruction Execution OPERAND Figure 3-3. Indirect Register Addressing to Register File

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDIRECT REGISTER ADDRESSING MODE (Continued) dst OPCODE PAIR Points to Register Pair Example Instruction References Program Memory Sample Instructions: CALL @RR2 JP @RR2 Program Memory Register File Value used in Instruction OPERAND REGISTER Program Memory 16-Bit Address Points to Program Memory Figure 3-4. Indirect Register Addressing to Program Memory

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDIRECT REGISTER ADDRESSING MODE (Continued) dst OPCODE ADDRESS 4-bit Working Register Address Point to the Working Register (1 of 8) Sample Instruction: OR R3, @R6 Program Memory Register File src 3 LSBs Value used in Instruction OPERAND Selected RP points to start fo working register block RP0 or RP1 MSB Points to RP0 or RP1 Figure 3-5. Indirect Working Register Addressing to Register File

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDIRECT REGISTER ADDRESSING MODE (Concluded) dst OPCODE 4-bit Working Register Address Sample Instructions: LCD R5,@RR6 ; Program memory access LDE R3,@RR14 ; External data memory access LDE @RR4, R8 ; External data memory access Program Memory Register File src Value used in Instruction OPERAND Example Instruction References either Program Memory or Data Memory Program Memory or Data Memory Next 2-bit Point to Working Register Pair (1 of 4) LSB Selects Register Pair 16-Bit address points to program memory or data memory RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDEXED ADDRESSING MODE (X) Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory. Please note, however, that you cannot access locations C0H–FFH in set 1 using Indexed addressing mode. In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range –128 to +127. This applies to external memory accesses only (see Figure 3-8.) For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to that base address (see Figure 3-9). The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory, when implemented. dst/src OPCODE Two-Operand Instruction Example Point to One of the Woking Register (1 of 8) Sample Instruction: LD R0, #BASE[R1] ; Where BASE is an 8-bit immediate value Program Memory Register File x 3 LSBs Value used in Instruction OPERAND INDEX Base Address RP0 or RP1 Selected RP points to start of working register block ~~+ Figure 3-7. Indexed Addressing to Register File

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDEXED ADDRESSING MODE (Continued) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair (1 of 4) LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block dst/src OPCODE Program Memory x OFFSET 4-bit Working Register Address Sample Instructions: LDC R4, #04H[RR2] ; The values in the program address (RR2 + 04H) are loaded into register R4. LDE R4,#04H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. NEXT 2 Bits Register Pair Value used in Instruction 8-Bits 16-Bits 16-Bits Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDEXED ADDRESSING MODE (Concluded) Register File OPERAND Program Memory or Data Memory Point to Working Register Pair LSB Selects 16-Bit address added to offset RP0 or RP1 MSB Points to RP0 or RP1 Selected RP points to start of working register block Sample Instructions: LDC R4, #1000H[RR2] ; The values in the program address (RR2 + 1000H) are loaded into register R4. LDE R4,#1000H[RR2] ; Identical operation to LDC example, except that external program memory is accessed. NEXT 2 Bits Register Pair Value used in Instruction 8-Bits 16-Bits 16-Bits dst/src OPCODE Program Memory src OFFSET 4-bit Working Register Address OFFSET Figure 3-9. Indexed Addressing to Program or Data Memory

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DIRECT ADDRESS MODE (DA) In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed. The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented. Sample Instructions: LDC R5,1234H ; The values in the program address (1234H) are loaded into register R5. LDE R5,1234H ; Identical operation to LDC example, except that external program memory is accessed. dst/src OPCODE Program Memory "0" or "1" Lower Address Byte LSB Selects Program Memory or Data Memory: "0" = Program Memory "1" = Data Memory Memory Address Used Upper Address Byte Program or Data Memory Figure 3-10. Direct Addressing for Load Instructions

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DIRECT ADDRESS MODE (Continued) OPCODE Program Memory Lower Address Byte Memory Address Used Upper Address Byte Sample Instructions: JP C,JOB1 ; Where JOB1 is a 16-bit immediate address CALL DISPLAY ; Where DISPLAY is a 16-bit immediate address Next OPCODE Figure 3-11. Direct Addressing for Call and Jump Instructions

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INDIRECT ADDRESS MODE (IA) In Indirect Address (IA) mode, the instruction specifies an address located in the lowest 256 bytes of the program memory. The selected pair of memory locations contains the actual address of the next instruction to be executed. Only the CALL instruction can use the Indirect Address mode. Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory, only an 8-bit address is supplied in the instruction; the upper bytes of the destination address are assumed to be all zeros. Current Instruction Program Memory Locations 0-255 Program Memory OPCODE dst Lower Address Byte Upper Address Byte Next Instruction LSB Must be Zero Sample Instruction: CALL #40H ; The 16-bit value in program memory addresses 40H and 41H is the subroutine start address. Figure 3-12. Indirect Addressing

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RELATIVE ADDRESS MODE (RA) In Relative Address (RA) mode, a twos-complement signed displacement between – 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction. Several program control instructions use the Relative Address mode to perform conditional jumps. The instructions that support RA addressing are BTJRF, BTJRT, DJNZ, CPIJE, CPIJNE, and JR. OPCODE Program Memory Displacement Program Memory Address Used Sample Instructions: JR ULT,$+OFFSET ; Where OFFSET is a value in the range +127 to -128 Next OPCODE Signed Displacement Value Current Instruction Current PC Value Figure 3-13. Relative Addressing

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IMMEDIATE MODE (IM) In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. The operand may be one byte or one word in length, depending on the instruction used. Immediate addressing mode is useful for loading constant values into registers. (The Operand value is in the instruction) OPCODE Sample Instruction: LD R0,#0AAH Program Memory OPERAND Figure 3-14. Immediate Addressing

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

4 CONTROL REGISTERS

In this chapter, detailed descriptions of the S3F82NB control registers are presented in an easy-to-read format. You can use this chapter as a quick-reference source when writing application programs. Figure 4-1 illustrates the important features of the standard register description format. Control register descriptions are arranged in alphabetical order according to register mnemonic. More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part II of this manual. Data and counter registers are not described in detail in this reference chapter. More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part II of this manual. The locations and read/write characteristics of all mapped registers in the S3F82NB register file are listed in Table 4-1. The hardware reset value for each mapped register is described in Chapter 8, "RESET and Power- Down." Table 4-1. Set 1 Registers Register Name Mnemonic Decimal Hex R/W Location D0H–D2H is not mapped. Basic Timer Control Register BTCON 211 D3H R/W System Clock Control Register CLKCON 212 D4H R/W System Flags Register FLAGS 213 D5H R/W Register Pointer 0 RP0 214 D6H R/W Register Pointer 1 RP1 215 D7H R/W Stack Pointer (High Byte) SPH 216 D8H R/W Stack Pointer (Low Byte) SPL 217 D9H R/W Instruction Pointer (High Byte) IPH 218 DAH R/W Instruction Pointer (Low Byte) IPL 219 DBH R/W Interrupt Request Register IRQ 220 DCH R Interrupt Mask Register IMR 221 DDH R/W System Mode Register SYM 222 DEH R/W Register Page Pointer PP 223 DFH R/W

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 4-2. Set 1, Bank 0 Registers Register Name Mnemonic Decimal Hex R/W Port Group 0 Control Register PG0CON 208 D0H R/W Port Group 1 Control Register PG1CON 209 D1H R/W Port 6 Control Register P6CON 210 D2H R/W A/D Converter Data Register (High Byte) ADDATAH 224 E0H R A/D Converter Data Register (Low Byte) ADDATAL 225 E1H R A/D Converter Control Register ADCON 226 E2H R/W Timer 0 Counter Register T0CNT 227 E3H R Timer 0 Data Register T0DATA 228 E4H R/W Timer 0 Control Register T0CON 229 E5H R/W Timer B Counter Register TBCNT 230 E6H R Timer A Counter Register TACNT 231 E7H R Timer B Data Register TBDATA 232 E8H R/W Timer A Data Register TADATA 233 E9H R/W Timer B Control Register TBCON 234 EAH R/W Timer 1/A Control Register TACON 235 EBH R/W Timer Interrupt Pending Register TINTPND 236 ECH R/W Timer Interrupt Control Register TINTCON 237 EDH R/W Watch Timer Control Register WTCON 238 EEH R/W LCD Control Register LCON 239 EFH R/W LCD Mode Register LMOD 240 F0H R/W Comparator Control Register CMPCON 241 F1H R/W Comparator Result Register CMPREG 242 F2H R SIO Control Register SIOCON 243 F3H R/W SIO Data Register SIODATA 244 F4H R/W SIO Pre-Scaler Register SIOPS 245 F5H R/W Flash Memory Sector Address Register (High Byte) FMSECH 246 F6H R/W Flash Memory Sector Address Register (Low Byte) FMSECL 247 F7H R/W Flash Memory User Programming Enable Register FMUSR 248 F8H R/W Flash Memory Control Register FMCON 249 F9H R/W Oscillator Control Register OSCCON 250 FAH R/W STOP Control Register STPCON 251 FBH R/W Location FCH is not mapped. Basic Timer Counter BTCNT 253 FDH R Location FEH is not mapped. Interrupt Priority Register IPR 255 FFH R/W

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 4-3. Set 1, Bank 1 Registers Register Name Mnemonic Decimal Hex R/W Port 4 Control Register (High Byte) P4CONH 208 D0H R/W Port 4 Control Register (Low Byte) P4CONL 209 D1H R/W Port 4 Pull-up Resistor Enable Register P4PUR 210 D2H R/W Port 0 Control Register (High Byte) P0CONH 224 E0H R/W Port 0 Control Register (Low Byte) P0CONL 225 E1H R/W Port 0 Pull-up Resistor Enable Register P0PUR 226 E2H R/W Alternative Function Selection Register AFSEL 227 E3H R/W Port 1 Control Register (High Byte) P1CONH 228 E4H R/W Port 1 Control Register (Low Byte) P1CONL 229 E5H R/W Port 1 Pull-up Resistor Enable Register P1PUR 230 E6H R/W Port 1 Interrupt Pending Register P1PND 231 E7H R/W Port 1 Interrupt Control Register (High Byte) P1INTH 232 E8H R/W Port 1 Interrupt Control Register (Low Byte) P1INTL 233 E9H R/W Port 2 Control Register (High Byte) P2CONH 234 EAH R/W Port 2 Control Register (Low Byte) P2CONL 235 EBH R/W Port 2 Pull-up Resistor Enable Register P2PUR 236 ECH R/W Port 3 Pull-up Resistor Enable Register P3PUR 237 EDH R/W Port 3 Control Register (High Byte) P3CONH 238 EEH R/W Port 3 Control Register (Low Byte) P3CONL 239 EFH R/W Port 0 Data Register P0 240 F0H R/W Port 1 Data Register P1 241 F1H R/W Port 2 Data Register P2 242 F2H R/W Port 3 Data Register P3 243 F3H R/W Port 4 Data Register P4 244 F4H R/W Port 5 Data Register P5 245 F5H R/W Port 6 Data Register P6 246 F6H R/W Port 7 Data Register P7 247 F7H R/W Port 8 Data Register P8 248 F8H R/W Port 9 Data Register P9 249 F9H R/W Port 10 Data Register P10 250 FAH R/W Port 5 Interrupt Control Register P5INT 251 FBH R/W Port 5 Interrupt Pending Register P5PND 252 FCH R/W Port 5 Pull-up Resistor Enable Register P5PUR 253 FDH R/W Port 5 Control Register (High Byte) P5CONH 254 FEH R/W Port 5 Control Register (Low Byte) P5CONL 255 FFH R/W

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 4-4. Page 15 Registers Register Name Mnemonic Decimal Hex R/W Reset Source Indicating Register RESETID 176 B0H R/W

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FLAGS - System Flags Register .7 Carry Flag (C) .6 Zero Flag (Z) Bit Identifier RESET Value Read/Write Bit Addressing Mode R = Read-only W = Write-only R/W = Read/write '-' = Not used Type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) RESET value notation: '-' = Not used 'x' = Undetermined value '0' = Logic zero '1' = Logic one Bit number(s) that is/are appended to the register name for bit addressing Name of individual bit or related bits Full Register nameRegister ID Sign Flag (S)

0 Operation does not generate a carry or borrow condition

0 Operation generates carry-out or borrow into high-order bit 7

0 Operation result is a non-zero value

0 Operation result is zero

0 Operation generates positive number (MSB = "0")

0 Operation generates negative number (MSB = "1")

(hexadecimal) .7 .6 .5 xxx R/W R/W R/W Register addressing mode only x R/W x R/W x R/W x R/W R/W Bit number: MSB = Bit 7 LSB = Bit 0 Figure 4-1. Register Description Format

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ADCON — A/D Converter Control Register E2H Set 1, Bank 0 RESET Value /g16/g3 0 0 0 0 0 0 0 Read/Write /g16/g3R/W R/W R/W R R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used for the S3F82NB .6–.4 A/D Input Pin Selection Bits 0 0 0 AD0 0 0 1 AD1 0 1 0 AD2 0 1 1 AD3 1 0 0 AD4 1 0 1 AD5 1 1 0 AD6 1 1 1 AD7 .3 End-of-Conversion Bit (Read-only)

0 Conversion not complete

1 Conversion complete

.2–.1 Clock Source Selection Bits 0 0 fxx/16 0 1 fxx/8 1 0 fxx/4 1 1 fxx/1 .0 Start or Enable Bit

0 Disable operation

1 Start operation

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification AFSEL — Alternative Function Selection Register E3H Set 1, Bank 1 RESET Value /g16/g3 /g16/g3 /g16/g3 /g16/g3 /g16/g3 /g16/g3 0 0 Read/Write /g16/g3 /g16/g3 /g16/g3 /g16/g3 /g16/g3 /g16/g3R/W R/W Addressing Mode Register addressing mode only .7–.2 Not used for the S3F82NB .1 P0.3 Alternative Mode Selection Bit

0 Alternative function (AD3)

1 Alternative function (T0OUT/T0PWM)

.0 P0.2 Alternative Mode Selection Bit

0 Alternative function (AD2)

1 Alternative function (T1OUT/T1PWM)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BTCON — Basic Timer Control Register D3H Set 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Watchdog Timer Function Disable Code (for System Reset) 1 0 1 0 Disable watchdog timer function Others Enable watchdog timer function .3–.2 Basic Timer Input Clock Selection Bits (3) 0 0 fxx/4096 0 1 fxx/1024 1 0 fxx/128 1 1 fxx /16 .1 Basic Timer Counter Clear Bit (1)

0 No effect

1 Clear the basic timer counter value

.0 Clock Frequency Divider Clear Bit for Basic Timer and Timer/Counters (2)

1 Clear both clock frequency dividers

NOTES: 1. When you write a “1” to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to “0”. 2. When you write a "1" to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0". 3. The fxx is selected clock for system (main OSC. or sub OSC.).

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CLKCON — System Clock Control Register D4H Set 1 RESET Value 0 /g16/g16 0 0 /g16/g16/g16 Read/Write R/W /g16/g16 R/W R/W /g16/g16/g16 Addressing Mode Register addressing mode only .7 Oscillator IRQ Wake-up Function Bit

0 Enable IRQ for main wake-up in power down mode

1 Disable IRQ for main wake-up in power down mode

.6–.5 Not used for the S3F82NB .4–.3 CPU Clock (System Clock) Selection Bits (note) 0 0 fxx/16 0 1 fxx/8 1 0 fxx/2 1 1 fxx/1 .2–.0 Not used for the S3F82NB NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster clock speeds, load the appropriate values to CLKCON.3 and CLKCON.4.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CMPCON — Comparator Control Register F1H Set 1, Bank 0 RESET Value 0 0 0 – 0 0 0 0 Read/Write R/W R/W R/W – R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Comparator Enable Bit

0 Disable Comparator

1 Enable Comparator

.6 Conversion Time Selection Bit 0 8 X 25/fx 1 8 X 24 /fx .5 External/Internal Reference Selection Bit

0 Internal reference, CIN0–CIN2; analog input

1 CIN2; External reference, CIN0–CIN1; analog input

.4 Not used, But you must keep “0” .3–.0 Reference Voltage Selection Bits Selected VREF= VDD X (N+0.5)/16, N = 0 to 15

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FLAGS — System Flags Register D5H Set 1 RESET Value x x x x x x 0 0 Read/Write R/W R/W R/W R/W R/W R/W R R/W Addressing Mode Register addressing mode only .7 Carry Flag (C)

1 Operation generates a carry-out or borrow into high-order bit 7

.6 Zero Flag (Z)

1 Operation result is zero

.5 Sign Flag (S)

0 Operation generates a positive number (MSB = "0")

1 Operation generates a negative number (MSB = "1")

.4 Overflow Flag (V)

0 Operation result is /g100 +127 or /g116 –128

1 Operation result is > +127 or < –128

.3 Decimal Adjust Flag (D)

0 Add operation completed

1 Subtraction operation completed

.2 Half-Carry Flag (H)

0 No carry-out of bit 3 or no borrow into bit 3 by addition or subtraction

1 Addition generated carry-out of bit 3 or subtraction generated borrow into bit 3

.1 Fast Interrupt Status Flag (FIS)

0 Interrupt return (IRET) in progress (when read)

1 Fast interrupt service routine in progress (when read)

.0 Bank Address Selection Flag (BA)

0 Bank 0 is selected

1 Bank 1 is selected

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FMCON — Flash Memory Control Register F9H Set 1, Bank 0 RESET Value 0 0 0 0 0 /g16/g16 0 Read/Write R/W R/W R/W R/W R /g16/g16 R/W Addressing Mode Register addressing mode only .7–.4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode 1 0 1 0 Sector erase mode 0 1 1 0 Hard lock mode Others Not available .3 Sector Erase Status Bit (Read-only)

0 Success sector erase

1 Fail sector erase

.2–.1 Not used for the S3F82NB .0 Flash Operation Start Bit

0 Operation stop bit

1 Operation start bit

NOTE: The FMCON.0 will be cleared automatically just after the corresponding operation completed.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FMSECH — Flash Memory Sector Address Register (High Byte) F6H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Flash Memory Sector Address Bits (High Byte) The 15th-8th to select a sector of Flash ROM NOTE: The high-byte flash memory sector address pointer value is higher eight bits of the 16-bit pointer address. FMSECL — Flash Memory Sector Address Register (Low Byte) F7H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Flash Memory Sector Address Bit (Low Byte) The 7th bit to select a sector of Flash ROM .6–.0 Don’t care NOTE: The low-byte flash memory sector address pointer value is lower eight bits of the 16-bit pointer address.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FMUSR — Flash Memory User Programming Enable Register F8H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Flash Memory User Programming Enable Bits 1 0 1 00101 E nable user programming mode Others Disable user programming mode

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IMR — Interrupt Mask Register DDH Set 1 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Interrupt Level 7 (IRQ7) Enable Bit; External Interrupts P5.4–P5.7

0 Disable (mask)

1 Enable (unmask)

.6 Interrupt Level 6 (IRQ6) Enable Bit; External Interrupts P1.4–P1.7 .5 Interrupt Level 5 (IRQ5) Enable Bit; External Interrupts P1.0–P1.3 .4 Interrupt Level 4 (IRQ4) Enable Bit; Watch Timer .3 Interrupt Level 3 (IRQ3) Enable Bit; SIO .2 Interrupt Level 2 (IRQ2) Enable Bit; Timer B Match .1 Interrupt Level 1 (IRQ1) Enable Bit; Timer 1/A Match/Capture or Overflow .0 Interrupt Level 0 (IRQ0) Enable Bit; Timer 0 Match/Capture or Overflow NOTE: When an interrupt level is masked, any interrupt requests that may be issued are not recognized by the CPU.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IPH — Instruction Pointer (High Byte) DAH Set 1 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (High Byte) The high-byte instruction pointer value is the upper eight bits of the 16-bit instruction pointer address (IP15–IP8). The lower byte of the IP address is located in the IPL register (DBH). IPL — Instruction Pointer (Low Byte) DBH Set 1 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Instruction Pointer Address (Low Byte) The low-byte instruction pointer value is the lower eight bits of the 16-bit instruction pointer address (IP7–IP0). The upper byte of the IP address is located in the IPH register (DAH).

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IPR — Interrupt Priority Register FFH Set 1, Bank 0 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7, .4, and .1 Priority Control Bits for Interrupt Groups A, B, and C 0 0 0 Group priority undefined 0 0 1 B > C > A 0 1 0 A > B > C 0 1 1 B > A > C 1 0 0 C > A > B 1 0 1 C > B > A 1 1 0 A > C > B 1 1 1 Group priority undefined .6 Interrupt Subgroup C Priority Control Bit

0 IRQ6 > IRQ7

1 IRQ7 > IRQ6

.5 Interrupt Group C Priority Control Bit

0 IRQ5 > (IRQ6, IRQ7)

1 (IRQ6, IRQ7) > IRQ5 .3 Interrupt Subgroup B Priority Control Bit

0 IRQ3 > IRQ4

1 IRQ4 > IRQ3

.2 Interrupt Group B Priority Control Bit

0 I R Q 2 > ( I R Q 3 , I R Q 4 )

1 (IRQ3, IRQ4) > IRQ2 .0 Interrupt Group A Priority Control Bit

0 IRQ0 > IRQ1

1 IRQ1 > IRQ0

NOTE: Interrupt group A -IRQ0, IRQ1 Interrupt group B -IRQ2, IRQ3, IRQ4 Interrupt group C -IRQ5, IRQ6, IRQ7

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IRQ — Interrupt Request Register DCH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Addressing Mode Register addressing mode only .7 Level 7 (IRQ7) Request Pending Bit; External Interrupts P5.4–P5.7

0 Not pending

1 Pending

.6 Level 6 (IRQ6) Request Pending Bit; External Interrupts P1.4–P1.7 .5 Level 5 (IRQ5) Request Pending Bit; External Interrupts P1.0–P1.3 .4 Level 4 (IRQ4) Request Pending Bit; Watch Timer .3 Level 3 (IRQ3) Request Pending Bit; SIO .2 Level 2 (IRQ2) Request Pending Bit; Timer B Match .1 Level 1 (IRQ1) Request Pending Bit; Timer 1/A Match/Capture or Overflow .0 Level 0 (IRQ0) Request Pending Bit; Timer 0 Match/Capture or Overflow

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCON — LCD Control Register EFH Set 1, Bank 0 RESET Value 0 0 0 0 0 /g16/g16 0 Read/Write R/W R/W R/W R/W R/W /g16/g16 R/W Addressing Mode Register addressing mode only .7–.5 LCD Clock Selection Bits 0 0 0 fw/27 (256 Hz) 0 0 1 fw/26 (512 Hz) 0 1 0 fw/25 (1024 Hz) 0 1 1 fw/24 (2048 Hz) 1 0 0 fw/23 (4096 Hz) Others Not available .4 LCD Bias Selection Bit 0 1/4 bias 1 1/5 bias .3 LCD Duty Selection Bit 0 1/8 duty 1 1/16 duty .2–.1 Not used for the S3F82NB .0 LCD Display Control Bits

0 Display off

1 Display on

NOTES: The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data value is re-write. So, the LCON register don’t re-write frequently.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LMOD — LCD Mode Control Register F1H Set 1, Bank 0 RESET Value 0 0 0 0 0 /g16/g16/g16 Read/Write R/W R/W R/W R/W R/W /g16/g16/g16 Addressing Mode Register addressing mode only .7–.4 LCD Contrast Level Control Bits 0 0 0 0 1/16 step (The dimmest level) 0 0 0 1 2/16 step 0 0 1 0 3/16 step 0 0 1 1 4/16 step 0 1 0 0 5/16 step 0 1 0 1 6/16 step 0 1 1 0 7/16 step 0 1 1 1 8/16 step 1 0 0 0 9/16 step 1 0 0 1 10/16 step 1 0 1 0 11/16 step 1 0 1 1 12/16 step 1 1 0 0 13/16 step 1 1 0 1 14/16 step 1 1 1 0 15/16 step 1 1 1 1 16/16 step (The brightest level) .3 Enable/Disable LCD Contrast Control Bit

0 Disable LCD contrast control

1 Enable LCD contrast control

.2–.0 Not used for the S3F82NB NOTES: VLCD = VDD x (n+17)/32, where n = 0 - 15.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OSCCON — Oscillator Control Register FAH Set 1, Bank 0 RESET Value /g16/g16/g16/g16 0 0 /g16 0 Read/Write /g16/g16/g16/g16 R/W R/W /g16 R/W Addressing Mode Register addressing mode only .7–.4 Not used for the S3F82NB .3 Main Oscillator Control Bit

0 Main oscillator RUN

1 Main oscillator STOP

.2 Sub Oscillator Control Bit

0 Sub oscillator RUN

1 Sub oscillator STOP

.1 Not used for the S3F82NB .0 System Clock Selection Bit

0 Select main oscillator for system clock

1 Select sub oscillator for system clock

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P0CONH — Port 0 Control Register (High Byte) E0H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.7/AD7 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD7) .5–.4 P0.6/AD6 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD6) .3–.2 P0.5/AD5 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD5) .1–.0 P0.4/AD4 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD4)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P0CONL — Port 0 Control Register (Low Byte) E1H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P0.3/AD3/T0OUT/T0PWM/T0CAP Configuration Bits 0 0 Input mode (T0CAP) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD3 or T0OUT/T0PWM) .5–.4 P0.2/AD2/T1OUT/T1PWM/T1CAP Configuration Bits 0 0 Input mode (T1CAP) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD2 or T1OUT/T1PWM) .3–.2 P0.1/AD1/T0CLK Configuration Bits 0 0 Schmitt trigger input mode (T0CLK) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD1) .1–.0 P0.0/AD0/T1CLK Configuration Bits 0 0 Schmitt trigger input mode (T1CLK) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (AD0)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P0PUR — Port 0 Pull-up Resistor Enable Register E2H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P0.7 Pull-up Resistor Enable Bit

0 Pull-up disable

1 Pull-up enable

.6 P0.6 Pull-up Resistor Enable Bit .5 P0.5 Pull-up Resistor Enable Bit .4 P0.4 Pull-up Resistor Enable Bit .3 P0.3 Pull-up Resistor Enable Bit .2 P0.2 Pull-up Resistor Enable Bit .1 P0.1 Pull-up Resistor Enable Bit .0 P0.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1CONH — Port 1 Control Register (High Byte) E4H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7/INT7/SCK Configuration Bits 0 0 Schmitt trigger input mode (SCK) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SCK out) .5–.4 P1.6/INT6/SO Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SO) .3–.2 P1.5/INT5/SI Configuration Bits 0 0 Schmitt trigger input mode (SI) 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Not available .1–.0 P1.4/INT4/BUZ Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (BUZ)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1CONL — Port 1 Control Register (Low Byte) E5H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3/INT3 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Not available .5–.4 P1.2/INT2 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Not available .3–.2 P1.1/INT1 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Not available .1–.0 P1.0/INT0/ AVREF T Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Not available NOTE: Refer to the SMART OPTION for configuring as one of the P1.0/INT0 and AV REF.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1PUR — Port 1 Pull-up Resistor Enable Register E6H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7 Pull-up Resistor Enable Bit .6 P1.6 Pull-up Resistor Enable Bit .5 P1.5 Pull-up Resistor Enable Bit .4 P1.4 Pull-up Resistor Enable Bit .3 P1.3 Pull-up Resistor Enable Bit .2 P1.2 Pull-up Resistor Enable Bit .1 P1.1 Pull-up Resistor Enable Bit .0 P1.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1INTH — Port 1 Interrupt Control Register (High Byte) E8H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.7/External interrupt (INT7) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .5–.4 P1.6/External interrupt (INT6) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .3–.2 P1.5/External interrupt (INT5) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .1–.0 P1.4/External interrupt (INT4) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1INTL — Port 1 Interrupt Control Register (Low Byte) E9H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P1.3/External interrupt (INT3) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .5–.4 P1.2/External interrupt (INT2) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .3–.2 P1.1/External interrupt (INT1) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .1–.0 P1.0/External interrupt (INT0) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P1PND — Port 1 Interrupt Pending Register E7H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P1.7/External Interrupt (INT7) Pending Bit

0 Clear pending bit (when write)

1 P1.7/INT7 interrupt request is pending (when read) .6 P1.6/External Interrupt (INT6) Pending Bit 1 P1.6/INT6 interrupt request is pending (when read) .5 P1.5/External Interrupt (INT5) Pending Bit 1 P1.5/INT5 interrupt request is pending (when read) .4 P1.4/External Interrupt (INT4) Pending Bit 1 P1.4/INT4 interrupt request is pending (when read) .3 P1.3/External Interrupt (INT3) Pending Bit 1 P1.3/INT3 interrupt request is pending (when read) .2 P1.2/External Interrupt (INT2) Pending Bit 1 P1.2/INT2 interrupt request is pending (when read) .1 P1.1/External Interrupt (INT1) Pending Bit 1 P1.1/INT1 interrupt request is pending (when read) .0 P1.0/External Interrupt (INT0) Pending Bit 1 P1.0/INT0 interrupt request is pending (when read)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P2CONH — Port 2 Control Register (High Byte) EAH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.7/SEG63 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG63) .5-.4 P2.6/SEG62 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG62) .3–.2 P2.5/SEG61 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG61) .1–.0 P2.4/SEG60 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG60)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P2CONL — Port 2 Control Register (Low Byte) EBH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P2.3/SEG59 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG59) .5-.4 P2.2/SEG58 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG58) .3–.2 P2.1/SEG57 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG57) .1–.0 P2.0/SEG56 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG56)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P2PUR — Port 2 Pull-up Resistor Enable Register ECH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P2.7 Pull-up Resistor Enable Bit .6 P2.6 Pull-up Resistor Enable Bit .5 P2.5 Pull-up Resistor Enable Bit .4 P2.4 Pull-up Resistor Enable Bit .3 P2.3 Pull-up Resistor Enable Bit .2 P2.2 Pull-up Resistor Enable Bit .1 P2.1 Pull-up Resistor Enable Bit .0 P2.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 2 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P3CONH — Port 3 Control Register (High Byte) EEH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.7/SEG71 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG71) .5–.4 P3.6/SEG70 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG70) .3–.2 P3.5/SEG69 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG69) .1–.0 P3.4/SEG68 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG68)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P3CONL — Port 3 Control Register (Low Byte) EFH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P3.3/SEG67 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG67) .5–.4 P3.2/SEG66 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG66) .3–.2 P3.1/SEG65 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG65) .1–.0 P3.0/SEG64 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG64)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P3PUR — Port 3 Pull-up Resistor Enable Register EDH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P3.7 Pull-up Resistor Enable Bit .6 P3.6 Pull-up Resistor Enable Bit .5 P3.5 Pull-up Resistor Enable Bit .4 P3.4 Pull-up Resistor Enable Bit .3 P3.3 Pull-up Resistor Enable Bit .2 P3.2 Pull-up Resistor Enable Bit .1 P3.1 Pull-up Resistor Enable Bit .0 P3.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 3 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P4CONH — Port 4 Control Register (High Byte) D0H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.7/SEG79 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG79) .5–.4 P4.6/SEG78 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG78) .3–.2 P4.5/SEG77 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG77) .1–.0 P4.4/SEG76 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG76)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P4CONL — Port 4 Control Register (Low Byte) D1H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P4.3/SEG75 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG75) .5–.4 P4.2/SEG74 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG74) .3–.2 P4.1/SEG73 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG73) .1–.0 P4.0/SEG72 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG72)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P4PUR — Port 4 Pull-up Resistor Enable Register D2H Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P4.7 Pull-up Resistor Enable Bit .6 P4.6 Pull-up Resistor Enable Bit .5 P4.5 Pull-up Resistor Enable Bit .4 P4.4 Pull-up Resistor Enable Bit .3 P4.3 Pull-up Resistor Enable Bit .2 P4.2 Pull-up Resistor Enable Bit .1 P4.1 Pull-up Resistor Enable Bit .0 P4.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 4 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P5CONH — Port 5 Control Register (High Byte) FEH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.7/SEG87/INT11 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG87) .5–.4 P5.6/SEG86/INT10 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG86) .3–.2 P5.5/SEG85/INT9 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG85) .1–.0 P5.4/SEG84/INT8 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG84)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P5CONL — Port 5 Control Register (Low Byte) FFH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.3/SEG83 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG83) .5–.4 P5.2/SEG82 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG82) .3–.2 P5.1/SEG81 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG81) .1–.0 P5.0/ SEG80 Configuration Bits 0 0 Input mode 0 1 Output mode, open-drain 1 0 Output mode, push-pull 1 1 Alternative function (SEG80)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P5PUR — Port 5 Pull-up Resistor Enable Register FDH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 P5.7 Pull-up Resistor Enable Bit .6 P5.6 Pull-up Resistor Enable Bit .5 P5.5 Pull-up Resistor Enable Bit .4 P5.4 Pull-up Resistor Enable Bit .3 P5.3 Pull-up Resistor Enable Bit .2 P5.2 Pull-up Resistor Enable Bit .1 P5.1 Pull-up Resistor Enable Bit .0 P5.0 Pull-up Resistor Enable Bit NOTE: A pull-up resistor of port 5 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function.

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P5INT — Port 5 Interrupt Control Register FBH Set 1, Bank 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P5.7/External Interrupt (INT11) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .5–.4 P5.6/External Interrupt (INT10) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .3–.2 P5.5/External Interrupt (INT9) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge .1–.0 P5.4/External Interrupt (INT8) Enable Bits 0 0 Disable interrupt 0 1 Enable interrupt by falling edge 1 0 Enable interrupt by rising edge 1 1 Enable interrupt by both falling and rising edge

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P5PND — Port 5 Interrupt Pending Register FCH Set 1, Bank 1 RESET Value 0 0 0 0 /g16/g16/g16/g16 Read/Write R/W R/W R/W R/W /g16/g16/g16/g16 Addressing Mode Register addressing mode only .7 P5.7/External Interrupt (INT11) Pending Bit 1 P5.7/INT11 interrupt request is pending (when read) .6 P5.6/External Interrupt (INT10) Pending Bit 1 P5.6/INT10 interrupt request is pending (when read) .5 P5.5/External Interrupt (INT9) Pending Bit 1 P5.5/INT9 interrupt request is pending (when read) .4 P5.4/External Interrupt (INT8) Pending Bit 1 P5.4/INT8 interrupt request is pending (when read) .3–.0 Not used for the S3F82NB

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification P6CON — Port 6 Control Register D2H Set 1, Bank 0 RESET Value /g16/g16 0 0 0 0 0 0 Read/Write /g16/g16 R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 Not used for the S3F82NB .5–.4 P6.2/CIN2 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (CIN2) .3–.2 P6.1/CIN1 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (CIN1) .1–.0 P6.0/CIN0 Configuration Bits 0 0 Schmitt trigger input mode 0 1 Schmitt trigger input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (CIN0)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PG0CON — Port Group 0 Control Register D0H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P10.4–P10.7/SEG28–SEG31 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG28 –SEG31) .5–.4 P10.0–P10.3/SEG24–SEG27 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG24 –SEG27) .3–.2 P9.4–P9.7/SEG36–SEG39 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG36 –SEG39) .1–.0 P9.0–P9.3/SEG32–SEG35 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG32 –SEG35)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PG1CON — Port Group 1 Control Register D1H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.6 P8.4–P8.7/SEG44–SEG47 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG44 –SEG47) .5–.4 P8.0–P8.3/SEG40–SEG43 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG40 –SEG43) .3–.2 P7.4–P7.7/SEG52–SEG55 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG52 –SEG55) .1–.0 P7.0–P7.3/SEG48–SEG51 Configuration Bits 0 0 Input mode 0 1 Input mode, pull-up 1 0 Output mode, push-pull 1 1 Alternative function (SEG48 –SEG51)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PP — Register Page Pointer DFH Set 1 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.4 Destination Register Page Selection Bits 0 0 0 0 Destination: page 0 0 0 0 1 Destination: page 1 0 0 1 0 Destination: page 2 0 0 1 1 Destination: page 3 0 1 0 0 Destination: page 4 0 1 0 1 Destination: page 5 0 1 1 0 Destination: page 6 0 1 1 1 Destination: page 7 1 0 0 0 Destination: page 8 1 0 0 1 Destination: page 9 1 0 1 0 Destination: page 10 1 0 1 1 Destination: page 11 1 1 0 0 Destination: page 12 1 1 0 1 Destination: page 13 1 1 1 0 Destination: page 14 1 1 1 1 Destination: page 15 .3 – .0 Source Register Page Selection Bits 0 0 0 0 Source: page 0 0 0 0 1 Source: page 1 0 0 1 0 Source: page 2 0 0 1 1 Source: page 3 0 1 0 0 Source: page 4 0 1 0 1 Source: page 5 0 1 1 0 Source: page 6 0 1 1 1 Source: page 7 1 0 0 0 Source: page 8 1 0 0 1 Source: page 9 1 0 1 0 Source: page 10 1 0 1 1 Source: page 11 1 1 0 0 Source: page 12 1 1 0 1 Source: page 13 1 1 1 0 Source: page 14 1 1 1 1 Source: page 15

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RP0 — Register Pointer 0 D6H Set 1 RESET Value 1 1 0 0 0 /g16/g16/g16 Read/Write R/W R/W R/W R/W R/W /g16/g16/g16 Addressing Mode Register addressing only .7–.3 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP0 points to address C0H in register set 1, selecting the 8-byte working register slice C0H–C7H. .2–.0 Not used for the S3F82NB RP1 — Register Pointer 1 D7H Set 1 RESET Value 1 1 0 0 1 /g16/g16/g16 Read/Write R/W R/W R/W R/W R/W /g16/g16/g16 Addressing Mode Register addressing only .7 – .3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256-byte working register areas in the register file. Using the register pointers RP0 and RP1, you can select two 8-byte register slices at one time as active working register space. After a reset, RP1 points to address C8H in register set 1, selecting the 8-byte working register slice C8H–CFH. .2 – .0 Not used for the S3F82NB 100

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RESETID — Reset Source Indicating Register B0H Page 15 Read/Write /g16/g16/g16 R/W /g16 R/W R/W /g16 Addressing Mode Register addressing mode only .7– .5 Not used for the S3F82NB .4 nRESET Pin Indicating Bit

0 Reset is not generated by nReset Pin (when read), cleared to ‘0’(when write)

1 Reset is generated by nReset Pin (when read), no effect (when write)

.3 Not used for the S3F82NB .2 WDT Reset Indicating Bit

0 Reset is not generated by WDT (when read), cleared to ‘0’(when write)

1 Reset is generated by WDT (when read), no effect (when write)

.1 LVR Reset Indicating Bit

0 Reset is not generated by LVR (when read), cleared to ‘0’(when write)

1 Reset is generated by LVR (when read), no effect (when write)

.0 Not used for the S3F82NB State of RESETID Depends on Reset Source LVR /g16/g16/g16 0 /g16 0 1 /g16 WDT, nRESET /g16/g16/g16 Note3 /g16 Note3 Note2 /g16 NOTES: has no effect. 2. Not effected by any other reset. 3. Bits corresponding to sources that are active at the time of reset will be set. 4. The RESETID.2–.1 are unknown values when a power-on reset occurs. 101

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SIOCON — SIO Control Register F3H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 SIO Shift Clock Selection Bit 0 Internal clock (P.S clock)

1 External clock (SCK)

.6 Data Direction Control Bit

0 MSB-first mode

1 LSB-first mode

.5 SIO Mode Selection Bit

0 Receive-only mode

1 Transmit/Receive mode

.4 Shift Clock Edge Selection Bit

0 Tx at falling edges, Rx at rising edges

1 Tx at rising edges, Rx at falling edges

.3 SIO Counter Clear and Shift Start Bit

0 No action

1 Clear 3-bit counter and start shifting

.2 SIO Shift Operation Enable Bit

0 Disable shifter and clock counter

1 Enable shifter and clock counter

.1 SIO Interrupt Enable Bit

0 Disable SIO Interrupt

1 Enable SIO Interrupt

.0 SIO Interrupt Pending Bit

0 No interrupt pending (when read), Clear pending condition (when write)

1 Interrupt is pending

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SPH — Stack Pointer (High Byte) D8H Set 1 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (High Byte) The high-byte stack pointer value is the upper eight bits of the 16-bit stack pointer address (SP15–SP8). The lower byte of the stack pointer value is located in register SPL (D9H). The SP value is undefined following a reset. SPL — Stack Pointer (Low Byte) D9H Set 1 RESET Value x x x x x x x x Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 Stack Pointer Address (Low Byte) The low-byte stack pointer value is the lower eight bits of the 16-bit stack pointer address (SP7–SP0). The upper byte of the stack pointer value is located in register SPH (D8H). The SP value is undefined following a reset. 103

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification STPCON — Stop Control Register FBH Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.0 STOP Control Bits 1 0 1 0 0 1 0 1 Enable stop instruction Other values Disable stop instruction NOTE: Before execute the STOP instruction. You must set this STPCON register as “10100101b”. Otherwise the STOP instruction will not execute as well as reset will be generated. 104

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SYM — System Mode Register DEH Set 1 RESET Value 0 /g16/g16 x x x 0 0 Read/Write R/W /g16/g16 R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Not used, But you must keep “0” .6–.5 Not used for the S3F82NB .4–.2 Fast Interrupt Level Selection Bits (1) 0 0 0 IRQ0 0 0 1 IRQ1 0 1 0 IRQ2 0 1 1 IRQ3 1 0 0 IRQ4 1 0 1 IRQ5 1 1 0 IRQ6 1 1 1 IRQ7 .1 Fast Interrupt Enable Bit (2)

0 Disable fast interrupt processing

1 Enable fast interrupt processing

.0 Global Interrupt Enable Bit (3)

0 Disable all interrupt processing

1 Enable all interrupt processing

NOTES: 1. You can select only one interrupt level at a time for fast interrupt processing. 3. Following a reset, you must enable global interrupt processing by executing an EI instruction (not by writing a "1" to SYM.0). 105

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification T0CON — Timer 0 Control Register E5H Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 /g16 Read/Write R/W R/W R/W R/W R/W R/W R/W /g16 Addressing Mode Register addressing mode only .7–.5 Timer 0 Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx/1 1 0 1 External clock (T0CLK) falling edge 1 1 0 External clock (T0CLK) rising edge 1 1 1 Not available .4–.3 Timer 0 Operating Mode Selection Bits 0 0 Interval mode (T0OUT) 0 1 Capture mode (Capture on rising edge, counter running, OVF can occur) 1 0 Capture mode (Capture on falling edge, counter running, OVF can occur) 1 1 PWM mode (OVF and match interrupt can occur) .2 Timer 0 Counter Clear Bit

1 Clear the timer 0 counter (when write)

.1 Timer 0 Counter Operating Enable Bit

0 Disable counting operation

1 Enable counting operation

.0 Not used for the S3F82NB 106

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TACON — Timer 1/A Control Register EBH Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Timer 1/A Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx/1 1 0 1 External clock (T1CLK) falling edge 1 1 0 External clock (T1CLK) rising edge 1 1 1 Not available .4–.3 Timer 1/A Operating Mode Selection Bits 0 0 Interval mode (T1OUT) 0 1 Capture mode (Capture on rising edge, counter running, OVF can occur) 1 0 Capture mode (Capture on falling edge, counter running, OVF can occur) 1 1 PWM mode (OVF and match interrupt can occur) .2 Timer 1/A Counter Clear Bit

1 Clear the timer 1/A counter (when write)

.1 Timer 1/A Match/Capture Interrupt Enable Bit .0 Timer 1/A Operating Mode Selection Bit

0 Two 8-bit timers mode (Timer A/B)

1 One 16-bit timer mode (Timer 1)

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TBCON — Timer B Control Register EAH Set 1, Bank 0 RESET Value 0 0 0 /g16/g16 0 0 /g16 Read/Write R/W R/W R/W /g16/g16 R/W R/W /g16 Addressing Mode Register addressing mode only .7–.5 Timer B Input Clock Selection Bits 0 0 0 fxx/1024 0 0 1 fxx/256 0 1 0 fxx/64 0 1 1 fxx/8 1 0 0 fxx/1 Others Not available .4–.3 Not used for the S3F82NB .2 Timer B Counter Clear Bit

1 Clear the timer B counter (when write)

.1 Timer B Counter Operating Enable Bit .0 Not used for the S3F82NB 108

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TINTCON — Timer Interrupt Control Register EDH Set 1, Bank 0 RESET Value /g16/g16/g16 0 0 0 0 0 Read/Write /g16/g16/g16 R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Not used for the S3F82NB .4 Timer B Interrupt Enable Bit

0 Disable interrupt

1 Enable interrupt

.3 Timer 1/A Match/Capture Interrupt Enable Bit .2 Timer 1/A Overflow Interrupt Enable Bit .1 Timer 0 Match/Capture Interrupt Enable Bit .0 Timer 0 Overflow Interrupt Enable Bit

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TINTPND — Timer Interrupt Pending Register ECH Set 1, Bank 0 RESET Value /g16/g16/g16 0 0 0 0 0 Read/Write /g16/g16/g16 R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7–.5 Not used for the S3F82NB .4 Timer B Interrupt Pending Bit

0 No interrupt pending (when read), clear pending bit (when write)

1 Interrupt is pending (when read)

.3 Timer 1/A Match/Capture Interrupt Pending Bit .2 Timer 1/A Overflow Interrupt Pending Bit .1 Timer 0 Match/Capture Interrupt Pending Bit .0 Timer 0 Overflow Interrupt Pending Bit

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification WTCON — Watch Timer Control Register EEH Set 1, Bank 0 RESET Value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Addressing Mode Register addressing mode only .7 Watch Timer Clock Selection Bit

0 Main system clock divided by 27 (fxx/128)

1 Sub system clock (fxt)

.6 Watch Timer Interrupt Enable Bit

0 Disable watch timer interrupt

1 Enable watch timer interrupt

.5–.4 Buzzer Signal Selection Bits 0 0 0.5 kHz 0 1 1 kHz 1 0 2 kHz 1 1 4 kHz .3–.2 Watch Timer Speed Selection Bits 0 0 Set watch timer interrupt to 0.5s 0 1 Set watch timer interrupt to 0.25s 1 0 Set watch timer interrupt to 0.125s 1 1 Set watch timer interrupt to 3.91ms .1 Watch Timer Enable Bit

0 Disable watch timer; Clear frequency dividing circuits

1 Enable watch timer

.0 Watch Timer Interrupt Pending Bit NOTE: Watch timer clock frequency (fw) is assumed to be 32.768 kHz. 111

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

5 INTERRUPT STRUCTURE

The S3C8-series interrupt structure has three basic components: levels, vectors, and sources. The SAM8 CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors. When a specific interrupt level has more than one vector address, the vector priorities are established in hardware. A vector address can be assigned to one or more sources. Levels Interrupt levels are the main unit for interrupt priority assignment and recognition. All peripherals and I/O blocks can issue interrupt requests. In other words, peripheral and I/O operations are interrupt-driven. There are eight possible interrupt levels: IRQ0–IRQ7, also called level 0–level 7. Each interrupt level directly corresponds to an interrupt request number (IRQn). The total number of interrupt levels used in the interrupt structure varies from device to device. The S3F82NB interrupt structure recognizes eight interrupt levels. The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels. They are just identifiers for the interrupt levels that are recognized by the CPU. The relative priority of different interrupt levels is determined by settings in the interrupt priority register, IPR. Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels. Vectors Each interrupt level can have one or more interrupt vectors, or it may have no vector address assigned at all. The maximum number of vectors that can be supported for a given level is 128 (The actual number of vectors used for S3C8-series devices is always much smaller). If an interrupt level has more than one vector address, the vector priorities are set in hardware. S3F82NB uses nineteen vectors. Sources A source is any peripheral that generates an interrupt. A source can be an external pin or a counter overflow. Each vector can have several interrupt sources. In the S3F82NB interrupt structure, there are nineteen possible interrupt sources. When a service routine starts, the respective pending bit should be either cleared automatically by hardware or cleared "manually" by program software. The characteristics of the source's pending mechanism determine which method would be used to clear its respective pending bit. 112

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT TYPES The three components of the S3C8 interrupt structure described before — levels, vectors, and sources — are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic. There are three possible combinations of interrupt structure components, called interrupt types 1, 2, and 3. The types differ in the number of vectors and interrupt sources assigned to each level (see Figure 5-1): Type 1: One level (IRQn) + one vector (V 1) + one source (S1) Type 2: One level (IRQn) + one vector (V 1) + multiple sources (S1 – Sn) Type 3: One level (IRQn) + multiple vectors (V 1 – Vn) + multiple sources (S1 – Sn, Sn+1 – Sn+m) In the S3F82NB microcontroller, two interrupt types are implemented. Vectors SourcesLevels V1 S2Type 2: IRQn Sn V1 S1 V2 S2Type 3: IRQn V3 S3 V1 S1Type 1: IRQn Vn Sn + 1 Sn Sn + 2 Sn + m NOTES: 1. The number of Sn and Vn value is expandable. 2. In the S3F82NB implementation, interrupt types 1 and 3 are used. Figure 5-1. S3C8-Series Interrupt Types 113

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification S3F82NB INTERRUPT STRUCTURE The S3F82NB microcontroller supports nineteen interrupt sources. All nineteen of the interrupt sources have a corresponding interrupt vector address. Eight interrupt levels are recognized by the CPU in this device-specific interrupt structure, as shown in Figure 5-2. When multiple interrupt levels are active, the interrupt priority register (IPR) determines the order in which contending interrupts are to be serviced. If multiple interrupts occur within the same interrupt level, the interrupt with the lowest vector address is usually processed first (The relative priorities of multiple interrupts within a single level are fixed in hardware). When the CPU grants an interrupt request, interrupt processing starts. All other interrupts are disabled and the program counter value and status flags are pushed to stack. The starting address of the service routine is fetched from the appropriate vector address (plus the next 8-bit value to concatenate the full 16-bit address) and the service routine is executed. 114

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification NOTES: 1. Within a given interrupt level, the low vector address has high priority. For example, DAH has higher priority than DCH within the level IRQ0 the priorities within each level are set at the factory. 2. External interrupts are triggered by a rising or falling edge, depending on the corresponding control register setting. Vectors SourcesLevels Reset/Clear H/W100HnRESET Basic Timer Overflow S/WDAH Timer 0 Match/Capture H/W, S/WE0H Timer 1/A Overflow S/WDEH Timer 1/A Match/Capture H/W, S/WDCH Timer 0 Overflow S/WEEH P1.3 External Interrupt S/WECH P1.2 External Interrupt S/WEAH P1.1 External Interrupt S/WE8H P1.0 External Interrupt IRQ0 IRQ1 IRQ5 S/WE2HIRQ2 Timer B Match S/WE4HIRQ3 SIO Interrupt S/WE6HIRQ4 Watch Timer Overflow S/WF6H P1.7 External Interrupt S/WF4H P1.6 External Interrupt S/WF2H P1.5 External Interrupt S/WF0H P1.4 External Interrupt IRQ6 S/WFEH P5.7 External Interrupt S/WFCH P5.6 External Interrupt S/WFAH P5.5 External Interrupt S/WF8H P5.4 External Interrupt IRQ7 Figure 5-2. S3F82NB Interrupt Structure 115

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3F82NB interrupt structure are stored in the vector address area of the internal 64-Kbyte ROM, 0H–FFFFH. (see Figure 5-3). You can allocate unused locations in the vector address area as normal program memory. If you do so, please be careful not to overwrite any of the stored vector addresses (Table 5-1 lists all vector addresses). The program reset address in the ROM is 0100H. The reset address of ROM can be changed by Smart Option in the S3F82NB (full-flash device). Refer to the Chapter 18. Embedded Flash Memory Interface for more detailed contents. (Decimal) 65,535 255 (Hex) FFFFH 00H0 64K-bytes Internal Program Memory Area Available ISP Sector Area Interrupt Vector Area Smart Option 3CH 3FH FFH 8FFH Figure 5-3. ROM Vector Address Area 116

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 5-1. Interrupt Vectors Vector Address Interrupt Source Request Reset/Clear Decimal Value Hex Value Interrupt Level Priority in Level H/W S/W 256 100H Basic timer overflow Reset – /g151

218 DAH Timer 0 match/capture IRQ0 0 /g151

220 DCH Timer 0 overflow 1 /g151/g151

222 DEH Timer 1/A match/capture IRQ1 0 /g151

224 E0H Timer 1/A overflow 1 /g151/g151

226 E2H Timer B match IRQ2 – /g151

228 E4H SIO interrupt IRQ3 – /g151

230 E6H Watch timer overflow IRQ4 – /g151

232 E8H P1.0 external interrupt IRQ5 0 /g151 234 EAH P1.1 external interrupt 1 /g151 236 ECH P1.2 external interrupt 2 /g151 238 EEH P1.3 external interrupt 3 /g151 240 F0H P1.4 external interrupt IRQ6 0 /g151 242 F2H P1.5 external interrupt 1 /g151 244 F4H P1.6 external interrupt 2 /g151 246 F6H P1.7 external interrupt 3 /g151 248 F8H P5.4 external interrupt IRQ7 0 /g151 250 FAH P5.5 external interrupt 1 /g151 252 FCH P5.6 external interrupt 2 /g151 254 FEH P5.7 external interrupt 3 /g151 NOTES: 1. Interrupt priorities are identified in inverse order: "0" is the highest priority, "1" is the next highest, and so on. 2. If two or more interrupts within the same level contend, the interrupt with the lowest vector address usually has priority o ver one with a higher vector address. The priorities within a given level are fixed in hardware. 117

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI) Executing the Enable Interrupts (EI) instruction globally enables the interrupt structure. All interrupts are then serviced as they occur according to the established priorities. NOTE The system initialization routine executed after a reset must always contain an EI instruction to globally enable the interrupt structure. During the normal operation, you can execute the DI (Disable Interrupt) instruction at any time to globally disable interrupt processing. The EI and DI instructions change the value of bit 0 in the SYM register. SYSTEM-LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources, four system-level registers control interrupt processing: — The interrupt mask register, IMR, enables (un-masks) or disables (masks) interrupt levels. — The interrupt priority register, IPR, controls the relative priorities of interrupt levels. — The interrupt request register, IRQ, contains interrupt pending flags for each interrupt level (as opposed to each interrupt source). — The system mode register, SYM, enables or disables global interrupt processing (SYM settings also enable fast interrupts and control the activity of external interface, if implemented). Table 5-2. Interrupt Control Register Overview Control Register ID R/W Function Description Interrupt mask register IMR R/W Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels: IRQ0–IRQ7. Interrupt priority register IPR R/W Controls the relative processing priorities of the interrupt levels. The seven levels of S3F82NB are organized into three groups: A, B, and C. Group A is IRQ0 and IRQ1, group B is IRQ2, IRQ3 and IRQ4, and group C is IRQ5, IRQ6, and IRQ7. Interrupt request register IRQ R This register contains a request pending bit for each interrupt level. System mode register SYM R/W This register enables/disables fast interrupt processing, dynamic global interrupt processing, and external interface control (An external memory interface is implemented in the S3F82NB microcontroller). NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended. 118

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways: globally or by specific interrupt level and source. The system-level control points in the interrupt structure are: — Global interrupt enable and disable (by EI and DI instructions or by direct manipulation of SYM.0) — Interrupt level enable/disable settings (IMR register) — Interrupt level priority settings (IPR register) — Interrupt source enable/disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing, be sure to include the necessary register file address (register pointer) information. Interrupt Request Register (Read-only) IRQ0-IRQ7, Interrupts Interrupt Mask Register Polling Cycle Interrupt Priority Register Global Interrupt Control (EI, DI or SYM.0 manipulation) S R Q RESET EI Vector Interrupt Cycle Figure 5-4. Interrupt Function Diagram 119

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral (see Table 5-3). Table 5-3. Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register(s) Location(s) in Set 1 Timer 0 match/capture Timer 0 overflow IRQ0 T0CON T0CNT T0DATA E5H, bank 0 E3H, bank 0 E4H, bank 0 Timer 1/A match/capture Timer 1/A overflow IRQ1 TACON TACNT TADATA EBH, bank 0 E7H, bank 0 E9H, bank 0 Timer B match IRQ2 TBCON TBCNT TBDATA EAH, bank 0 E6H, bank 0 E8H, bank 0 SIO interrupt IRQ3 SIOCON SIODATA SIOPS F3H, bank 0 F4H, bank 0 F5H, bank 0 Watch timer overflow IRQ4 WTCON EEH, bank 0 P1.0 external interrupt P1.1 external interrupt P1.2 external interrupt P1.3 external interrupt IRQ5 P1CONlL P1INTL P1PND E5H, bank 1 E9H, bank 1 E7H, bank 1 P1.4 external interrupt P1.5 external interrupt P1.6 external interrupt P1.7 external interrupt IRQ6 P1CONH P1INTH P1PND E4H, bank 1 E8H, bank 1 E7H, bank 1 P5.4 external interrupt P5.5 external interrupt P5.6 external interrupt P5.7 external interrupt IRQ7 P5CONH P5INT P5PND FEH, bank 1 FBH, bank 1 FCH, bank 1 NOTE: If a interrupt is un-mask (Enable interrupt level) in the IMR register, the pending bit and enable bit of the interrupt should be written after a DI instruction is executed. 120

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SYSTEM MODE REGISTER (SYM) The system mode register, SYM (set 1, DEH), is used to globally enable and disable interrupt processing and to control fast interrupt processing (see Figure 5-5). undetermined. The instructions EI and DI enable and disable global interrupt processing, respectively, by modifying the bit 0 value of the SYM register. In order to enable interrupt processing an Enable Interrupt (EI) instruction must be included in the initialization routine, which follows a reset operation. Although you can manipulate SYM.0 directly to enable and disable interrupts during the normal operation, it is recommended to use the EI and DI instructions for this purpose. System Mode Register (SYM) DEH, Set 1, R/W Global interrupt enable bit: (3) 0 = Disable all interrupts processing 1 = Enable all interrupts processing Fast interrupt enable bit: (2) 0 = Disable fast interrupts processing 1 = Enable fast interrupts processing Fast interrupt level selection bits: (1) 0 0 0 = IRQ0 0 0 1 = IRQ1 0 1 0 = IRQ2 0 1 1 = IRQ3 1 0 0 = IRQ4 1 0 1 = IRQ5 1 1 0 = IRQ6 1 1 1 = IRQ7 Not used for the S3F82NB NOTES: 1. You can select only one interrupt level at a time for fast interrupt processing. 2. Setting SYM.1 to "1" enables fast interrupt processing for the interrupt processing for the interrupt level currently selected by SYM.2-SYM.4. 3. Following a reset, you must enable global interrupt processing by executing EI instruction (not by writing a "1" to SYM.0) Always logic "0" Figure 5-5. System Mode Register (SYM) 121

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT MASK REGISTER (IMR) The interrupt mask register, IMR (set 1, DDH) is used to enable or disable interrupt processing for individual interrupt levels. After a reset, all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine. Each IMR bit corresponds to a specific interrupt level: bit 1 to IRQ1, bit 2 to IRQ2, and so on. When the IMR bit of an interrupt level is cleared to "0", interrupt processing for that level is disabled (masked). When you set a level's IMR bit to "1", interrupt processing for the level is enabled (not masked). The IMR register is mapped to register location DDH in set 1. Bit values can be read and written by instructions using the Register addressing mode. Interrupt Mask Register (IMR) DDH, Set 1, R/W IRQ1IRQ2 IRQ4IRQ5IRQ6IRQ7 IRQ0 IRQ3 NOTE: Before IMR register is changed to any value, all interrupts must be disable. Using DI instruction is recommended. Interrupt level enable : 0 = Disable (mask) interrupt level 1 = Enable (un-mask) interrupt levelFigure 5-6. Interrupt Mask Register (IMR) 122

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT PRIORITY REGISTER (IPR) The interrupt priority register, IPR (set 1, bank 0, FFH), is used to set the relative priorities of the interrupt levels in the microcontroller’s interrupt structure. After a reset, all IPR bit values are undetermined and must therefore be written to their required settings by the initialization routine. When more than one interrupt sources are active, the source with the highest priority level is serviced first. If two sources belong to the same interrupt level, the source with the lower vector address usually has the priority (This priority is fixed in hardware). To support programming of the relative interrupt level priorities, they are organized into groups and subgroups by the interrupt logic. Please note that these groups (and subgroups) are used only by IPR logic for the IPR register priority definitions (see Figure 5-7): Group A IRQ0, IRQ1 Group B IRQ2, IRQ3, IRQ4 Group C IRQ5, IRQ6, IRQ7 IPR Group B IPR Group C IRQ2 IRQ4 IRQ3 B22B21 IRQ5 IRQ7 IRQ6 C22C21 IPR Group A IRQ1 IRQ0 Figure 5-7. Interrupt Request Priority Groups As you can see in Figure 5-8, IPR.7, IPR.4, and IPR.1 control the relative priority of interrupt groups A, B, and C. For example, the setting "001B" for these bits would select the group relationship B > C > A. The setting "101B" would select the relationship C > B > A. The functions of the other IPR bit settings are as follows: — IPR.5 controls the relative priorities of group C interrupts. — Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5, — IPR.0 controls the relative priority setting of IRQ0 and IRQ1 interrupts. 123

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Interrupt Priority Register (IPR) FFH, Set 1, Bank 0, R/W Group A: 0 = IRQ0 > IRQ1 1 = IRQ1 > IRQ0 Subgroup B: 0 = IRQ3 > IRQ4 1 = IRQ4 > IRQ3 Group C: 0 = IRQ5 > (IRQ6, IRQ7) 1 = (IRQ6, IRQ7) > IRQ5 Subgroup C: 0 = IRQ6 > IRQ7 1 = IRQ7 > IRQ6 Group B: 0 = IRQ2 > (IRQ3, IRQ4) 1 = (IRQ3, IRQ4) > IRQ2 Group priority: 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 = Undefined = B > C > A = A > B > C = B > A > C = C > A > B = C > B > A = A > C > B = Undefined D7 D4 D1 Figure 5-8. Interrupt Priority Register (IPR) 124

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT REQUEST REGISTER (IRQ) You can poll bit values in the interrupt request register, IRQ (set 1, DCH), to monitor interrupt request status for all levels in the microcontroller’s interrupt structure. Each bit corresponds to the interrupt level of the same number: bit 0 to IRQ0, bit 1 to IRQ1, and so on. A "0" indicates that no interrupt request is currently being issued for that level. A "1" indicates that an interrupt request has been generated for that level. IRQ bit values are read-only addressable using Register addressing mode. You can read (test) the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of specific interrupt levels. After a reset, all IRQ status bits are cleared to “0”. You can poll IRQ register values even if a DI instruction has been executed (that is, if global interrupt processing is disabled). If an interrupt occurs while the interrupt structure is disabled, the CPU will not service it. You can, however, still detect the interrupt request by polling the IRQ register. In this way, you can determine which events occurred while the interrupt structure was globally disabled. Interrupt Request Register (IRQ) DCH, Set 1, Read-only IRQ1IRQ2IRQ3IRQ4IRQ5IRQ6IRQ7 IRQ0 Interrupt level request pending bits: 0 = Interrupt level is not pending 1 = Interrupt level is pending Figure 5-9. Interrupt Request Register (IRQ) 125

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits: one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared in the interrupt service routine. Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware, interrupt logic sets the corresponding pending bit to "1" when a request occurs. It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced. The CPU acknowledges the interrupt source by sending an IACK, executes the service routine, and clears the pending bit to "0". This type of pending bit is not mapped and cannot, therefore, be read or written by application software. In the S3F82NB interrupt structure, the timer 0 match/capture and overflow interrupt (IRQ0), the timer 1/A match/capture and overflow interrupt (IRQ1), the timer B match interrupt (IRQ2), the SIO interrupt (IRQ3) belongs to this category of interrupts in which pending condition is cleared automatically by hardware. Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software. The service routine must clear the appropriate pending bit before a return-from-interrupt subroutine (IRET) occurs. To do this, a "0" must be written to the corresponding pending bit location in the source’s mode or control register. /g41/g3Programming Tip — How to clear an interrupt pending bit As the following examples are shown, a load instruction should be used to clear an interrupt pending bit. Examples: 1. SB1 LD P1PND, #11111011B ; Clear P1.2's interrupt pending bit /g120 /g120 /g120 IRET 2. SB0 LD TINTPND, #11111101B ; Clear timer 0 match/capture interrupt pending bit /g120 /g120 /g120 IRET 126

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows: 1. A source generates an interrupt request by setting the interrupt request bit to "1". 2. The CPU polling procedure identifies a pending condition for that source. 3. The CPU checks the sources interrupt level. 4. The CPU generates an interrupt acknowledge signal. 5. Interrupt logic determines the interrupt's vector address. 6. The service routine starts and the source's pending bit is cleared to "0" (by hardware or by software). 7. The CPU continues polling for interrupt requests. INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced, the following conditions must be met: — Interrupt processing must be globally enabled (EI, SYM.0 = "1") — The interrupt level must be enabled (IMR register) — The interrupt level must have the highest priority if more than one levels are currently requesting service — The interrupt must be enabled at the interrupt's source (peripheral control register) When all the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence: 1. Reset (clear to "0") the interrupt enable bit in the SYM register (SYM.0) to disable all subsequent interrupts. 2. Save the program counter (PC) and status flags to the system stack. 3. Branch to the interrupt vector to fetch the address of the service routine. 4. Pass control to the interrupt service routine. When the interrupt service routine is completed, the CPU issues an Interrupt Return (IRET). The IRET restores the PC and status flags, setting SYM.0 to "1". It allows the CPU to process the next interrupt request. 127

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM (00H–FFH) contains the addresses of interrupt service routines that correspond to each level in the interrupt structure. Vectored interrupt processing follows this sequence: 1. Push the program counter's low-byte value to the stack. 2. Push the program counter's high-byte value to the stack. 3. Push the FLAG register values to the stack. 4. Fetch the service routine's high-byte address from the vector location. 5. Fetch the service routine's low-byte address from the vector location. 6. Branch to the service routine specified by the concatenated 16-bit vector address. NOTE A 16-bit vector address always begins at an even-numbered ROM address within the range of 00H–FFH. NESTING OF VECTORED INTERRUPTS It is possible to nest a higher-priority interrupt request while a lower-priority request is being serviced. To do this, you must follow these steps: 1. Push the current 8-bit interrupt mask register (IMR) value to the stack (PUSH IMR). 2. Load the IMR register with a new mask value that enables only the higher priority interrupt. 3. Execute an EI instruction to enable interrupt processing (a higher priority interrupt will be processed if it occurs). 4. When the lower-priority interrupt service routine ends, restore the IMR to its original value by returning the previous mask value from the stack (POP IMR). 5. Execute an IRET. Depending on the application, you may be able to simplify the procedure above to some extent. INSTRUCTION POINTER (IP) The instruction pointer (IP) is adopted by all the S3C8-series microcontrollers to control the optional high-speed interrupt processing feature called fast interrupts. The IP consists of register pair DAH and DBH. The names of IP registers are IPH (high byte, IP15–IP8) and IPL (low byte, IP7–IP0). FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles. To select a specific interrupt level for fast interrupt processing, you write the appropriate 3-bit value to SYM.4–SYM.2. Then, to enable fast interrupt processing for the selected level, you set SYM.1 to “1”. 128

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FAST INTERRUPT PROCESSING (Continued) Two other system registers support fast interrupt processing: — The instruction pointer (IP) contains the starting address of the service routine (and is later used to swap the program counter values), and — When a fast interrupt occurs, the contents of the FLAGS register is stored in an unmapped, dedicated register called FLAGS' (“FLAGS prime”). NOTE For the S3F82NB microcontroller, the service routine for any one of the eight interrupts levels: IRQ0– IRQ7 can be selected for fast interrupt processing. Procedure for Initiating Fast Interrupts To initiate fast interrupt processing, follow these steps: 1. Load the start address of the service routine into the instruction pointer (IP). 2. Load the interrupt level number (IRQn) into the fast interrupt selection field (SYM.4–SYM.2) 3. Write a "1" to the fast interrupt enable bit in the SYM register. Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processing, the following events occur: 1. The contents of the instruction pointer and the PC are swapped. 2. The FLAG register values are written to the FLAGS' (“FLAGS prime”) register. 3. The fast interrupt status bit in the FLAGS register is set. 4. The interrupt is serviced. 5. Assuming that the fast interrupt status bit is set, when the fast interrupt service routine ends, the instruction pointer and PC values are swapped back. 6. The content of FLAGS' (“FLAGS prime”) is copied automatically back to the FLAGS register. 7. The fast interrupt status bit in FLAGS is cleared automatically. Relationship to Interrupt Pending Bit Types As described previously, there are two types of interrupt pending bits: One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed; the other that must be cleared by the application program's interrupt service routine. You can select fast interrupt processing for interrupts with either type of pending condition clear function — by hardware or by software. Programming Guidelines Remember that the only way to enable/disable a fast interrupt is to set/clear the fast interrupt enable bit in the SYM register, SYM.1. Executing an EI or DI instruction globally enables or disables all interrupt processing, including fast interrupts. If you use fast interrupts, remember to load the IP with a new start address when the fast interrupt service routine ends. 129

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

6 INSTRUCTION SET

The SAM8 instruction set is specifically designed to support the large register files that are typical of most SAM8 microcontrollers. There are 78 instructions. The powerful data manipulation capabilities and features of the instruction set include: — A full complement of 8-bit arithmetic and logic operations, including multiply and divide — No special I/O instructions (I/O control/data registers are mapped directly into the register file) — Decimal adjustment included in binary-coded decimal (BCD) operations — 16-bit (word) data can be incremented and decremented — Flexible instructions for bit addressing, rotate, and shift operations DATA TYPES The SAM8 CPU performs operations on bits, bytes, BCD digits, and two-byte words. Bits in the register file can be set, cleared, complemented, and tested. Bits within a byte are numbered from 7 to 0, where bit 0 is the least significant (right-most) bit. REGISTER ADDRESSING To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit data or 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces." ADDRESSING MODES There are seven explicit addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), Immediate (IM), and Indirect (IA). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes." 130

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-1. Instruction Group Summary Mnemonic Operands Instruction Load Instructions CLR dst Clear LD dst,src Load LDB dst,src Load bit LDE dst,src Load external data memory LDC dst,src Load program memory LDED dst,src Load external data memory and decrement LDCD dst,src Load program memory and decrement LDEI dst,src Load external data memory and increment LDCI dst,src Load program memory and increment LDEPD dst,src Load external data memory with pre-decrement LDCPD dst,src Load program memory with pre-decrement LDEPI dst,src Load external data memory with pre-increment LDCPI dst,src Load program memory with pre-increment LDW dst,src Load word POP dst Pop from stack POPUD dst,src Pop user stack (decrementing) POPUI dst,src Pop user stack (incrementing) PUSH src Push to stack PUSHUD dst,src Push user stack (decrementing) PUSHUI dst,src Push user stack (incrementing) 131

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Arithmetic Instructions ADC dst,src Add with carry ADD dst,src Add CP dst,src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst,src Divide INC dst Increment INCW dst Increment word MULT dst,src Multiply SBC dst,src Subtract with carry SUB dst,src Subtract Logic Instructions AND dst,src Logical AND COM dst Complement OR dst,src Logical OR XOR dst,src Logical exclusive OR 132

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-1. Instruction Group Summary (Continued) Mnemonic Operands Instruction Program Control Instructions BTJRF dst,src Bit test and jump relative on false BTJRT dst,src Bit test and jump relative on true CALL dst Call procedure CPIJE dst,src Compare, increment and jump on equal CPIJNE dst,src Compare, increment and jump on non-equal DJNZ r,dst Decrement register and jump on non-zero ENTER Enter EXIT Exit IRET Interrupt return JP cc,dst Jump on condition code JP dst Jump unconditional JR cc,dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst,src Bit AND BCP dst,src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst,src Bit OR BXOR dst,src Bit XOR TCM dst,src Test complement under mask TM dst,src Test under mask 133

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-1. Instruction Group Summary (Concluded) Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SB0 Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRP0 src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Stop mode 134

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FLAGS REGISTER (FLAGS) The flags register FLAGS contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.7–FLAGS.4, can be tested and used with conditional jump instructions; two others FLAGS.3 and FLAGS.2 are used for BCD arithmetic. The FLAGS register also contains a bit to indicate the status of fast interrupt processing (FLAGS.1) and a bank address status bit (FLAGS.0) to indicate whether bank 0 or bank 1 is currently being addressed. FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result. System Flags Register (FLAGS) D5H, Set 1, R/W Bank address status flag (BA) First interrupt status flag (FIS) Half-carry flag (H) Decimal adjust flag (D)Overflow (V) Sign flag (S) Zero flag (Z) Carry flag (C) Figure 6-1. System Flags Register (FLAGS) 135

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FLAG DESCRIPTIONS C Carry Flag (FLAGS.7) The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag. Z Zero Flag (FLAGS.6) For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero. S Sign Flag (FLAGS.5) Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number. V Overflow Flag (FLAGS.4) The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than – 128. It is also cleared to "0" following logic operations. D Decimal Adjust Flag (FLAGS.3) The DA bit is used to specify what type of instruction was executed last during BCD operations, so that a subsequent decimal adjust operation can execute correctly. The DA bit is not usually accessed by programmers, and cannot be used as a test condition. H Half-Carry Flag (FLAGS.2) The H bit is set to "1" whenever an addition generates a carry-out of bit 3, or when a subtraction borrows out of bit 4. It is used by the Decimal Adjust (DA) instruction to convert the binary result of a previous addition or subtraction into the correct decimal (BCD) result. The H flag is seldom accessed directly by a program. FIS Fast Interrupt Status Flag (FLAGS.1) The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing. When set, it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed. BA Bank Address Flag (FLAGS.0) The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected, bank 0 or bank 1. The BA flag is cleared to "0" (select bank 0) when you execute the SB0 instruction and is set to "1" (select bank 1) when you execute the SB1 instruction. 136

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INSTRUCTION SET NOTATION Table 6-2. Flag Notation Conventions Flag Description C Carry flag Z Zero flag S Sign flag V Overflow flag D Decimal-adjust flag H Half-carry flag

0 Cleared to logic zero

1 Set to logic one

• Set or cleared according to operation – Value is unaffected x Value is undefined Table 6-3. Instruction Set Symbols Symbol Description dst Destination operand src Source operand @ Indirect register address prefix PC Program counter IP Instruction pointer FLAGS Flags register (D5H) RP Register pointer # Immediate operand or register address prefix H Hexadecimal number suffix D Decimal number suffix B Binary number suffix opc Opcode 137

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-4. Instruction Notation Conventions Notation Description Actual Operand Range cc Condition code See list of condition codes in Table 6-6. r Working register only Rn (n = 0–15) rb Bit (b) of working register Rn.b (n = 0–15, b = 0–7) r0 Bit 0 (LSB) of working register Rn (n = 0–15) rr Working register pair RRp (p = 0, 2, 4, ..., 14) R Register or working register reg or Rn (reg = 0–255, n = 0–15) Rb Bit 'b' of register or working register reg.b (reg = 0–255, b = 0–7) RR Register pair or working register pair reg or RRp (reg = 0–254, even number only, where p = 0, 2, ..., 14) IA Indirect addressing mode addr (addr = 0–254, even number only) Ir Indirect working register only @Rn (n = 0–15) IR Indirect register or indirect working register @Rn or @reg (reg = 0–255, n = 0–15) Irr Indirect working register pair only @RRp (p = 0, 2, ..., 14) IRR Indirect register pair or indirect working register pair @RRp or @reg (reg = 0–254, even only, where p = 0, 2, ..., 14) X Indexed addressing mode #reg [Rn] (reg = 0–255, n = 0–15) XS Indexed (short offset) addressing mode #addr [RRp] (addr = range –128 to +127, where p = 0, 2, ..., 14) xl Indexed (long offset) addressing mode #addr [RRp] (addr = range 0–65535, where p = 0, 2, ..., 14) da Direct addressing mode addr (addr = range 0–65535) ra Relative addressing mode addr (addr = number in the range +127 to –128 that is an offset relative to the address of the next instruction) im Immediate addressing mode #data (data = 0–255) iml Immediate (long) addressing mode #data (data = range 0–65535) 138

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-5. Opcode Quick Reference OPCODE MAP LOWER NIBBLE (HEX) – 0 1 2 3 4 5 6 7 U 0 DEC DEC IR1 ADD r1,r2 ADD r1,Ir2 ADD R2,R1 ADD IR2,R1 ADD R1,IM BOR r0–Rb P 1 RLC RLC IR1 ADC r1,r2 ADC r1,Ir2 ADC R2,R1 ADC IR2,R1 ADC R1,IM BCP r1.b, R2 P 2 INC INC IR1 SUB r1,r2 SUB r1,Ir2 SUB R2,R1 SUB IR2,R1 SUB R1,IM BXOR r0–Rb E 3 JP IRR1 SRP/0/1 IM SBC r1,r2 SBC r1,Ir2 SBC R2,R1 SBC IR2,R1 SBC R1,IM BTJR r2.b, RA R 4 DA DA IR1 OR r1,r2 OR r1,Ir2 OR R2,R1 OR IR2,R1 OR R1,IM LDB r0–Rb

5 POP

r1,r2 AND r1,Ir2 AND R2,R1 AND IR2,R1 AND R1,IM BITC r1.b N 6 COM COM IR1 TCM r1,r2 TCM r1,Ir2 TCM R2,R1 TCM IR2,R1 TCM R1,IM BAND r0–Rb I 7 PUSH PUSH IR2 TM r1,r2 TM r1,Ir2 TM R2,R1 TM IR2,R1 TM R1,IM BIT r1.b B 8 DECW RR1 DECW IR1 PUSHUD IR1,R2 PUSHUI IR1,R2 MULT R2,RR1 MULT IR2,RR1 MULT IM,RR1 LD r1, x, r2 B 9 RL RL IR1 POPUD IR2,R1 POPUI IR2,R1 DIV R2,RR1 DIV IR2,RR1 DIV IM,RR1 LD r2, x, r1 L A INCW RR1 INCW IR1 CP r1,r2 CP r1,Ir2 CP R2,R1 CP IR2,R1 CP R1,IM LDC r1, Irr2, xL E B CLR CLR IR1 XOR r1,r2 XOR r1,Ir2 XOR R2,R1 XOR IR2,R1 XOR R1,IM LDC r2, Irr2, xL C RRC RRC IR1 CPIJE Ir,r2,RA LDC r1,Irr2 LDW RR2,RR1 LDW IR2,RR1 LDW RR1,IML LD r1, Ir2 H D SRA SRA IR1 CPIJNE Irr,r2,RA LDC r2,Irr1 CALL IA1 LD IR1,IM LD Ir1, r2 E E RR RR IR1 LDCD r1,Irr2 LDCI r1,Irr2 LD R2,R1 LD R2,IR1 LD R1,IM LDC r1, Irr2, xs X F SWAP SWAP IR1 LDCPD r2,Irr1 LDCPI r2,Irr1 CALL IRR1 LD IR2,R1 CALL DA1 LDC r2, Irr1, xs 139

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 6-5. Opcode Quick Reference (Continued) OPCODE MAP LOWER NIBBLE (HEX) – 8 9 A B C D E F U 0 LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC NEXT P 1 /g112/g112/g112/g112/g112/g112/g112 ENTER P 2 E XIT E 3 W FI R 4 S B 0

5 S B1

I 7 /g112/g112/g112/g112/g112/g112/g112 STOP B 8 D I B 9 E I L A R E T E B I R E T C R CF H D /g112/g112/g112/g112/g112/g112/g112 SCF E E C C F X F LD r1,R2 LD r2,R1 DJNZ r1,RA JR cc,RA LD r1,IM JP cc,DA INC NOP 140

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CONDITION CODES The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6. The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions. Table 6-6. Condition Codes Binary Mnemonic Description Flags Set

0000 F Always false –

1000 T Always true –

0111 (note) C Carry C = 1 1111 (note) NC No carry C = 0 0110 (note) Z Zero Z = 1 1110 (note) NZ Not zero Z = 0

1101 PL Plus S = 0

0101 MI Minus S = 1

0100 OV Overflow V = 1

1100 NOV No overflow V = 0

0110 (note) EQ Equal Z = 1 1110 (note) NE Not equal Z = 0

1001 GE Greater than or equal (S XOR V) = 0

0001 LT Less than (S XOR V) = 1

1010 GT Greater than (Z OR (S XOR V)) = 0

0010 LE Less than or equal (Z OR (S XOR V)) = 1

1111 (note) UGE Unsigned greater than or equal C = 0 0111 (note) ULT Unsigned less than C = 1

1011 UGT Unsigned greater than (C = 0 AND Z = 0) = 1

0011 ULE Unsigned less than or equal (C OR Z) = 1

NOTES: 1. It indicates condition codes that are related to two different mnemonics but which test the same flag. For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used. 2. For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used. 141

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAM8 instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description: — Instruction name (mnemonic) — Full instruction name — Source/destination format of the instruction operand — Shorthand notation of the instruction's operation — Textual description of the instruction's effect — Specific flag settings affected by the instruction — Detailed description of the instruction's format, execution time, and addressing mode(s) — Programming example(s) explaining how to use the instruction 142

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ADC — Add with Carry ADC dst,src Operation: dst /g109 d s t + s r c + c The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurs, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if there is a carry from the most significant bit of the low-order four bits of the result; cleared otherwise. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 12 r r 6 13 r lr opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: ADC R1,R2 /g111 R 1 = 1 4 H , R 2 = 0 3 H ADC R1,@R2 /g111 R1 = 1BH, R2 = 03H ADC 01H,02H /g111 Register 01H = 24H, register 02H = 03H ADC 01H,@02H /g111 Register 01H = 2BH, register 02H = 03H ADC 01H,#11H /g111 Register 01H = 32H In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1. 143

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ADD — Add ADD dst,src Operation: dst /g109 d s t + s r c The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed. Flags: C: Set if there is a carry from the most significant bit of the result; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if both operands are of the same sign and the result is of the opposite sign; cleared otherwise. D: Always cleared to "0". H: Set if a carry from the low-order nibble occurred. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 02 r r 6 03 r lr opc src dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: ADD R1,R2 /g111 R 1 = 1 5 H , R 2 = 0 3 H ADD R1,@R2 /g111 R1 = 1CH, R2 = 03H ADD 01H,02H /g111 Register 01H = 24H, register 02H = 03H ADD 01H,@02H /g111 Register 01H = 2BH, register 02H = 03H ADD 01H,#25H /g111 Register 01H = 46H In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1. 144

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification AND — Logical AND AND dst,src Operation: dst /g109 d s t A N D s r c The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 52 r r 6 53 r lr opc src dst 3 6 54 R R 6 55 R IR opc dst src 3 6 56 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: AND R1,R2 /g111 R 1 = 0 2 H , R 2 = 0 3 H AND R1,@R2 /g111 R1 = 02H, R2 = 03H AND 01H,02H /g111 Register 01H = 01H, register 02H = 03H AND 01H,@02H /g111 Register 01H = 00H, register 02H = 03H AND 01H,#25H /g111 Register 01H = 21H In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1. 145

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BAND — Bit AND BAND dst,src.b BAND dst.b,src Operation: dst(0) /g109 dst(0) AND src(b) or dst(b) /g109 dst(b) AND src(0) The specified bit of the source (or the destination) is logically ANDed with the zero bit (LSB) of the destination (or source). The resultant bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | b | 0 src 3 6 67 r0 Rb opc src | b | 1 dst 3 6 67 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H and register 01H = 05H: BAND R1,01H.1 /g111 R1 = 06H, register 01H = 05H BAND 01H.1,R1 /g111 Register 01H = 05H, R1 = 07H In the first example, source register 01H contains the value 05H (00000101B) and destination working register R1 contains 07H (00000111B). The statement "BAND R1,01H.1" ANDs the bit 1 value of the source register ("0") with the bit 0 value of register R1 (destination), leaving the value 06H (00000110B) in register R1. 146

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BCP — Bit Compare BCP dst,src.b Operation: dst(0) – src(b) The specified bit of the source is compared to (subtracted from) bit zero (LSB) of the destination. The zero flag is set if the bits are the same; otherwise it is cleared. The contents of both operands are unaffected by the comparison. Flags: C: Unaffected. Z: Set if the two bits are the same; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | b | 0 src 3 6 17 r0 Rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H and register 01H = 01H: BCP R1,01H.1 /g111 R1 = 07H, register 01H = 01H If destination working register R1 contains the value 07H (00000111B) and the source register 01H contains the value 01H (00000001B), the statement "BCP R1,01H.1" compares bit one of the source register (01H) and bit zero of the destination register (R1). Because the bit values are not identical, the zero flag bit (Z) is cleared in the FLAGS register (0D5H). 147

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BITC — Bit Complement BITC dst.b Operation: dst(b) /g109 NOT dst(b) This instruction complements the specified bit within the destination without affecting any other bits in the destination. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 57 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H BITC R1.1 /g111 R 1 = 0 5 H If working register R1 contains the value 07H (00000111B), the statement "BITC R1.1" complements bit one of the destination and leaves the value 05H (00000101B) in register R1. Because the result of the complement is not "0", the zero flag (Z) in the FLAGS register (0D5H) is cleared. 148

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BITR — Bit Reset BITR dst.b Operation: dst(b) /g109 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 0 2 4 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITR R1.1 /g111 R 1 = 0 5 H If the value of working register R1 is 07H (00000111B), the statement "BITR R1.1" clears bit one of the destination register R1, leaving the value 05H (00000101B). 149

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BITS — Bit Set BITS dst.b Operation: dst(b) /g109 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst | b | 1 2 4 77 rb NOTE: In the second byte of the instruction format, the destination address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BITS R1.3 /g111 R1 = 0FH If working register R1 contains the value 07H (00000111B), the statement "BITS R1.3" sets bit three of the destination register R1 to "1", leaving the value 0FH (00001111B). 150

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BOR — Bit OR BOR dst,src.b BOR dst.b,src Operation: dst(0) /g109 d s t ( 0 ) O R s r c ( b ) or dst(b) /g109 d s t ( b ) O R s r c ( 0 ) The specified bit of the source (or the destination) is logically ORed with bit zero (LSB) of the destination (or the source). The resulting bit value is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | b | 0 src 3 6 07 r0 Rb opc src | b | 1 dst 3 6 07 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit. Examples: Given: R1 = 07H and register 01H = 03H: BOR R1, 01H.1 /g111 R1 = 07H, register 01H = 03H BOR 01H.2, R1 /g111 Register 01H = 07H, R1 = 07H In the first example, destination working register R1 contains the value 07H (00000111B) and source register 01H the value 03H (00000011B). The statement "BOR R1,01H.1" logically ORs bit one of register 01H (source) with bit zero of R1 (destination). This leaves the same value (07H) in working register R1. In the second example, destination register 01H contains the value 03H (00000011B) and the source working register R1 the value 07H (00000111B). The statement "BOR 01H.2,R1" logically ORs bit two of register 01H (destination) with bit zero of R1 (source). This leaves the value 07H in register 01H. 151

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BTJRF — Bit Test, Jump Relative on False BTJRF dst,src.b Operation: If src(b) is a "0", then PC /g109 P C + d s t The specified bit within the source operand is tested. If it is a "0", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRF instruction is executed. Flags: No flags are affected. Format: (Note 1) Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src | b | 0 dst 3 10 37 RA rb NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRF SKIP,R1.3 /g111 PC jumps to SKIP location If working register R1 contains the value 07H (00000111B), the statement "BTJRF SKIP,R1.3" tests bit 3. Because it is "0", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 152

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BTJRT — Bit Test, Jump Relative on True BTJRT dst,src.b Operation: If src(b) is a "1", then PC /g109 P C + d s t The specified bit within the source operand is tested. If it is a "1", the relative address is added to the program counter and control passes to the statement whose address is now in the PC; otherwise, the instruction following the BTJRT instruction is executed. Flags: No flags are affected. Format: (Note 1) Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src | b | 1 dst 3 10 37 RA rb NOTE: In the second byte of the instruction format, the source address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Example: Given: R1 = 07H: BTJRT SKIP,R1.1 If working register R1 contains the value 07H (00000111B), the statement "BTJRT SKIP,R1.1" tests bit one in the source register (R1). Because it is a "1", the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 153

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BXOR — Bit XOR BXOR dst,src.b BXOR dst.b,src Operation: dst(0) /g109 dst(0) XOR src(b) or dst(b) /g109 dst(b) XOR src(0) The specified bit of the source (or the destination) is logically exclusive-ORed with bit zero (LSB) of the destination (or source). The result bit is stored in the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Cleared to "0". V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | b | 0 src 3 6 27 r0 Rb opc src | b | 1 dst 3 6 27 Rb r0 NOTE: In the second byte of the 3-byte instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R1 = 07H (00000111B) and register 01H = 03H (00000011B): BXOR R1,01H.1 /g111 R1 = 06H, register 01H = 03H BXOR 01H.2,R1 /g111 Register 01H = 07H, R1 = 07H In the first example, destination working register R1 has the value 07H (00000111B) and source register 01H has the value 03H (00000011B). The statement "BXOR R1,01H.1" exclusive-ORs bit one of register 01H (source) with bit zero of R1 (destination). The result bit value is stored in bit zero of R1, changing its value from 07H to 06H. The value of source register 01H is unaffected. 154

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CALL — Call Procedure CALL dst Operation: SP /g109 SP – 1 @SP /g109 PCL SP /g109 SP –1 @SP /g109 PCH PC /g109 dst The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 IA Examples: Given: R0 = 35H, R1 = 21H, PC = 1A47H, and SP = 0002H: CALL 3521H /g111 SP = 0000H (Memory locations 0000H = 1AH, 0001H = 4AH, where 4AH is the address that follows the instruction.) CALL @RR0 /g111 SP = 0000H (0000H = 1AH, 0001H = 49H) CALL #40H /g111 SP = 0000H (0000H = 1AH, 0001H = 49H) In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0002H, the statement "CALL 3521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 0000H. The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 0001H (because the two-byte instruction format was used). The PC is then loaded with the value 3521H, the address of the first instruction in the program sequence to be executed. Assuming that the contents of the program counter and stack pointer are the same as in the first example, if program address 0040H contains 35H and program address 0041H contains 21H, the statement "CALL #40H" produces the same result as in the second example 155

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CCF — Complement Carry Flag CCF Operation: C /g109 NOT C The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one. Flags: C: Complemented. No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 EF Example: Given: The carry flag = "0": CCF If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one. 156

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CLR — Clear CLR dst Operation: dst /g109 "0" The destination location is cleared to "0". Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 B0 R

4 B 1 I R

Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH: CLR 00H /g111 Register 00H = 00H CLR @01H /g111 Register 01H = 02H, register 02H = 00H In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H. 157

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COM — Complement COM dst Operation: dst /g109 N O T d s t The contents of the destination location are complemented (one's complement); all "1s" are changed to "0s", and vice-versa. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 60 R 4 61 IR Examples: Given: R1 = 07H and register 07H = 0F1H: COM R1 /g111 R1 = 0F8H COM @R1 /g111 R1 = 07H, register 07H = 0EH In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B). In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B). 158

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CP — Compare CP dst,src Operation: dst – src The source operand is compared to (subtracted from) the destination operand, and the appropriate flags are set accordingly. The contents of both operands are unaffected by the comparison. Flags: C: Set if a "borrow" occurred (src > dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 A2 r r

6 A 3 r l r

6 A 5 R I R

Examples: 1. Given: R1 = 02H and R2 = 03H: C P R 1 , R 2 /g111 Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1". 2. Given: R1 = 05H and R2 = 0AH: CP R1,R2 JP UGE,SKIP INC R1 SKIP LD R3,R1 In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3. 159

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CPIJE — Compare, Increment, and Jump on Equal CPIJE dst,src,RA Operation: If dst – src = "0", PC /g109 P C + R A Ir /g109 I r + 1 The source operand is compared to (subtracted from) the destination operand. If the result is "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter. Otherwise, the instruction immediately following the CPIJE instruction is executed. In either case, the source pointer is incremented by one before the next instruction is executed. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst RA 3 12 C2 r Ir NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 02H: CPIJE R1,@R2,SKIP /g111 R2 = 04H, PC jumps to SKIP location In this example, working register R1 contains the value 02H, working register R2 the value 03H, and register 03 contains 02H. The statement "CPIJE R1,@R2,SKIP" compares the @R2 value 02H (00000010B) to 02H (00000010B). Because the result of the comparison is equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source register (R2) is incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 160

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CPIJNE — Compare, Increment, and Jump on Non-Equal CPIJNE dst,src,RA Operation: If dst – src "0", PC /g109 P C + R A Ir /g109 I r + 1 The source operand is compared to (subtracted from) the destination operand. If the result is not "0", the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise the instruction following the CPIJNE instruction is executed. In either case the source pointer is incremented by one before the next instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst RA 3 12 D2 r Ir NOTE: Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken. Example: Given: R1 = 02H, R2 = 03H, and register 03H = 04H: CPIJNE R1,@R2,SKIP /g111 R2 = 04H, PC jumps to SKIP location Working register R1 contains the value 02H, working register R2 (the source pointer) the value 03H, and general register 03 the value 04H. The statement "CPIJNE R1,@R2,SKIP" subtracts 04H (00000100B) from 02H (00000010B). Because the result of the comparison is non-equal, the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP. The source pointer register (R2) is also incremented by one, leaving a value of 04H. (Remember that the memory location must be within the allowed range of + 127 to – 128.) 161

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DA — Decimal Adjust DA dst Operation: dst /g109 D A d s t The destination operand is adjusted to form two 4-bit BCD digits following an addition or subtraction operation. For addition (ADD, ADC) or subtraction (SUB, SBC), the following table indicates the operation performed. (The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits): Instruction Carry Before DA Bits 4–7 Value (Hex) H Flag Before DA Bits 0–3 Value (Hex) Number Added to Byte Carry After DA 0 0–9 0 0–9 00 0 0 0–8 0 A–F 06 0 0 0–9 1 0–3 06 0 ADD 0 A–F 0 0–9 60 1 ADC 0 9–F 0 A–F 66 1

0 A–F 1 0–3 66 1

1 0–2 0 0–9 60 1 1 0–2 0 A–F 66 1 1 0–3 1 0–3 66 1 0 0–9 0 0–9 00 = – 00 0 SUB 0 0–8 1 6–F FA = – 06 0 SBC 1 7–F 0 0–9 A0 = – 60 1 1 6–F 1 6–F 9A = – 66 1 Flags: C: Set if there was a carry from the most significant bit; cleared otherwise (see table). Z: Set if result is "0"; cleared otherwise. S: Set if result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 40 R 4 41 IR 162

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DA — Decimal Adjust DA (Continued) Example: Given: Working register R0 contains the value 15 (BCD), working register R1 contains 27 (BCD), and address 27H contains 46 (BCD): ADD R1,R0 ; C /g109 "0", H /g109 "0", Bits 4–7 = 3, bits 0–3 = C, R1 /g109 3CH DA R1 ; R1 /g109 3CH + 06 If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, when the binary representations are added in the destination location using standard binary arithmetic: 0 0 0 1 0 1 0 1 15 + 0 0 1 0 0 1 1 1 0 0 1 1 1 1 0 0 = 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained: 0 0 1 1 1 1 0 0 + 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 = 42 Assuming the same values given above, the statements SUB 27H,R0 ; C /g109 "0", H /g109 "0", Bits 4–7 = 3, bits 0–3 = 1 DA @R1 ; @R1 /g109 31–0 leave the value 31 (BCD) in address 27H (@R1). 163

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DEC — Decrement DEC dst Operation: dst /g109 dst – 1 The contents of the destination operand are decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 00 R 4 01 IR Examples: Given: R1 = 03H and register 03H = 10H: DEC R1 /g111 R 1 = 0 2 H DEC @R1 /g111 Register 03H = 0FH In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH. 164

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DECW — Decrement Word DECW dst Operation: dst /g109 dst – 1 The contents of the destination location (which must be an even address) and the operand following that location are treated as a single 16-bit value that is decremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 80 RR 8 81 IR Examples: Given: R0 = 12H, R1 = 34H, R2 = 30H, register 30H = 0FH, and register 31H = 21H: DECW RR0 /g111 R 0 = 1 2 H , R 1 = 3 3 H DECW @R2 /g111 Register 30H = 0FH, register 31H = 20H In the first example, destination register R0 contains the value 12H and register R1 the value 34H. The statement "DECW RR0" addresses R0 and the following operand R1 as a 16-bit word and decrements the value of R1 by one, leaving the value 33H. NOTE: A system malfunction may occur if you use a Zero flag (FLAGS.6) result together with a DECW instruction. To avoid this problem, we recommend that you use DECW as shown in the following example: LOOP: DECW RR0 LD R2,R1 O R R 2 , R 0 JR NZ,LOOP 165

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DI — Disable Interrupts DI Operation: SYM (0) /g109 0 Bit zero of the system mode control register, SYM.0, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 8F Example: Given: SYM = 01H: DI If the value of the SYM register is 01H, the statement "DI" leaves the new value 00H in the register and clears SYM.0 to "0", disabling interrupt processing. Before changing IMR, interrupt pending and interrupt source control register, be sure DI state. 166

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DIV — Divide (Unsigned) DIV dst,src Operation: dst ÷ src dst (UPPER) /g109 REMAINDER dst (LOWER) /g109 QUOTIENT The destination operand (16 bits) is divided by the source operand (8 bits). The quotient (8 bits) is stored in the lower half of the destination. The remainder (8 bits) is stored in the upper half of the destination. When the quotient is /g116 2 8, the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect. Both operands are treated as unsigned integers. Flags: C: Set if the V flag is set and quotient is between 28 and 29 –1; cleared otherwise. Z: Set if divisor or quotient = "0"; cleared otherwise. S: Set if MSB of quotient = "1"; cleared otherwise. V: Set if quotient is /g116 2 8 or if divisor = "0"; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst 3 26/10 94 RR R 26/10 95 RR IR 26/10 96 RR IM NOTE: Execution takes 10 cycles if the divide-by-zero is attempted; otherwise it takes 26 cycles. Examples: Given: R0 = 10H, R1 = 03H, R2 = 40H, register 40H = 80H: DIV RR0,R2 /g111 R 0 = 0 3 H , R 1 = 4 0 H DIV RR0,@R2 /g111 R 0 = 0 3 H , R 1 = 2 0 H DIV RR0,#20H /g111 R 0 = 0 3 H , R 1 = 8 0 H In the first example, destination working register pair RR0 contains the values 10H (R0) and 03H (R1), and register R2 contains the value 40H. The statement "DIV RR0,R2" divides the 16-bit RR0 value by the 8-bit value of the R2 (source) register. After the DIV instruction, R0 contains the value 03H and R1 contains 40H. The 8-bit remainder is stored in the upper half of the destination register RR0 (R0) and the quotient in the lower half (R1). 167

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification DJNZ — Decrement and Jump if Non-Zero DJNZ r,dst Operation: r /g109 r – 1 If r /g122 0, PC /g109 P C + d s t The working register being used as a counter is decremented. If the contents of the register are not logic zero after decrementing, the relative address is added to the program counter and control passes to the statement whose address is now in the PC. The range of the relative address is +127 to –128, and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement. N O T E : In case of using DJNZ instruction, the working register being used as a counter should be set at the one of location 0C0H to 0CFH with SRP, SRP0, or SRP1 instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst r | opc dst 2 8 (jump taken) rA RA 8 (no jump) r = 0 to F Example: Given: R1 = 02H and LOOP is the label of a relative address: S R P # 0 C 0 H DJNZ R1,LOOP DJNZ is typically used to control a "loop" of instructions. In many cases, a label is used as the destination operand instead of a numeric relative address value. In the example, working register R1 contains the value 02H, and LOOP is the label for a relative address. The statement "DJNZ R1, LOOP" decrements register R1 by one, leaving the value 01H. Because the contents of R1 after the decrement are non-zero, the jump is taken to the relative address specified by the LOOP label. 168

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification EI — Enable Interrupts EI Operation: SYM (0) /g109 1 An EI instruction sets bit zero of the system mode register, SYM.0 to "1". This allows interrupts to be serviced as they occur (assuming they have highest priority). If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 9F Example: Given: SYM = 00H: EI If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 01H, enabling all interrupts. (SYM.0 is the enable bit for global interrupt processing.) 169

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ENTER — Enter ENTER Operation: SP /g109 SP – 2 @SP /g109 IP IP /g109 PC PC /g109 @IP IP /g109 IP + 2 This instruction is useful when implementing threaded-code languages. The contents of the instruction pointer are pushed to the stack. The program counter (PC) value is then written to the instruction pointer. The program memory word that is pointed to by the instruction pointer is loaded into the PC, and the instruction pointer is incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 14 1F Example: The diagram below shows one example of how to use an ENTER statement. 0050IP 0022SP

22 Data

110 Routine

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification EXIT — Exit EXIT Operation: IP /g109 @SP SP /g109 SP + 2 PC /g109 @IP IP /g109 I P + 2 This instruction is useful when implementing threaded-code languages. The stack value is popped and loaded into the instruction pointer. The program memory word that is pointed to by the instruction pointer is then loaded into the program counter, and the instruction pointer is incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 14 (internal stack) 2F 16 (internal stack) Example: The diagram below shows one example of how to use an EXIT statement. 0050IP 0022SP Address Data 0040PC Address Data Memory 0052IP 0022SP Address Data 0060PC Address Data Memory Stack Stack Before After

60 Main

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IDLE — Idle Operation IDLE Operation: The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue. Idle mode can be released by an interrupt request (IRQ) or an external reset operation. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc 1 4 6F – – Example: The instruction IDLE stops the CPU clock but not the system clock. 172

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INC — Increment INC dst Operation: dst /g109 d s t + 1 The contents of the destination operand are incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst dst | opc 1 4 rE r r = 0 to F opc dst 2 4 20 R 4 21 IR Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH: INC R0 /g111 R0 = 1CH INC 00H /g111 Register 00H = 0DH INC @R0 /g111 R0 = 1BH, register 01H = 10H In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register. The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH. In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H. 173

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification INCW — Increment Word INCW dst Operation: dst /g109 d s t + 1 The contents of the destination (which must be an even address) and the byte following that location are treated as a single 16-bit value that is incremented by one. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 A0 RR

8 A 1 I R

Examples: Given: R0 = 1AH, R1 = 02H, register 02H = 0FH, and register 03H = 0FFH: INCW RR0 /g111 R0 = 1AH, R1 = 03H INCW @R1 /g111 Register 02H = 10H, register 03H = 00H In the first example, the working register pair RR0 contains the value 1AH in register R0 and 02H in register R1. The statement "INCW RR0" increments the 16-bit destination by one, leaving the value 03H in register R1. In the second example, the statement "INCW @R1" uses Indirect Register (IR) addressing mode to increment the contents of general register 03H from 0FFH to 00H and register 02H from 0FH to 10H. NOTE: A system malfunction may occur if you use a Zero (Z) flag (FLAGS.6) result together with an INCW instruction. To avoid this problem, we recommend that you use INCW as shown in the following example: LOOP: INCW RR0 LD R2,R1 OR R2,R0 JR NZ,LOOP 174

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IRET — Interrupt Return IRET IRET (Normal) IRET (Fast) Operation: FLAGS /g109 @SP PC /g108 I P SP /g109 SP + 1 FLAGS /g109 FLAGS' PC /g109 @SP FIS /g109 0 SP /g109 S P + 2 SYM(0) /g109 1 This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts. A "normal IRET" is executed only if the fast interrupt status bit (FIS, bit one of the FLAGS register, 0D5H) is cleared (= "0"). If a fast interrupt occurred, IRET clears the FIS bit that was set at the beginning of the service routine. Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred). Format: IRET (Normal) Bytes Cycles Opcode (Hex) opc 1 10 (internal stack) BF 12 (internal stack) IRET (Fast) Bytes Cycles Opcode (Hex) opc 1 6 BF Example: In the figure below, the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled. When an interrupt occurs, the program counter and instruction pointer are swapped. This causes the PC to jump to address 100H and the IP to keep the return address. The last instruction in the service routine normally is a jump to IRET at address FFH. This causes the instruction pointer to be loaded with 100H "again" and the program counter to jump back to the main program. Now, the next interrupt can occur and the IP is still correct at 100H. IRET Interrupt Service Routine JP to FFH FFH 100H FFFFH NOTE: In the fast interrupt example above, if the last instruction is not a jump to IRET, you must pay attention to the order of the last two instructions. The IRET cannot be immediately proceeded by a clearing of the interrupt status (as with a reset of the IPR register). 175

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification JP — Jump JP cc,dst (Conditional) JP dst (Unconditional) Operation: If cc is true, PC /g109 d s t The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code (cc) is true; otherwise, the instruction following the JP instruction is executed. The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair. Control then passes to the statement addressed by the PC. Flags: No flags are affected. Format: (1) (2) Bytes Cycles Opcode (Hex) Addr Mode dst cc | opc dst 3 8 ccD DA cc = 0 to F opc dst 2 8 30 IRR NOTES: 1. The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump. 2. In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits. Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H: J P C , L A B E L _ W /g111 LABEL_W = 1000H, PC = 1000H J P @ 0 0 H /g111 PC = 0120H The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction. The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H. 176

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification JR — Jump Relative JR cc,dst Operation: If cc is true, PC /g109 P C + d s t If the condition specified by the condition code (cc) is true, the relative address is added to the program counter and control passes to the statement whose address is now in the program counter; otherwise, the instruction following the JR instruction is executed. (See list of condition codes). The range of the relative address is +127, –128, and the original value of the program counter is taken to be the address of the first instruction byte following the JR statement. Flags: No flags are affected. Format: (1) Bytes Cycles Opcode (Hex) Addr Mode dst cc | opc dst 2 6 ccB RA cc = 0 to F NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits. Example: Given: The carry flag = "1" and LABEL_X = 1FF7H: JR C,LABEL_X /g111 P C = 1 F F 7 H If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed. 177

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LD — Load LD dst,src Operation: dst /g109 src The contents of the source are loaded into the destination. The source's contents are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c dst | opc src 2 4 rC r IM 4 r8 r R src | opc dst 2 4 r9 R r r = 0 to F opc dst | src 2 4 C7 r lr

4 D 7 I r r

6 E 5 R I R

6 D6 IR IM

opc dst | src x 3 6 87 r x [r] opc src | dst x 3 6 97 x [r] r 178

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LD — Load LD (Continued) Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH: LD R0,#10H /g111 R0 = 10H LD R0,01H /g111 R0 = 20H, register 01H = 20H LD 01H,R0 /g111 Register 01H = 01H, R0 = 01H LD R1,@R0 /g111 R1 = 20H, R0 = 01H LD @R0,R1 /g111 R0 = 01H, R1 = 0AH, register 01H = 0AH LD 00H,01H /g111 Register 00H = 20H, register 01H = 20H LD 02H,@00H /g111 Register 02H = 20H, register 00H = 01H LD 00H,#0AH /g111 Register 00H = 0AH LD @00H,#10H /g111 Register 00H = 01H, register 01H = 10H LD @00H,02H /g111 Register 00H = 01H, register 01H = 02, register 02H = 02H LD R0,#LOOP[R1] /g111 R0 = 0FFH, R1 = 0AH LD #LOOP[R0],R1 /g111 Register 31H = 0AH, R0 = 01H, R1 = 0AH 179

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDB — Load Bit LDB dst,src.b LDB dst.b,src Operation: dst(0) /g109 src(b) or dst(b) /g109 src(0) The specified bit of the source is loaded into bit zero (LSB) of the destination, or bit zero of the source is loaded into the specified bit of the destination. No other bits of the destination are affected. The source is unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | b | 0 src 3 6 47 r0 Rb opc src | b | 1 dst 3 6 47 Rb r0 NOTE: In the second byte of the instruction formats, the destination (or source) address is four bits, the bit address 'b' is three bits, and the LSB address value is one bit in length. Examples: Given: R0 = 06H and general register 00H = 05H: LDB R0,00H.2 /g111 R0 = 07H, register 00H = 05H LDB 00H.0,R0 /g111 R0 = 06H, register 00H = 04H In the first example, destination working register R0 contains the value 06H and the source general register 00H the value 05H. The statement "LD R0,00H.2" loads the bit two value of the 00H register into bit zero of the R0 register, leaving the value 07H in register R0. In the second example, 00H is the destination register. The statement "LD 00H.0,R0" loads bit zero of register R0 to the specified bit (bit zero) of the destination register, leaving 04H in general register 00H. 180

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDC/LDE — Load Memory LDC/LDE dst,src Operation: dst /g109 src This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes 'Irr' or 'rr' values an even number for program memory and odd an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c 1. opc dst | src 2 10 C3 r Irr 2. opc src | dst 2 10 D3 Irr r 3. opc dst | src XS 3 12 E7 r XS [rr] 4. opc src | dst XS 3 12 F7 XS [rr] r 5. opc dst | src XLL XL H 4 14 A7 r XL [rr] 6. opc src | dst XLL XL H 4 14 B7 XL [rr] r 7. opc dst | 0000 DAL DA H 4 14 A7 r DA 8. opc src | 0000 DAL DA H 4 14 B7 DA r 9. opc dst | 0001 DAL DA H 4 14 A7 r DA 10. opc src | 0001 DAL DA H 4 14 B7 DA r NOTES: 1. The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0–1. 2. For formats 3 and 4, the destination address 'XS [rr]' and the source address 'XS [rr]' are each one byte. 3. For formats 5 and 6, the destination address 'XL [rr] and the source address 'XL [rr]' are each two bytes. 4. The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory. 181

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDC/LDE — Load Memory LDC/LDE (Continued) Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H; Program memory locations 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H: LDC R0,@RR2 ; R0 /g109 contents of program memory location 0104H ; R 0 = 1 A H , R 2 = 0 1 H , R 3 = 0 4 H LDE R0,@RR2 ; R0 /g109 contents of external data memory location 0104H ; R 0 = 2 A H , R 2 = 0 1 H , R 3 = 0 4 H LDC (note) @RR2,R0 ; 11H (contents of R0) is loaded into program memory ; location 0104H (RR2), ; working registers R0, R2, R3 /g111 no change LDE @RR2,R0 ; 11H (contents of R0) is loaded into external data memory ; location 0104H (RR2), ; working registers R0, R2, R3 /g111 no change LDC R0,#01H[RR2] ; R0 /g109 contents of program memory location 0105H ; (01H + RR2), ; R0 = 6DH, R2 = 01H, R3 = 04H LDE R0,#01H[RR2] ; R0 /g109 contents of external data memory location 0105H ; (01H + RR2), R0 = 7DH, R2 = 01H, R3 = 04H LDC (note) #01H[RR2],R0 ; 11H (contents of R0) is loaded into program memory location ; 0105H (01H + 0104H) LDE #01H[RR2],R0 ; 11H (contents of R0) is loaded into external data memory ; location 0105H (01H + 0104H) LDC R0,#1000H[RR2] ; R0 /g109 contents of program memory location 1104H ; (1000H + 0104H), R0 = 88H, R2 = 01H, R3 = 04H LDE R0,#1000H[RR2] ; R0 /g109 contents of external data memory location 1104H ; (1000H + 0104H), R0 = 98H, R2 = 01H, R3 = 04H LDC R0,1104H ; R0 /g109 contents of program memory location 1104H, R0 = 88H LDE R0,1104H ; R0 /g109 contents of external data memory location 1104H, ; R 0 = 9 8 H LDC (note) 1105H,R0 ; 11H (contents of R0) is loaded into program memory location ; 1105H, (1105H) /g109 11H LDE 1105H,R0 ; 11H (contents of R0) is loaded into external data memory ; location 1105H, (1105H) /g109 11H NOTE: These instructions are not supported by masked ROM type devices. 182

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDCD/LDED — Load Memory and Decrement LDCD/LDED dst,src Operation: dst /g109 src rr /g109 rr – 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected. LDCD references program memory and LDED references external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 10 E2 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH: LDCD R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is decremented by one ; R8 = 0CDH, R6 = 10H, R7 = 32H (RR6 /g109 RR6 – 1) LDED R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is decremented by one (RR6 /g109 RR6 – 1) ; R8 = 0DDH, R6 = 10H, R7 = 32H 183

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDCI/LDEI — Load Memory and Increment LDCI/LDEI dst,src Operation: dst /g109 src rr /g109 r r + 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected. LDCI refers to program memory and LDEI refers to external data memory. The assembler makes 'Irr' even for program memory and odd for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 10 E3 r Irr Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H: LDCI R8,@RR6 ; 0CDH (contents of program memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 /g109 RR6 + 1) ; R8 = 0CDH, R6 = 10H, R7 = 34H LDEI R8,@RR6 ; 0DDH (contents of data memory location 1033H) is loaded ; into R8 and RR6 is incremented by one (RR6 /g109 RR6 + 1) ; R8 = 0DDH, R6 = 10H, R7 = 34H 184

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDCPD/LDEPD — Load Memory with Pre-Decrement LDCPD/ LDEPD dst,src Operation: rr /g109 r r – 1 dst /g109 src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first decremented. The contents of the source location are then loaded into the destination location. The contents of the source are unaffected. LDCPD refers to program memory and LDEPD refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for external data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src | dst 2 14 F2 Irr r Examples: Given: R0 = 77H, R6 = 30H, and R7 = 00H: LDCPD @RR6,R0 ; (RR6 /g109 RR6 – 1) ; 77H (contents of R0) is loaded into program memory location ; 2FFFH (3000H – 1H) ; R 0 = 7 7 H , R 6 = 2 F H , R 7 = 0 F F H LDEPD @RR6,R0 ; (RR6 /g109 RR6 – 1) ; 77H (contents of R0) is loaded into external data memory ; location 2FFFH (3000H – 1H) ; R 0 = 7 7 H , R 6 = 2 F H , R 7 = 0 F F H 185

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDCPI/LDEPI — Load Memory with Pre-Increment LDCPI/ LDEPI dst,src Operation: rr /g109 r r + 1 dst /g109 src These instructions are used for block transfers of data from program or data memory from the register file. The address of the memory location is specified by a working register pair and is first incremented. The contents of the source location are loaded into the destination location. The contents of the source are unaffected. LDCPI refers to program memory and LDEPI refers to external data memory. The assembler makes 'Irr' an even number for program memory and an odd number for data memory. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src | dst 2 14 F3 Irr r Examples: Given: R0 = 7FH, R6 = 21H, and R7 = 0FFH: LDCPI @RR6,R0 ; (RR6 /g109 RR6 + 1) ; 7FH (contents of R0) is loaded into program memory ; location 2200H (21FFH + 1H) ; R 0 = 7 F H , R 6 = 2 2 H , R 7 = 0 0 H LDEPI @RR6,R0 ; (RR6 /g109 RR6 + 1) ; 7FH (contents of R0) is loaded into external data memory ; location 2200H (21FFH + 1H) ; R 0 = 7 F H , R 6 = 2 2 H , R 7 = 0 0 H 186

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LDW — Load Word LDW dst,src Operation: dst /g109 src The contents of the source (a word) are loaded into the destination. The contents of the source are unaffected. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst 3 8 C4 RR RR

8 C5 RR IR

Examples: Given: R4 = 06H, R5 = 1CH, R6 = 05H, R7 = 02H, register 00H = 1AH, register 01H = 02H, register 02H = 03H, and register 03H = 0FH: LDW RR6,RR4 /g111 R6 = 06H, R7 = 1CH, R4 = 06H, R5 = 1CH LDW 00H,02H /g111 Register 00H = 03H, register 01H = 0FH, register 02H = 03H, register 03H = 0FH LDW RR2,@R7 /g111 R 2 = 0 3 H , R 3 = 0 F H , LDW 04H,@01H /g111 Register 04H = 03H, register 05H = 0FH LDW RR6,#1234H /g111 R 6 = 1 2 H , R 7 = 3 4 H LDW 02H,#0FEDH /g111 Register 02H = 0FH, register 03H = 0EDH In the second example, please note that the statement "LDW 00H,02H" loads the contents of the source word 02H, 03H into the destination word 00H, 01H. This leaves the value 03H in general register 00H and the value 0FH in register 01H. The other examples show how to use the LDW instruction with various addressing modes and formats. 187

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification MULT — Multiply (Unsigned) MULT dst,src Operation: dst /g109 d s t /g117 src The 8-bit destination operand (even register of the register pair) is multiplied by the source operand (8 bits) and the product (16 bits) is stored in the register pair specified by the destination address. Both operands are treated as unsigned integers. Flags: C: Set if result is /g33 255; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if MSB of the result is a "1"; cleared otherwise. V: Cleared. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Examples: Given: Register 00H = 20H, register 01H = 03H, register 02H = 09H, register 03H = 06H: MULT 00H, 02H /g111 Register 00H = 01H, register 01H = 20H, register 02H = 09H MULT 00H, @01H /g111 Register 00H = 00H, register 01H = 0C0H MULT 00H, #30H /g111 Register 00H = 06H, register 01H = 00H In the first example, the statement "MULT 00H,02H" multiplies the 8-bit destination operand (in the register 00H of the register pair 00H, 01H) by the source register 02H operand (09H). The 16-bit product, 0120H, is stored in the register pair 00H, 01H. 188

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification NEXT — Next NEXT Operation: PC /g109 @ I P IP /g109 I P + 2 The NEXT instruction is useful when implementing threaded-code languages. The program memory word that is pointed to by the instruction pointer is loaded into the program counter. The instruction pointer is then incremented by two. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 10 0F Example: The following diagram shows one example of how to use the NEXT instruction. Data Before After 0045IP Address Data 0130PC 43 Address H Address L Address H Address Data Memory

130 Routine

120 Next

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification NOP — No Operation NOP Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 FF Example: When the instruction NOP is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time. 190

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OR — Logical OR OR dst,src Operation: dst /g109 d s t O R s r c The source operand is logically ORed with the destination operand and the result is stored in the destination. The contents of the source are unaffected. The OR operation results in a "1" being stored whenever either of the corresponding bits in the two operands is a "1"; otherwise a "0" is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 42 r r 6 43 r lr opc src dst 3 6 44 R R 6 45 R IR opc dst src 3 6 46 R IM Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH: OR R0,R1 /g111 R0 = 3FH, R1 = 2AH OR R0,@R2 /g111 R0 = 37H, R2 = 01H, register 01H = 37H OR 00H,01H /g111 Register 00H = 3FH, register 01H = 37H OR 01H,@00H /g111 Register 00H = 08H, register 01H = 0BFH OR 00H,#02H /g111 Register 00H = 0AH In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0. The other examples show the use of the logical OR instruction with the various addressing modes and formats. 191

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification POP — Pop From Stack POP dst Operation: dst /g109 @SP SP /g109 S P + 1 The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one. Flags: No flags affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 8 50 R 8 51 IR Examples: Given: Register 00H = 01H, register 01H = 1BH, SPH (0D8H) = 00H, SPL (0D9H) = 0FBH, and stack register 0FBH = 55H: POP 00H /g111 Register 00H = 55H, SP = 00FCH POP @00H /g111 Register 00H = 01H, register 01H = 55H, SP = 00FCH In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 00FBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 00FCH. 192

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification POPUD — Pop User Stack (Decrementing) POPUD dst,src Operation: dst /g109 src IR /g109 IR – 1 This instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then decremented. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst 3 8 92 R IR Example: Given: Register 00H = 42H (user stack pointer register), register 42H = 6FH, and register 02H = 70H: POPUD 02H,@00H /g111 Register 00H = 41H, register 02H = 6FH, register 42H = 6FH If general register 00H contains the value 42H and register 42H the value 6FH, the statement "POPUD 02H,@00H" loads the contents of register 42H into the destination register 02H. The user stack pointer is then decremented by one, leaving the value 41H. 193

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification POPUI — Pop User Stack (Incrementing) POPUI dst,src Operation: dst /g109 src IR /g109 IR + 1 The POPUI instruction is used for user-defined stacks in the register file. The contents of the register file location addressed by the user stack pointer are loaded into the destination. The user stack pointer is then incremented. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc src dst 3 8 93 R IR Example: Given: Register 00H = 01H and register 01H = 70H: POPUI 02H,@00H /g111 Register 00H = 02H, register 01H = 70H, register 02H = 70H If general register 00H contains the value 01H and register 01H the value 70H, the statement "POPUI 02H,@00H" loads the value 70H into the destination general register 02H. The user stack pointer (register 00H) is then incremented by one, changing its value from 01H to 02H. 194

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PUSH — Push To Stack PUSH src Operation: SP /g109 S P – 1 @SP /g109 src A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc src 2 8 (internal clock) 70 R 8 (external clock) 8 (internal clock) 8 (external clock) 71 IR Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SPH = 00H, and SPL = 00H: PUSH 40H /g111 Register 40H = 4FH, stack register 0FFH = 4FH, SPH = 0FFH, SPL = 0FFH PUSH @40H /g111 Register 40H = 4FH, register 4FH = 0AAH, stack register 0FFH = 0AAH, SPH = 0FFH, SPL = 0FFH In the first example, if the stack pointer contains the value 0000H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0000 to 0FFFFH. It then loads the contents of register 40H into location 0FFFFH and adds this new value to the top of the stack. 195

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PUSHUD — Push User Stack (Decrementing) PUSHUD dst,src Operation: IR /g109 I R – 1 dst /g109 src This instruction is used to address user-defined stacks in the register file. PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst src 3 8 82 IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 02H = 1AH: PUSHUD @00H,01H /g111 Register 00H = 02H, register 01H = 05H, register 02H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUD @00H,01H" decrements the user stack pointer by one, leaving the value 02H. The 01H register value, 05H, is then loaded into the register addressed by the decremented user stack pointer. 196

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PUSHUI — Push User Stack (Incrementing) PUSHUI dst,src Operation: IR /g109 I R + 1 dst /g109 src This instruction is used for user-defined stacks in the register file. PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst src 3 8 83 IR R Example: Given: Register 00H = 03H, register 01H = 05H, and register 04H = 2AH: PUSHUI @00H,01H /g111 Register 00H = 04H, register 01H = 05H, register 04H = 05H If the user stack pointer (register 00H, for example) contains the value 03H, the statement "PUSHUI @00H,01H" increments the user stack pointer by one, leaving the value 04H. The 01H register value, 05H, is then loaded into the location addressed by the incremented user stack pointer. 197

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RCF — Reset Carry Flag RCF RCF Operation: C /g109 0 The carry flag is cleared to logic zero, regardless of its previous value. Flags: C: Cleared to "0". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 CF Example: Given: C = "1" or "0": The instruction RCF clears the carry flag (C) to logic zero. 198

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RET — Return RET Operation: PC /g109 @SP SP /g109 S P + 2 The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 8 (internal stack) AF 10 (internal stack) Example: Given: SP = 00FCH, (SP) = 101AH, and PC = 1234: RET /g111 PC = 101AH, SP = 00FEH The statement "RET" pops the contents of stack pointer location 00FCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 00FEH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 00FEH. 199

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RL — Rotate Left RL dst Operation: C /g109 dst (7) dst (0) /g109 dst (7) dst (n + 1) /g109 dst (n), n = 0–6 The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag. C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 90 R 4 91 IR Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H: RL 00H /g111 Register 00H = 55H, C = "1" RL @01H /g111 Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags. 200

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RLC — Rotate Left Through Carry RLC dst Operation: dst (0) /g3/g109 C C /g109 dst (7) dst (n + 1) /g109/g3 dst (n), n = 0–6 The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero. C Flags: C: Set if the bit rotated from the most significant bit position (bit 7) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 10 R 4 11 IR Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0": RLC 00H /g111 Register 00H = 54H, C = "1" RLC @01H /g111 Register 01H = 02H, register 02H = 2EH, C = "0" In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag. 201

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RR — Rotate Right RR dst Operation: C /g109 dst (0) dst (7) /g109 dst (0) dst (n /g12/g3/g3/g109 dst (n + 1), n = 0–6 The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C). C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 E0 R

4 E 1 I R

Examples: Given: Register 00H = 31H, register 01H = 02H, and register 02H = 17H: RR 00H /g111 Register 00H = 98H, C = "1" RR @01H /g111 Register 01H = 02H, register 02H = 8BH, C = "1" In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1". 202

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification RRC — Rotate Right Through Carry RRC dst Operation: dst (7) /g109 C C /g109 dst (0) dst (n) /g109 dst (n + 1), n = 0–6 The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB). C Flags: C: Set if the bit rotated from the least significant bit position (bit zero) was "1". Z: Set if the result is "0" cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the sign of the destination changed during rotation; cleared otherwise. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 C0 R

4 C 1 I R

Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0": RRC 00H /g111/g3Register 00H = 2AH, C = "1" RRC @01H /g111 Register 01H = 02H, register 02H = 0BH, C = "1" In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0". 203

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SB0 — Select Bank 0 SB0 Operation: BANK /g3/g109 0 The SB0 instruction clears the bank address flag in the FLAGS register (FLAGS.0) to logic zero, selecting bank 0 register addressing in the set 1 area of the register file. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 4F Example: The statement SB0 clears FLAGS.0 to "0", selecting bank 0 register addressing. 204

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SB1 — Select Bank 1 SB1 Operation: BANK /g109/g3 1 The SB1 instruction sets the bank address flag in the FLAGS register (FLAGS.0) to logic one, selecting bank 1 register addressing in the set 1 area of the register file. (Bank 1 is not implemented in some S3C8-series microcontrollers.) Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 5F Example: The statement SB1 sets FLAGS.0 to "1", selecting bank 1 register addressing, if implemented. 205

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SBC — Subtract with Carry SBC dst,src Operation: dst /g109 dst – src – c The source operand, along with the current value of the carry flag, is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's-complement of the source operand to the destination operand. In multiple precision arithmetic, this instruction permits the carry ("borrow") from the subtraction of the low-order operands to be subtracted from the subtraction of high-order operands. Flags: C: Set if a borrow occurred (src /g33 dst); cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite sign and the sign of the result is the same as the sign of the source; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow". Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 32 r r 6 33 r lr opc src dst 3 6 34 R R 6 35 R IR opc dst src 3 6 36 R IM Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH: SBC R1,R2 /g111 R1 = 0CH, R2 = 03H SBC R1,@R2 /g111 R1 = 05H, R2 = 03H, register 03H = 0AH SBC 01H,02H /g111 Register 01H = 1CH, register 02H = 03H SBC 01H,@02H /g111 Register 01H = 15H,register 02H = 03H, register 03H = 0AH SBC 01H,#8AH /g111 Register 01H = 5H; C, S, and V = "1" In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1. 206

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SCF — Set Carry Flag SCF Operation: C /g3/g109 1 The carry flag (C) is set to logic one, regardless of its previous value. Flags: C: Set to "1". No other flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4 DF Example: The statement SCF sets the carry flag to logic one. 207

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SRA — Shift Right Arithmetic SRA dst Operation: dst (7) /g109 dst (7) C /g109 dst (0) dst (n) /g109 dst (n + 1), n = 0–6 An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6. C Flags: C: Set if the bit shifted from the LSB position (bit zero) was "1". Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 D0 R

4 D 1 I R

Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1": SRA 00H /g111 Register 00H = 0CD, C = "0" SRA @02H /g111 Register 02H = 03H, register 03H = 0DEH, C = "0" In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H. 208

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SRP/SRP0/SRP1 — Set Register Pointer SRP src SRP0 src SRP1 src Operation: If src (1) = 1 and src (0) = 0 then: RP0 (3–7) /g109 src (3–7) If src (1) = 0 and src (0) = 1 then: RP1 (3–7) /g109 src (3–7) If src (1) = 0 and src (0) = 0 then: RP0 (4–7) /g109 src (4–7), RP0 (3) /g109 0 RP1 (3) /g109 1 The source data bits one and zero (LSB) determine whether to write one or both of the register pointers, RP0 and RP1. Bits 3–7 of the selected register pointer are written unless both register pointers are selected. RP0.3 is then cleared to logic zero and RP1.3 is set to logic one. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode src opc src 2 4 31 IM Examples: The statement SRP #40H sets register pointer 0 (RP0) at location 0D6H to 40H and register pointer 1 (RP1) at location 0D7H to 48H. The statement "SRP0 #50H" sets RP0 to 50H, and the statement "SRP1 #68H" sets RP1 to 68H. 209

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification STOP — Stop Operation STOP Operation: The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode. During Stop mode, the contents of on-chip CPU registers, peripheral registers, and I/O port control and data registers are retained. Stop mode can be released by an external reset operation or by external interrupts. For the reset operation, the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed. Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc 1 4 7F – – Example: The statement STOP halts all microcontroller operations. 210

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SUB — Subtract SUB dst,src Operation: dst /g109 dst – src The source operand is subtracted from the destination operand and the result is stored in the destination. The contents of the source are unaffected. Subtraction is performed by adding the two's complement of the source operand to the destination operand. Flags: C: Set if a "borrow" occurred; cleared otherwise. Z: Set if the result is "0"; cleared otherwise. S: Set if the result is negative; cleared otherwise. V: Set if arithmetic overflow occurred, that is, if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand; cleared otherwise. D: Always set to "1". H: Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise indicating a "borrow". Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 22 r r 6 23 r lr opc src dst 3 6 24 R R 6 25 R IR opc dst src 3 6 26 R IM Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH: SUB R1,R2 /g111 R1 = 0FH, R2 = 03H SUB R1,@R2 /g111 R 1 = 0 8 H , R 2 = 0 3 H SUB 01H,02H /g111 Register 01H = 1EH, register 02H = 03H SUB 01H,@02H /g111 Register 01H = 17H, register 02H = 03H SUB 01H,#90H /g111 Register 01H = 91H; C, S, and V = "1" SUB 01H,#65H /g111 Register 01H = 0BCH; C and S = "1", V = "0" In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1. 211

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SWAP — Swap Nibbles SWAP dst Operation: dst (0 – 3) /g108 dst (4 – 7) The contents of the lower four bits and upper four bits of the destination operand are swapped. 70 4 3 Flags: C: Undefined. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Undefined. D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst opc dst 2 4 F0 R

4 F 1 I R

Examples: Given: Register 00H = 3EH, register 02H = 03H, and register 03H = 0A4H: SWAP 00H /g111 Register 00H = 0E3H SWAP @02H /g111 Register 02H = 03H, register 03H = 4AH In the first example, if general register 00H contains the value 3EH (00111110B), the statement "SWAP 00H" swaps the lower and upper four bits (nibbles) in the 00H register, leaving the value 0E3H (11100011B). 212

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TCM — Test Complement Under Mask TCM dst,src Operation: (NOT dst) AND src This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always cleared to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 62 r r 6 63 r lr opc src dst 3 6 64 R R 6 65 R IR opc dst src 3 6 66 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TCM R0,R1 /g111 R 0 = 0 C 7 H , R 1 = 0 2 H , Z = " 1 " TCM R0,@R1 /g111 R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" TCM 00H,01H /g111 Register 00H = 2BH, register 01H = 02H, Z = "1" TCM 00H,@01H /g111 Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "1" TCM 00H,#34 /g111 Register 00H = 2BH, Z = "0" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation. 213

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TM — Test Under Mask TM dst,src Operation: dst AND src This instruction tests selected bits in the destination operand for a logic zero value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask), which is ANDed with the destination operand. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 72 r r 6 73 r lr opc src dst 3 6 74 R R 6 75 R IR opc dst src 3 6 76 R IM Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: TM R0,R1 /g111 R 0 = 0 C 7 H , R 1 = 0 2 H , Z = " 0 " TM R0,@R1 /g111 R0 = 0C7H, R1 = 02H, register 02H = 23H, Z = "0" TM 00H,01H /g111 Register 00H = 2BH, register 01H = 02H, Z = "0" TM 00H,@01H /g111 Register 00H = 2BH, register 01H = 02H, register 02H = 23H, Z = "0" TM 00H,#54H /g111 Register 00H = 2BH, Z = "1" In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation. 214

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification WFI — Wait for Interrupt WFI Operation: The CPU is effectively halted until an interrupt occurs, except that DMA transfers can still take place during this wait state. The WFI status can be released by an internal interrupt, including a fast interrupt . Flags: No flags are affected. Format: Bytes Cycles Opcode (Hex) opc 1 4n 3F ( n = 1, 2, 3, … ) Example: The following sample program structure shows the sequence of operations that follow a "WFI" statement: EI WFI (Next instruction) Main program ... ... Interrupt occurs Interrupt service routine ... Clear interrupt flag IRET Service routine completed (Enable global interrupt) (Wait for interrupt) 215

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification XOR — Logical Exclusive OR XOR dst,src Operation: dst /g109 d s t X O R s r c The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored. Flags: C: Unaffected. Z: Set if the result is "0"; cleared otherwise. S: Set if the result bit 7 is set; cleared otherwise. V: Always reset to "0". D: Unaffected. H: Unaffected. Format: Bytes Cycles Opcode (Hex) Addr Mode dst s r c opc dst | src 2 4 B2 r r

6 B 3 r l r

6 B 5 R I R

Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H: XOR R0,R1 /g111 R0 = 0C5H, R1 = 02H XOR R0,@R1 /g111 R0 = 0E4H, R1 = 02H, register 02H = 23H XOR 00H,01H /g111 Register 00H = 29H, register 01H = 02H XOR 00H,@01H /g111 Register 00H = 08H, register 01H = 02H, register 02H = 23H XOR 00H,#54H /g111 Register 00H = 7FH In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0. 216

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

7 CLOCK CIRCUIT

The S3F82NB microcontroller has two oscillator circuits: a main clock and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency of S3F82NB is determined by CLKCON register settings. SYSTEM CLOCK CIRCUIT The system clock circuit has the following components: — External crystal, ceramic resonator, RC oscillation source, or an external clock source — Oscillator stop and wake-up functions — Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16) — System clock control register, CLKCON — Oscillator control register, OSCCON and STOP control register, STPCON CPU CLOCK NOTATION In this document, the following notation is used for descriptions of the CPU clock; fx: main clock fxt: sub clock fxx: selected system clock 217

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CLOCK STATUS DURING POWER-DOWN MODES The two power-down modes, Stop mode and Idle mode, affect the system clock as follows: — In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator is started, by a reset operation or an external interrupt (with RC delay noise filter), and can be released by internal interrupt too when the sub-system oscillator is running and watch timer is operating with sub-system clock. — In Idle mode, the internal clock signal is gated to the CPU, but not to interrupt structure, timers and timer/ counters. Idle mode is released by a reset or by an external or internal interrupt. 1/1-1/4096 Frequency Dividing Circuit Stop Release Main-System Oscillator Circuit Selector 1 fX fXt Stop Sub-system Oscillator Circuit INT OSCCON.0 OSCCON.3 OSCCON.2 Selector 2 STPCON STOP OSC inst. fXX CLKCON.4-.3 CPU Clock Stop Watch Timer Basic Timer Timer/Counters 0, 1/A Watch Timer LCD Controller SIO A/D Converter Comparator LVR IDLE Instruction 1/1 1/161/2 1/8 LCD Controller Figure 7-6. System Clock Circuit Diagram 219

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SYSTEM CLOCK CONTROL REGISTER (CLKCON) The system clock control register, CLKCON, is located in the set 1, address D4H. It is read/write addressable and has the following functions: — Oscillator frequency divide-by value After the main oscillator is activated, and the fxx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed fxx/8, fxx/2, or fxx/1. System Clock Control Register (CLKCON) D4H, Set 1, R/W Not used (must keep always 0) Not used (must keep always 0) Divide-by selection bits for CPU clock frequency: 00 = fXX/16 01 = fXX/8 10 = fXX/2 11 = fXX/1 Oscillator IRQ wake-up function bit: 0 = Enable IRQ for main wake-up in power down mode 1 = Disable IRQ for main wake-up in power down mode NOTE: After a reset, the slowest clock (divided by 16) is selected as the system clock. To select faster speed, load the appropriate values to CLKCON.3-.4. Figure 7-7. System Clock Control Register (CLKCON) 220

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OSCILLATOR CONTROL REGISTER (OSCCON) The oscillator control register, OSCCON, is located in set 1, bank 0, at address FAH. It is read/write addressable and has the following functions: — System clock selection — Main oscillator control — Sub oscillator control OSCCON.0 register settings select Main clock or Sub clock as system clock. After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0". The main oscillator can be stopped or run by setting OSCCON.3. The sub oscillator can be stopped or run by setting OSCCON.2. Oscillator Control Register (OSCCON) FAH, Set 1, Bank 0, R/W Main system oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP Sub system oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP Not used for S3F82NB System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select Not used for S3F82NB Figure 7-8. Oscillator Control Register (OSCCON) 221

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification STOP CONTROL REGISTER (STPCON) The STOP control register, STPCON, is located in the bank 0 of set1, address F5H. It is read/write addressable and has the following functions: — Enable/Disable STOP instruction After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B". STOP Control Register (STPCON) F5H, Set 1, bank 0, R/W STOP Control bits: Other values = Disable STOP instruction 10100101 = Enable STOP instruction NOTE: Before executing the STOP instruction, set the STPCON register as "10100101b". Otherwise the STOP instruction will not be executed and reset will be generated. Figure 7-9. STOP Control Register (STPCON) /g41/g3PROGRAMMING TIP — How to Use Stop Instruction This example shows how to go STOP mode when a main clock is selected as the system clock. LD STOPCON,#1010010B ; Enable STOP instruction STOP ; Enter STOP mode NOP NOP NOP ; Release STOP mode LD STOPCON,#00000000B ; Disable STOP instruction 222

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SWITCHING THE CPU CLOCK Data loading in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies. OSCCON.0 selects the main clock (fx) or the sub clock (fxt) for the CPU clock. OSCCON .3 start or stop main clock oscillation and OSCCON.2 start or stop sub clock oscillation. CLKCON.4–.3 controls the frequency divider circuit, and divides the selected fxx clock by 1, 2, 8 and 16. If the sub clock (fxt) is selected for system clock, the CLKCON.4–.3 must be set to “11”. For example, you are using the default CPU clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set CLKCON.4- .3 to "11", OSCCON.0 to “1”, and OSCCON.3 to “1” by turns. This switches the clock from fx to fxt and stops main clock oscillation. The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to “0” to enable main clock oscillation. Then, after a certain number of machine cycles have elapsed, select the main clock by setting OSCCON.0 to “0”. /g41/g3PROGRAMMING TIP — Switching the CPU Clock 1. This example shows how to change from the main clock to the sub clock: MA2SUB OR CLKCON,#18H ; Non-divided clock for system clock LD OSCCON,#01H ; Switches to the sub clock CALL DLY16 ; Delay 16 ms OR OSCCON,#08H ; Stop the main clock oscillation RET 2. This example shows how to change from sub clock to main clock: SUB2MA AND OSCCON,#07H ; Start the main clock oscillation CALL DLY16 ; Delay 16 ms AND OSCCON,#06H ; Switch to the main clock RET DLY16 SRP #0C0H LD R0,#20H DEL NOP DJNZ R0,DEL RET 223

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

8 RESET and POWER-DOWN

During a power-on reset, the voltage at VDD goes to High level and the nRESET pin is forced to Low level. The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings the S3F82NB into a known operating status. To allow time for internal CPU clock oscillation to stabilize, the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required time of a reset operation for oscillation stabilization is 1 millisecond. Whenever a reset occurs during normal operation (that is, when both V DD and nRESET are High level), the nRESET pin is forced Low level and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values In summary, the following sequence of events occurs during a reset operation: — All interrupt is disabled. — The watchdog function (basic timer) is enabled. — Ports 0-10 and set to input mode, and all pull-up resistors are disabled for the I/O port. — Peripheral control and data register settings are disabled and reset to their default hardware values. — The program counter (PC) is loaded with the program reset address in the ROM, 0100H. — When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed at normal mode by smart option. — The reset address at ROM can be changed by Smart Option in the S3F82NB (full-flash device). Refer to "The Chapter 18. Embedded Flash Memory Interface" for more detailed contents. NORMAL MODE RESET OPERATION In normal mode, the Test pin is tied to V SS. A reset enables access to the 64-Kbyte on-chip ROM. (The external interface is not automatically configured). NOTE To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing "1010B" to the upper nibble of BTCON. 224

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification HARDWARE RESET VALUES Table 8-1, 8-2, 8-3, 8-4 list the reset values for CPU and system registers, peripheral control registers, and peripheral data registers following a reset operation. The following notation is used to represent reset values: — A "1" or a "0" shows the reset bit value as logic one or logic zero, respectively. — An "x" means that the bit value is undefined after a reset. — A dash ("–") means that the bit is either not used or not mapped, but read 0 is the bit value. Table 8-1. S3F82NB Set 1 Register and Values after RESET Register Name Mnemonic Address Bit Values after RESET D e cH e x7654 3 2 10 Locations D0H–D2H are not mapped. Basic timer control register BTCON 211 D3H 0000 0 0 00 System clock control register CLKCON 212 D4H 0––0 0 – –– System flags register FLAGS 213 D5H x x x x x x 0 0 Register pointer 0 RP0 214 D6H 1100 0 – –– Register pointer 1 RP1 215 D7H 1100 1 – –– Stack pointer (high byte) SPH 216 D8H x x x x x x x x Stack pointer (low byte) SPL 217 D9H x x x x x x x x Instruction pointer (high byte) IPH 218 DAH x x x x x x x x Instruction pointer (low byte) IPL 219 DBH x x x x x x x x Interrupt request register IRQ 220 DCH 0000 0 0 00 Interrupt mask register IMR 221 DDH x x x x x x x x System mode register SYM 222 DEH 0 – – x x x 0 0 Register page pointer PP 223 DFH 0000 0 0 00 NOTES: 1. An 'x' means that the bit value is undefined following reset. 2. A dash ('-') means that the bit is neither used nor mapped, but the bit is read as “0”. Table 8-2. S3F82NB Page15 Register and Values after RESET Register Name Mnemonic Address Bit Values after RESET Dec Hex 7 6 5 4 3 2 1 0 Reset Source Indicating Register RESETID 176 B0H Refer to the Page 4-51. NOTES: 1. An 'x' means that the bit value is undefined following reset. 2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”. 225

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 8-3. S3F82NB Set 1, Bank 0 Register and Values after RESET Register Name Mnemonic Address Bit Values after RESET Dec Hex 7 6 5 4 3 2 1 0 Port Group 0 Control Register PG0CON 208 D0H 0 0 0 0 0 0 0 0 Port Group 1 Control Register PG1CON 209 D1H 0 0 0 0 0 0 0 0 Port 6 Control Register P6CON 210 D2H – – 0 0 0 0 0 0 A/D Converter Data Register (High Byte) ADDATAH 224 E0H x x x x x x x x A/D Converter Data Register (Low Byte) ADDATAL 225 E1H – – – – – – x x A/D Converter Control Register ADCON 226 E2H – 0 0 0 0 0 0 0 Timer 0 Counter Register T0CNT 227 E3H 0 0 0 0 0 0 0 0 Timer 0 Data Register T0DATA 228 E4H 1 1 1 1 1 1 1 1 Timer 0 Control Register T0CON 229 E5H 0 0 0 0 0 0 0 – Timer B Counter Register TBCNT 230 E6H 0 0 0 0 0 0 0 0 Timer A Counter Register TACNT 231 E7H 0 0 0 0 0 0 0 0 Timer B Data Register TBDATA 232 E8H 1 1 1 1 1 1 1 1 Timer A Data Register TADATA 233 E9H 1 1 1 1 1 1 1 1 Timer B Control Register TBCON 234 EAH 0 0 0 – – 0 0 – Timer 1/A Control Register TACON 235 EBH 0 0 0 0 0 0 0 0 Timer Interrupt Pending Register TINTPND 236 ECH – – – 0 0 0 0 0 Timer Interrupt Control Register TINTCON 237 EDH – – – 0 0 0 0 0 Watch Timer Control Register WTCON 238 EEH 0 0 0 0 0 0 0 0 LCD Control Register LCON 239 EFH 0 0 0 0 0 – – 0 LCD Mode Register LMOD 240 F0H 0 0 0 0 0 – – – Comparator Control Register CMPCON 241 F1H 0 0 0 – 0 0 0 0 Comparator Result Register CMPREG 242 F2H – – – – – 0 0 0 SIO Control Register SIOCON 243 F3H 0 0 0 0 0 0 0 0 SIO Data Register SIODATA 244 F4H 0 0 0 0 0 0 0 0 SIO Pre-scaler Register SIOPS 245 F5H 0 0 0 0 0 0 0 0 Flash Memory Sector Address Register (High Byte) FMSECH 246 F6H 0 0 0 0 0 0 0 0 Flash Memory Sector Address Register (Low Byte) FMSECL 247 F7H 0 0 0 0 0 0 0 0 Flash Memory User Programming Enable Register FMUSR 248 F8H 0 0 0 0 0 0 0 0 Flash Memory Control Register FMCON 249 F9H 0 0 0 0 0 – – 0 Oscillator Control Register OSCCON 250 FAH – – – – 0 0 – 0 STOP Control register STPCON 251 FBH 0 0 0 0 0 0 0 0 Location FCH is not mapped. Basic Timer Counter BTCNT 253 FDH 0 0 0 0 0 0 0 0 Location FEH is not mapped. Interrupt Priority Register IPR 255 FFH x x x x x x x x NOTES: 1. An 'x' means that the bit value is undefined following reset. 2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”. 226

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 8-4. S3F82NB Set 1, Bank 1 Register and Values after RESET Register Name Mnemonic Address Bit Values after RESET Dec Hex 7 6 5 4 3 2 1 0 Port 4 Control Register (High Byte) P4CONH 208 D0H 0 0 0 0 0 0 0 0 Port 4 Control Register (Low Byte) P4CONL 209 D1H 0 0 0 0 0 0 0 0 Port 4 Pull-up Resistor Enable Register P4PUR 210 D2H 0 0 0 0 0 0 0 0 Port 0 Control Register (High Byte) P0CONH 224 E0H 0 0 0 0 0 0 0 0 Port 0 Control Register (Low Byte) P0CONL 225 E1H 0 0 0 0 0 0 0 0 Port 0 Pull-up Resistor Enable Register P0PUR 226 E2H 0 0 0 0 0 0 0 0 Alternative Function Selection Register AFSEL 227 E3H – – – – – – 0 0 Port 1 Control Register (High Byte) P1CONH 228 E4H 0 0 0 0 0 0 0 0 Port 1 Control Register (Low Byte) P1CONL 229 E5H 0 0 0 0 0 0 0 0 Port 1 Pull-up Resistor Enable Register P1PUR 230 E6H 0 0 0 0 0 0 0 0 Port 1 Interrupt Pending Register P1PND 231 E7H 0 0 0 0 0 0 0 0 Port 1 Interrupt Control Register (High Byte) P1INTH 232 E8H 0 0 0 0 0 0 0 0 Port 1 Interrupt Control Register (Low Byte) P1INTL 233 E9H 0 0 0 0 0 0 0 0 Port 2 Control Register (High Byte) P2CONH 234 EAH 0 0 0 0 0 0 0 0 Port 2 Control Register (Low Byte) P2CONL 235 EBH 0 0 0 0 0 0 0 0 Port 2 Pull-up Resistor Enable Register P2PUR 236 ECH 0 0 0 0 0 0 0 0 Port 3 Pull-up Resistor Enable Register P3PUR 237 EDH – – 0 0 0 0 0 0 Port 3 Control Register (High Byte) P3CONH 238 EEH 0 0 0 0 0 0 0 0 Port 3 Control Register (Low Byte) P3CONL 239 EFH 0 0 0 0 0 0 0 0 Port 0 Data Register P0 240 F0H 0 0 0 0 0 0 0 0 Port 1 Data Register P1 241 F1H 0 0 0 0 0 0 0 0 Port 2 Data Register P2 242 F2H 0 0 0 0 0 0 0 0 Port 3 Data Register P3 243 F3H 0 0 0 0 0 0 0 0 Port 4 Data Register P4 244 F4H 0 0 0 0 0 0 0 0 Port 5 Data Register P5 245 F5H 0 0 0 0 0 0 0 0 Port 6 Data Register P6 246 F6H – – – – – 0 0 0 Port 7 Data Register P7 247 F7H 0 0 0 0 0 0 0 0 Port 8 Data Register P8 248 F8H 0 0 0 0 0 0 0 0 Port 9 Data Register P9 249 F9H 0 0 0 0 0 0 0 0 Port 10 Data Register P10 250 FAH 0 0 0 0 0 0 0 0 Port 5 Interrupt Control Register P5INT 251 FBH 0 0 0 0 0 0 0 0 Port 5 Interrupt Pending Register P5PND 252 FCH 0 0 0 0 – – – – Port 5 Pull-up Resistor Enable Register P5PUR 253 FDH 0 0 0 0 0 0 0 0 Port 5 Control Register (High Byte) P5CONH 254 FEH 0 0 0 0 0 0 0 0 Port 5 Control Register (Low Byte) P5CONL 255 FFH 0 0 0 0 0 0 0 0 NOTES: 1. An 'x' means that the bit value is undefined following reset. 2. A dash ('–') means that the bit is neither used nor mapped, but the bit is read as “0”. 227

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification POWER-DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP (opcode 7FH). In Stop mode, the operation of the CPU and all peripherals is halted. That is, the on-chip main oscillator stops and the supply current is reduced to less than 3/g80A. All system functions stop when the clock “freezes”, but data stored in the internal register file is retained. Stop mode can be released in one of two ways: by a reset or by interrupts, for more details see Figure 7-6. NOTE Do not use stop mode if you are using an external clock source because XIN or XTIN input must be restricted internally to VSS to reduce current leakage. Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns to high level: all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. A reset operation automatically selects a slow clock fxx/16 because CLKCON.3 and CLKCON.4 are cleared to ‘00B’. After the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H (and 0101H) Using an External Interrupt to Release Stop Mode External interrupts with an RC-delay noise filter circuit can be used to release Stop mode. Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller’s current internal operating mode. The external interrupts in the S3F82NB interrupt structure that can be used to release Stop mode are: — External interrupts P1.0–P1.7, P5.4–P5.7 (INT0–INT11) Please note the following conditions for Stop mode release: — If you release Stop mode using an external interrupt, the current values in system and peripheral control registers are unchanged except STPCON register. — If you use an internal or external interrupt for Stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering Stop mode. — When the Stop mode is released by external interrupt, the CLKCON.4 and CLKCON.3 bit-pair setting remains unchanged and the currently selected clock value is used. — The external interrupt is serviced when the Stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated Stop mode is executed. Using an Internal Interrupt to Release Stop Mode Activate any enabled interrupt, causing Stop mode to be released. Other things are same as using external interrupt. How to Enter into Stop Mode Handling STPCON register then writing STOP instruction (keep the order). LD STPCON,#10100101B STOP NOP NOP NOP 228

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification IDLE MODE Idle mode is invoked by the instruction IDLE (opcode 6FH). In idle mode, CPU operations are halted while some peripherals remain active. During idle mode, the internal clock signal is gated away from the CPU, but all peripherals timers remain active. Port pins retain the mode (input or output) they had at the time idle mode was entered. There are two ways to release idle mode: 1. Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slow clock fxx/16 because CLKCON.4 and CLKCON.3 are cleared to ‘00B’. If interrupts are masked, a reset is the only way to release idle mode. 2. Activate any enabled interrupt, causing idle mode to be released. When you use an interrupt to release idle mode, the CLKCON.4 and CLKCON.3 register values remain unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt (IRET) occurs, the instruction immediately following the one that initiated idle mode is executed. 229

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

9 I/O PORTS

The S3F82NB microcontroller has eleven bit-programmable I/O ports, P0–P10. The port 6 is a 3-bit port and the others are 8-bit ports. This gives a total of 83 I/O pins. Each port can be flexibly configured to meet application design requirements. The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. Table 9-1 gives you a general overview of the S3F82NB I/O port functions. 230

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 9-1. S3F82NB Port Configuration Overview Port Configuration Options 0 1-bit programmable I/O port. Input (P0.0 and P0.1 are Schmitt trigger input) or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternately P0.0–P0.7 can be used as T1CLK/AD0, T0CLK/AD1, T1OUT/T1PWM/T1CAP/AD2, T0OUT/T0PWM/T0CAP/AD3, AD4–AD7. 1 1-bit programmable I/O port. Schmitt trigger input or push-pull, open-drain output mode selected by software; software assignable pull-ups. P1.0–P1.7 can be used as inputs for external interrupts INT0–INT7 (with noise filter, interrupt enable and pending control). The P1.0 is configured as one of the P1.0/INT0 and AV REF by “Smart option”. Alternately P1.0–P1.7 can be used as BUZ, SI, SO, SCK. 2 1-bit programmable I/O port. Input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternatively P2.0-P2.7 can be used as outputs for LCD SEG. 3 1-bit programmable I/O port. Input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternatively P3.0-P3.7 can be used as outputs for LCD SEG. 4 1-bit programmable I/O port. Input or push-pull, open-drain output mode selected by software; software assignable pull-ups. Alternatively P4.0-P4.7 can be used as outputs for LCD SEG. 5 1-bit programmable I/O port. Input (P5.4–P5.7 are Schmitt trigger input) or push-pull, open-drain output mode selected by software; software assignable pull-ups. P5.4–P5.7 can be used as inputs for external interrupts INT8–INT11 (with noise filter, interrupt enable and pending control). Alternatively P5.0-P5.7 can be used as outputs for LCD SEG. 6 1-bit programmable I/O port. Schmitt trigger input or push-pull output mode selected by software; software assignable pull-ups. Alternatively P6.0–P6.2 can be used as CIN0–CIN2. 7 4-bit programmable I/O port. Input or push-pull output mode selected by software; software assignable pull-ups. Alternatively P7.0–P7.7 can be used as outputs for LCD SEG. 8 4-bit programmable I/O port. Input or push-pull output mode selected by software; software assignable pull-ups. Alternatively P8.0–P8.7 can be used as outputs for LCD SEG. 9 4-bit programmable I/O port. Input or push-pull output mode selected by software; software assignable pull-ups. Alternatively P9.0–P9.7 can be used as outputs for LCD SEG. 10 4-bit programmable I/O port. Input or push-pull output mode selected by software; software assignable pull-ups. Alternatively P10.0–P10.7 can be used as outputs for LCD SEG. 231

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT DATA REGISTERS Table 9-2 gives you an overview of the register locations of all twelve S3F82NB I/O port data registers. Data registers for ports 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 have the general format shown in Figure 9-1. Table 9-2. Port Data Register Summary Register Name Mnemonic Decimal Hex Location R/W Port 0 data register P0 0 F0H Set 1, Bank 1 R/W Port 1 data register P1 1 F1H Set 1, Bank 1 R/W Port 2 data register P2 2 F2H Set 1, Bank 1 R/W Port 3 data register P3 3 F3H Set 1, Bank 1 R/W Port 4 data register P4 4 F4H Set 1, Bank 1 R/W Port 5 data register P5 5 F5H Set 1, Bank 1 R/W Port 6 data register P6 6 F6H Set 1, Bank 1 R/W Port 7 data register P7 7 F7H Set 1, Bank 1 R/W Port 8 data register P8 8 F8H Set 1, Bank 1 R/W Port 9 data register P9 9 F9H Set 1, Bank 1 R/W Port 10 data register P10 10 FAH Set 1, Bank 1 R/W MSB S3F82NB I/O Port Data Register Format (n = 0-10) Figure 9-1. S3F82NB I/O Port Data Register Format 232

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 0 Port 0 is an 8-bit I/O port that can be used for general purpose I/O as A/D converter inputs, AD0-AD7. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location F0H in Set 1, Bank 1. P0.0–P0.7 can serve as inputs (with or without pull-ups), as outputs (push-pull or open-drain). And you can configure the following alternative functions: — Low-byte pins (P0.0–P0.3): AD0/T1CLK, AD1/T0CLK, AD2/T1OUT/T1PWM/T1CAP, AD3/T0OUT/T0PWM/T0CAP — High-byte pins (P0.4–P0.7): AD4-AD7 Port 0 Control Register (P0CONH, P0CONL) P0CONH and P0CONL registers to "00H", configuring all pins to input mode. You use control registers settings to select input or output mode, enable pull-up resistors, select push-pull or open-drain output mode and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 0 control registers must also be enabled in the associated peripheral module. Port 0 Pull-up Resistor Enable Register (P0PUR) Using the port 0 pull-up resistor enable register, P0PUR (E2H, set1, bank1), you can configure pull-up resistors to individual port 0 pins. Alternative Function Selection Register (AFSEL) Using the port 0 alternative function selection register, AFSEL (E3H, set1, bank1), you can configure alternative mode to P0.2 and P0.3. The AD3 or T0OUT/T0PWM outputs depend on AFSEL.1 and the AD2 or T1OUT/T1PWM outputs depend on AFSEL.0. Port 0 Control Register, High Byte (P0CONH) E0H, Set 1, Bank 1, R/W P0.6/AD6 P0.5/AD5 P0.4/AD4 P0CONH bit-pair pin configuration settings: Input mode Output mode, open-drain Output mode, push-pull Alternative function (AD4-AD7) P0.7/AD7 Figure 9-2. Port 0 High-Byte Control Register (P0CONH) 233

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Alternative Function Selection Register (AFSEL) E3H, Set 1, Bank 1, R/W P0.3 Alternative mode selection bit: Alternative Function (AD3) Not used for the S3F82NB Alternative Function (T0OUT/T0PWM) P0.2 Alternative mode selection bit: Alternative Function (AD2) Alternative Function (T1OUT/T1PWM) Figure 9-5. Alternative Function Selection Register (AFSEL) 235

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 1 Port 1 is an 8-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location F1H in set 1, bank 1. P1.0–P1.7 can serve as inputs (with or without pull- ups), as outputs (push-pull or open-drain). P1.0 is configured as one of the P1.0/INT0 and AVREF by “Smart option”. And you can configure the following alternative functions: — Low-byte pins (P1.0-P1.3): AV REF — High-byte pins (P1.4-P1.7): BUZ, SI, SO, SCK Port 1 Control Register (P1CONH, P1CONL) P1CONH and P1CONL registers to "00H", configuring all pins to input mode. In input mode, three different selections are available: — Schmitt trigger input with interrupt generation on falling signal edges. — Schmitt trigger input with interrupt generation on rising signal edges. — Schmitt trigger input with interrupt generation on falling/rising signal edges. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 1 control registers must also be enabled in the associated peripheral module. Port 1 Pull-up Resistor Enable Register (P1PUR) Using the port 1 pull-up resistor enable register, P1PUR (E6H, set1, bank1), you can configure pull-up resistors to individual port 1 pins. Port 1 Interrupt Enable and Pending Registers (P1INTH, P1INTL, P1PND) To process external interrupts at the port 1 pins, the additional control registers are provided: the port 1 interrupt enable register P1INTH (high byte, E8H, set 1, bank 1), P1INTL (Low byte, E9H, set1, bank1) and the port 1 interrupt pending register P1PND (E7H, set 1, bank 1). The port 1 interrupt pending register P1PND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P1PND register at regular intervals. When the interrupt enable bit of any port 1 pin is “1”, a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P1PND bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a “0” to the corresponding P1PND bit. 236

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Port 1 Control Register, High Byte (P1CONH) E4H, Set 1, Bank 1, R/W P1CONH bit-pair pin configuration settings: 11 Alternative function (BUZ, SO, SCK, not used for P1.5) P1.4/INT4 /BUZ P1.5/INT5 /SI P1.6/INT6 /SO P1.7/INT7 /SCK Output mode, push-pull Schmitt trigger input mode (SCK, SI) Output mode, open-drain Figure 9-6. Port 1 High-Byte Control Register (P1CONH) Port 1 Control Register, Low Byte (P1CONL) E5H, Set 1, Bank 1, R/W

11 Not available

P1.0/INT0 /AVREF P1.1/INT1P1.2/INT2P1.3/INT3 Output mode, push-pull Schmitt trigger input mode Output mode, open-drain P1CONL bit-pair pin configuration settings: NOTE: Refer to the SMART OPTION for configuring as one of the P1.0/INT0 and AVREF. Figure 9-7. Port 1 Low-Byte Control Register (P1CONL) 237

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Port 1 Pull-up Resistor Enable Register (P1PUR) E6H, Set 1, Bank 1, R/W P1PUR bit configuration settings: Disable Pull-up Resistor Enable Pull-up Resistor NOTE: A pull-up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function. Figure 9-8. Port 1 Pull-up Resistor Enable Register (P1PUR) Port 1 Interrupt Control Register, High Byte (P1INTH) E8H, Set 1, Bank 1, R/W INT7 INT6 INT5 INT4 P1INTH bit-pair pin configuration settings: Disable interrupt Enable interrupt by falling edge

10 Enable interrupt by rising edge

11 Enable interrupt by both falling and rising edge

Figure 9-9. Port 1 High-Byte Interrupt Control Register (P1INTH) 238

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Port 1 Interrupt Control Register, Low Byte (P1INTL) E9H, Set 1, Bank 1, R/W INT3 INT2 INT1 INT0 P1INTL bit-pair pin configuration settings: Disable interrupt Enable interrupt by falling edge Figure 9-10. Port 1 Low-Byte Interrupt Control Register (P1INTL) Port 1 Interrupt Pending Register (P1PND) E7H, Set 1, Bank 1, R/W PND7 PND6 PND5 PND4 PND3 PND2 PND1 PND0 P1PND bit configuration settings: Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Figure 9-11. Port 1 Interrupt Pending Register (P1PND) 239

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 2 Port 2 is an 8-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location F2H in set 1, bank 1. P2.0–P2.7 can serve as inputs (with or without pull- ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also. Port 2 Control Register (P2CONH, P2CONL) P2CONH and P2CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the alternative functions. Port 2 Pull-up Resistor Enable Register (P2PUR) Using the port 2 pull-up resistor enable register, P2PUR (ECH, set1, bank1), you can configure pull-up resistors to individual port 2 pins. Port 2 Control Register, High Byte (P2CONH) EAH, Set 1, Bank 1, R/W P2.6/SEG62 P2.5/SEG61 P2.4/SEG60 P2CONH bit-pair pin configuration settings: Input mode Output mode, Open-drain Output mode, Push-pull Alternative function (SEG60-SEG63) P2.7/SEG63 Figure 9-12. Port 2 High-Byte Control Register (P2CONH) 240

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 3 Port 3 is an 8-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location F3H in set 1, bank 1. P3.0–P3.7 can serve as inputs (with or without pull- ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also. Port 3 Control Register (P3CONH, P3CONL) P3CONH and P3CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the alternative functions. Port 3 Pull-up Resistor Enable Register (P3PUR) Using the port 3 pull-up resistor enable register, P3PUR (EDH, set1, bank1), you can configure pull-up resistors to individual port 3 pins. Port 3 Control Register, High Byte (P3CONH) EEH, Set 1, Bank 1, R/W P3.6/SEG70 P3.5/SEG69 P3.4/SEG68 P3CONH bit-pair pin configuration settings: Input mode Output mode, Open-drain Output mode, Push-pull Alternative function (SEG68-SEG71) P3.7/SEG71 Figure 9-15. Port 3 High-Byte Control Register (P3CONH) 242

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 4 Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location F4H in set 1, bank 1. P4.0–P4.7 can serve as inputs (with or without pull- ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also. Port 4 Control Register (P4CONH, P4CONL) P4CONH and P4CONL registers to “00H”, configuring all pins to input mode. You use control registers settings to select input or output mode, enable pull-up resistors, select push-pull or open drain output mode and enable the alternative functions. Port 4 Pull-up Resistor Enable Register (P4PUR) Using the port 4 pull-up resistor enable register, P4PUR (D2H, set1, bank1), you can configure pull-up resistors to individual port 4 pins. Port 4 Control Register, High Byte (P4CONH) D0H, Set 1, Bank 1, R/W P4.6/SEG78 P4.5/SEG77 P4.4/SEG76 P4CONH bit-pair pin configuration settings: Input mode Output mode, Open-drain Output mode, Push-pull Alternative function (SEG76-SEG79) P4.7/SEG79 Figure 9-18. Port 4 High-Byte Control Register (P4CONH) 244

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 5 Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location F5H in set 1, bank 1. P5.0–P5.7 can serve as inputs (with or without pull- ups), as outputs (push-pull or open-drain). And they can serve as segment pins for LCD also. And you can configure the following alternative functions: — High-byte pins (P5.4–P5.7): INT8-INT11 Port 5 Control Register (P5CONH, P5CONL) P5CONH and P5CONL registers to "00H", configuring all pins to input mode. In input mode, three different selections are available: — Schmitt trigger input with interrupt generation on falling signal edges. — Schmitt trigger input with interrupt generation on rising signal edges. — Schmitt trigger input with interrupt generation on falling/rising signal edges. Port 5 Interrupt Enable and Pending Registers (P5INT, P5PND) To process external interrupts at the port 5 pins, the additional control registers are provided: the port 5 interrupt enable register P5INT (FBH, set 1, bank 1) and the port 5 interrupt pending register P5PND (FCH, set 1, bank 1). The port 5 interrupt pending register P5PND lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the P5PND register at regular intervals. When the interrupt enable bit of any port 5 pin is “1”, a rising or falling signal edge at that pin will generate an interrupt request. The corresponding P5PND bit is then automatically set to “1” and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a “0” to the corresponding P5PND bit. 246

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Port 5 Pull-up Resistor Enable Register (P5PUR) FDH, Set 1, Bank 1, R/W P5PUR bit configuration settings: Disable Pull-up Resistor Enable Pull-up Resistor NOTE: A pull-up resistor of port 5 is automatically disabled only when the corresponding pin is selected as push-pull output or alternative function. Figure 9-23. Port 5 Pull-up Resistor Enable Register (P5PUR) Port 5 Interrupt Control Register (P5INT) EBH, Set 1, Bank 1, R/W INT11 INT10 INT9 INT8 P5INT bit-pair pin configuration settings: Disable interrupt Enable interrupt by falling edge Figure 9-24. Port 5 High-Byte Interrupt Control Register (P5INT) 248

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Port 5 Interrupt Pending Register (P5PND) FCH, Set 1, Bank 1, R/W PND11 PND10 PND9 PND8 Not used for the S3F82NB P5PND bit configuration settings: Interrupt request is not pending, pending bit clear when write 0 Interrupt request is pending Figure 9-25. Port 5 Interrupt Pending Register (P5PND) 249

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 6 Port 6 is a 3-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location F6H in set 1, bank 0. P6.0–P6.2 can serve as inputs (with or without pull- ups), as push-pull outputs. And you can configure the following alternative functions: — Pins (P6.0-P6.2): CIN0, CIN1, CIN2 Port 6 Control Register (P6CON) Port 6 has one 8-bit control register: P6CON for P6.0–P6.2. A reset clears the P6CON register to “00H”, configuring all pins to input mode. You use control registers settings to select input (with or without pull-ups) or push-pull output mode and enable the alternative functions. When programming the port, please remember that any alternative peripheral I/O function you configure using the port 6 control register must also be enabled in the associated peripheral module. Port 6 Control Register (P6CON) D2H, Set 1, Bank 0, R/W P6.2/CIN2 P6.1/CIN1 P6.0/CIN0 P6CON bit-pair pin configuration settings: Schmitt trigger input mode Schmitt trigger input mode, pull-up Output mode, Push-pull Alternative function (CIN0-CIN2) Not used for the S3F82NB Figure 9-26. Port 6 Control Register (P6CON) 250

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 7, 8 Port 7 and Port 8 are 8-bit I/O port with nibble configurable pins, respectively. Port 7 and 8 pins are accessed directly by writing or reading the port 7 and 8 data registers, P7 at location F7H and P8 at location F8H in set 1, can serve as segment pins for LCD also. Port Group 1 Control Register (PG1CON) reset clears the PG1CON register to “00H”, configuring all pins to input mode. Port Group 1 Control Register (PG1CON) D1H, Set 1, Bank 0, R/W P7.0-P7.3 /SEG48-SEG51 PG1CON bit-pair pin configuration settings: Input mode Input mode, pull-up Output mode, Push-pull Alternative function (SEG40-SEG55) P8.4-P8.7 /SEG44-SEG47 P8.0-P8.3 /SEG40-SEG43 P7.4-P7.7 /SEG52-SEG55 Figure 9-27. Port Group 1 Control Register (PG1CON) 251

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PORT 9, 10 Port 9 and Port 10 are 8-bit I/O port with nibble configurable pins, respectively. Port 9 and 10 pins are accessed directly by writing or reading the port 9 and 10 data registers, P9 at location F9H and P10 at location FAH in set 1, can serve as segment pins for LCD also. Port Group 0 Control Register (PG0CON) reset clears the PG0CON register to “00H”, configuring all pins to input mode. Port Group 0 Control Register (PG0CON) D0H, Set 1, Bank 0, R/W P9.0-P9.3 /SEG32-SEG35 PG0CON bit-pair pin configuration settings: Input mode Input mode, pull-up Output mode, Push-pull Alternative function (SEG24-SEG39) P10.4-P10.7 /SEG28-SEG31 P10.0-P10.3 /SEG24-SEG27 P9.4-P9.7 /SEG36-SEG39 Figure 9-28. Port Group 0 Control Register (PG0CON) 252

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

10 BASIC TIMER

S3F82NB has an 8-bit basic timer. BASIC TIMER (BT) You can use the basic timer (BT) in two different ways: — As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction. — To signal the end of the required oscillation stabilization interval after a reset or a Stop mode release. The functional components of the basic timer block are: — Clock frequency divider (f xx divided by 4096, 1024, 128, or 16) with multiplexer — 8-bit basic timer counter, BTCNT (set 1, Bank 0, FDH, read-only) — Basic timer control register, BTCON (set 1, D3H, read/write) 253

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BASIC TIMER CONTROL REGISTER (BTCON) The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in set 1, address D3H, and is read/write addressable using Register addressing mode. A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of f xx/4096. To disable the watchdog function, you must write the signature code "1010B" to the basic timer register control bits BTCON.7–BTCON.4. The 8-bit basic timer counter, BTCNT (set 1, bank 0, FDH), can be cleared at any time during the normal operation by writing a "1" to BTCON.1. To clear the frequency dividers, write a "1" to BTCON.0. Basic TImer Control Register (BTCON) D3H, Set 1, R/W Divider clear bit: 0 = No effect 1= Clear dvider Basic timer counter clear bit: 0 = No effect 1= Clear BTCNT Basic timer input clock selection bits: 00 = f XX/4096 01 = fXX/1024 10 = fXX/128 11 = fXX/16 Watchdog timer enable bits: 1010B = Disable watchdog function Other value = Enable watchdog function Figure 10-1. Basic Timer Control Register (BTCON) 254

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7–BTCON.4 to any value other than "1010B". (The "1010B" value disables the watchdog function.) A reset clears BTCON to "00H", automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock. A reset is generated whenever the basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring, To do this, the BTCNT value must be cleared (by writing a “1” to BTCON.1) at regular intervals. If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during the normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically. Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval after a reset or when stop mode has been released by an external interrupt. In stop mode, whenever a reset or an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an external interrupt). When BTCNT.4 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume the normal operation. In summary, the following events occur when stop mode is released: 1. During the stop mode, a power-on reset or an external interrupt occurs to trigger the Stop mode release and oscillation starts. 2. If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source. 3. Clock oscillation stabilization interval begins and continues until bit 4 of the basic timer counter overflows. 4. When a BTCNT.4 overflow occurs, the normal CPU operation resumes. 255

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows). MUX fXX/4096 DIV fXX/1024 fXX/128 fXX/16 fXX Bits 3, 2 Bit 0 Basic Timer Control Register (Write '1010xxxxB' to Disable) Clear Bit 1 RESET or STOP Data Bus 8-Bit Up Counter (BTCNT, Read-Only) Start the CPU (NOTE) OVF RESET R Figure 10-2. Basic Timer Block Diagram 256

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification 11 8-BIT TIMER 0 8-BIT TIMER 0 OVERVIEW The 8-bit timer 0 is an 8-bit general-purpose timer/counter. Timer 0 has three operating modes, one of which you select using the appropriate T0CON setting: — Interval timer mode (Toggle output at T0OUT pin) — Capture input mode with a rising or falling edge trigger at the T0CAP pin — PWM mode (T0PWM) Timer 0 has the following functional components: — Clock frequency divider (fxx divided by 1024, 256, 64, 8 or 1) with multiplexer — External clock input pin (T0CLK) — 8-bit counter (T0CNT), 8-bit comparator, and 8-bit reference data register (T0DATA) — I/O pins for capture input (T0CAP) or PWM or match output (T0PWM, T0OUT) — Timer 0 overflow interrupt (IRQ0 vector DCH) and match/capture interrupt (IRQ0 vector DAH) generation — Timer 0 control register, T0CON (set 1, Bank 0, E5H, read/write) 257

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER 0 CONTROL REGISTER (T0CON) You use the timer 0 control register, T0CON, to — Select the timer 0 operating mode (interval timer, capture mode, or PWM mode) — Select the timer 0 input clock frequency — Clear the timer 0 counter, T0CNT — Enable the timer 0 counting operation T0CON is located in set 1, Bank 0 at address E5H, and is read/write addressable using Register addressing mode. A reset clears T0CON to '00H'. This sets timer 0 to normal interval timer mode, selects an input clock frequency of fxx/1024, and disable counting operation. You can clear the timer 0 counter at any time during normal operation by writing a "1" to T0CON.2. TIMER INTERRUPT CONTROL REGISTER (TINTCON) You use the timer interrupt control register, TINTCON, to — Enable the timer 0 overflow interrupt or timer 0 match/capture interrupt TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode. The timer 0 overflow interrupt (T0OVF) is interrupt level IRQ0 and has the vector address DCH. When a timer 0 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware or must be cleared by software. To enable the timer 0 match/capture interrupt (IRQ0, vector DAH), you must write TINTCON.1 to "1". To detect a match/capture interrupt pending condition, the application program polls TINTPND.1. When a "1" is detected, a timer 0 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 0 match/capture interrupt pending bit, TINTPND.1. 258

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer 0 Control Register (T0CON) E5H, Set 1, Bank 0, R/W Timer 0 counter operating enable bit: 0 = DIsable counting operating 1 = Enable counting operating Not used for the S3F82NB Timer 0 counter clear bit: 0 = No effect 1 = Clear the timer 0 counter (when write) Timer 0 clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx/1 101 = External clock (T0CLK) falling edge 110 = External clock (T0CLK) rising edge 111 = Not available Timer 0 operating mode selection bits: 00 = Interval mode (T0OUT) 01 = Capture mode (capture on rising edge, Counter running, OVF can occur) 10 = Capture mode (Capture on falling edge, Counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Figure 11-1. Timer 0 Control Register (T0CON) Timer Interrupt Control Register (TINTCON) EDH, Set 1, Bank 0, R/W B Timer 0 overflow interuptNot used for the S3F82NB TINTCON bit configuration settings: Timer 0 match/capture interupt Timer 1/A overflow interupt Timer 1/A match/capture interupt Timer B match interupt Figure 11-2. Timer Interrupt Control Register (TINTCON) 259

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer Interrupt Pending Register (TINTPND) ECH, Set 1, Bank 0, R/W Timer 0 overflow interupt pending bitNot used for the S3F82NB 0 = Interrupt request is not pending, pending bit clear when write "0" 1 = Interrupt request is pending Timer 0 match/capture interupt pending bit Timer 1/A overflow interupt pending bit Timer 1/A match/capture interupt pending bit Timer B match interupt pending bit Figure 11-3. Timer Interrupt Pending Register (TINTPND) 260

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER 0 FUNCTION DESCRIPTION Timer 0 Interrupts (IRQ0, Vectors DAH and DCH) The timer 0 can generate two interrupts: the timer 0 overflow interrupt (T0OVF), and the timer 0 match/capture interrupt (T0INT). T0OVF is interrupt level IRQ0, vector DCH. T0INT also belongs to interrupt level IRQ0, but is assigned the separate vector address, DAH. A timer 0 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a “0” to the TINTPND.0 interrupt pending bit. However, the timer 0 match/capture interrupt pending condition must be cleared by the application’s interrupt service routine by writing a "0" to the TINTPND.1 interrupt pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 reference data register, T0DATA. The match signal generates a timer 0 match interrupt (T0INT, vector DAH) and clears the counter. If, for example, you write the value "10H" to T0DATA, the counter will increment until it reaches “10H”. At this point, the timer 0 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 0 output pin is inverted (see Figure 11-4). Match Signal M U X 8-Bit Up Counter Timer 0 Buffer Register 8-Bit Comparator Timer 0 Data Register T0CON.2 T0CON.4-.3 TINTPND.1 Capture Signal TINTCON.1 T0INT (IRQ0) T0OUT Pending Interrupt Enable/Disable Match R (Clear) CLK (Match INT) T0OVF Figure 11-4. Simplified Timer 0 Function Diagram: Interval Timer Mode 261

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T0PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 0 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer 0 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T0PWM pin is held to Low level as long as the reference data value is less than or equal to ( /g100 ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t CLK /g117 256 (see Figure 11-5). Match Signal M U X 8-Bit Up Counter Timer 0 Buffer Register 8-Bit Comparator Timer 0 Data Register T0CON.2 T0CON.4-.3 TINTPND.1 Capture Signal TINTCON.1 T0INT (IRQ0) T0PWM Output (P0.3) Pending Interrupt Enable/Disable Match T0OVF(IRQ0) CLK T0OVF High level when data > counter, Lower level when data < counter (Match INT) TINTPND.0 TINTCON.0 (Overflow INT) Figure 11-5. Simplified Timer 0 Function Diagram: PWM Mode 262

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Capture Mode In capture mode, a signal edge that is detected at the T0CAP pin opens a gate and loads the current counter value into the timer 0 data register. You can select rising or falling edges to trigger this operation. Timer 0 also gives you capture input source: the signal edge at the T0CAP pin. You select the capture input by setting the values of the timer 0 capture input selection bits in the port 0 control register, P0CONL.7–.6, (set 1, bank 1, E1H). When P0CONL.7–.6 is "00" the T0CAP input is selected. Both kinds of timer 0 interrupts can be used in capture mode: the timer 0 overflow interrupt is generated whenever a counter overflow occurs; the timer 0 match/capture interrupt is generated whenever the counter value is loaded into the timer 0 data register. By reading the captured data value in T0DATA, and assuming a specific value for the timer 0 clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T0CAP pin (see Figure 11-6). M U X T0CON.4-.3 TINTPND.1 TINTCON.1 T0INT (IRQ0) Pending Interrupt Enable/Disable Match Signal 8-Bit Up Counter Timer 0 Data Register CLK T0CON.4-.3 T0CAP (Capture INT) T0OVF(IRQ0) TINTPND.0 TINTCON.0 (Overflow INT) Figure 11-6. Simplified Timer 0 Function Diagram: Capture Mode 263

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BLOCK DIAGRAM Timer 0 Data Register Timer 0 Buffer Register 8-bit Comparator 8-bit Up-Counter (Read Only) Clear Match T0CON.7-.5 fXX/1024 fXX/64 fXX/8 T0CLK TINTCON.0 T0CON.2 M U X T0OVF M U X T0INT TINTCON.1 T0OUT T0PWM TINTPND.1 T0CON.4-.3 Data Bus Data Bus fXX/256 fXX/1 M U XT0CAP T0CON.4-.3 TINTPND.0OVF (IRQ0) Match Signal T0CON.2 T0OVF (IRQ0) R T0CON.1 Figure 11-7. Timer 0 Functional Block Diagram 264

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

12 TIMER 1

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. When TACON.0 is set to "1", it is in one 16- bit timer mode. When TACON.0 is set to "0", the timer 1 is used as two 8-bit timers. — One 16-bit timer mode (Timer 1) — Two 8-bit timers mode (Timer A and B) ONE 16-BIT TIMERS MODE (TIMER 1) OVERVIEW The 16-bit timer 1 is a 16-bit general-purpose timer. Timer 1 has three operating modes, one of which you select using the appropriate TACON setting: — Interval timer mode (Toggle output at T1OUT pin) — Capture input mode with a rising or falling edge trigger at the T1CAP pin — PWM mode (T1PWM) Timer 1 has the following functional components: — Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer — External clock input pin (T1CLK) — 16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA) — I/O pins for capture input (T1CAP) or PWM or match output (T1PWM, T1OUT) — Timer 1 overflow interrupt (IRQ1 vector E0H) and match/capture interrupt (IRQ1 vector DEH) generation — Timer 1 control register, TACON (set 1, bank 0, EBH, read/write) 265

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER 1 CONTROL REGISTER (TACON) You use the timer 1 control register, TACON, to — Enable the timer 1 operating (interval timer, capture mode, or PWM mode) — Select the timer 1 input clock frequency — Clear the timer 1 counter, TACNT and TBCNT — Enable the timer 1 counting operating TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/1024, and disable counting operation. You can clear the timer 1 counter at any time during the normal operation by writing a "1" to TACON.2. TIMER INTERRUPT CONTROL REGISTER (TINTCON) You use the timer interrupt control register, TINTCON, to — Enable the timer 1/A overflow interrupt or timer 1/A match/capture interrupt TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode. The timer 1 overflow interrupt (T1OVF) is interrupt level IRQ1 and has the vector address E0H. When a timer 1 overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware or must be cleared by software. To enable the timer 1 match/capture interrupt (IRQ1, vector DEH), you must write TACON.0 to "1", TACON.1 and TINTCON.3 to "1". To detect a match/capture interrupt pending condition, the application program polls TINTPND.3. When a "1" is detected, a timer 1 match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 match/capture interrupt pending bit, TINTPND.3. 266

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer 1 Control Register (TACON) EBH, Set 1, Bank 0, R/W Timer 1 counter operating enable bit: 0 = DIsable counting operating 1 = Enable counting operating Timer 1 counter clear bit: 0 = No effect 1 = Clear the timer 1 counter (when write) Timer 1 clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx/1 101 = External clock (T1CLK) falling edge 110 = External clock (T1CLK) rising edge 111 = Not available Timer 1 operating mode selection bits: 00 = Interval mode (T1OUT) 01 = Capture mode (capture on rising edge, Counter running, OVF can occur) 10 = Capture mode (Capture on falling edge, Counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Timer 1 operating enable bit: 0 = Two 8-bit timer mode (Timer A/B) 1 = One 16-bit timer mdoe (Timer 1) Figure 12-1. Timer 1 Control Register (TACON) 267

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer Interrupt Control Register (TINTCON) EDH, Set 1, Bank 0, R/W Timer 0 overflow interuptNot used for the S3F82NB TINTCON bit configuration settings: Timer 0 match/capture interupt Timer 1/A overflow interupt Timer 1/A match/capture interupt Timer B match interupt Figure 12-2. Timer Interrupt Control Register (TINTCON) Timer Interrupt Pending Register (TINTPND) ECH, Set 1, Bank 0, R/W Timer 0 overflow interupt pending bitNot used for the S3F82NB 0 = Interrupt request is not pending, pending bit clear when write "0" 1 = Interrupt request is pending Timer 0 match/capture interupt pending bit Timer 1/A overflow interupt pending bit Timer 1/A match/capture interupt pending bit Timer B match interupt pending bit Figure 12-3. Timer Interrupt Pending Register (TINTPND) 268

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER 1 FUNCTION DESCRIPTION Timer 1 Interrupts (IRQ1, Vectors DEH and E0H) The timer 1 can generate two interrupts: the timer 1 overflow interrupt (T1OVF), and the timer 1 match/ capture interrupt (T1INT). T1OVF is belongs to interrupt level IRQ1, vector E0H. T1INT also belongs to interrupt level IRQ1, but is assigned the separate vector address, DEH. A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced or should be cleared by software in the interrupt service routine by writing a “0” to the TINTPND.2 interrupt pending bit. However, the timer 1 match/capture interrupt pending condition must be cleared by the application’s interrupt service routine by writing a "0" to the TINTPND.3 interrupt pending bit. Interval Timer Mode In interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 reference data register, TBDATA/TADATA. The match signal generates a timer 1 match interrupt (T1INT, vector DEH) and clears the counter. If, for example, you write the value "1087H" to TBDATA/TADATA, the counter will increment until it reaches “1087H”. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes. With each match, the level of the signal at the timer 1 output pin is inverted (see Figure 12-4). Match Signal M U X 16-Bit Up Counter Timer 1 Buffer Register 16-Bit Comparator Timer 1 Data Register TACON.2 TACON.4-.3 TINTPND.3 Capture Signal TINTCON.3 T1INT (IRQ1) T1OUT Pending Interrupt Enable/Disable Match R (Clear) CLK (Match INT) T1OVF Figure 12-4. Simplified Timer 1 Function Diagram: Interval Timer Mode 269

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer 1 data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFFFH", and then continues incrementing from "0000H". Although you can use the match signal to generate a timer 1 overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data value is less than or equal to ( /g100 ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t CLK /g117 65536 (see Figure 12-5). Match Signal M U X 16-Bit Up Counter Timer 1 Buffer Register 16-Bit Comparator Timer 1 Data Register TACON.2 TACON.4-.3 TINTPND.3 Capture Signal TINTCON.3 T1INT (IRQ1) T1PWM Pending Interrupt Enable/Disable Match T1OVF(IRQ1) CLK T1OVF High level when data > counter, Lower level when data < counter (Match INT) TINTPND.2 TINTCON.2 (Overflow INT) Figure 12-5. Simplified Timer 1 Function Diagram: PWM Mode 270

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER 1 BLOCK DIAGRAM Timer 1 Data Register (TBDATA/TADATA) Timer 1 Buffer Register (16-Bit) 16-bit Comparator 16-bit Up-Counter (Read Only) (TBCNT/TACNT) Clear Match TACON.7-.5 fXX/1024 fXX/64 fXX/8 T1CLK TINTCON.2 TACON.2 M U X T1OVF M U X T1INT TINTCON.3 T1OUT T1PWM TINTPND.3 TACON.4-.3 Data Bus Data Bus fXX/256 fXX/1 M U XT1CAP TACON.4-.3 TINTPND.2OVF (IRQ1) Match Signal TACON.2 T1OVF (IRQ1) R Pending Pending NOTE: When TACON.0 is "1", 16-bit timer 1. TACON.1 Figure 12-7. Timer 1 Functional Block Diagram 272

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TWO 8-BIT TIMERS MODE (TIMER A and B) OVERVIEW The 8-bit timer A is an 8-bit general-purpose timer. Timer A has three operating modes, one of which you select using the appropriate TACON setting: — Interval timer mode (Toggle output at T1OUT pin) — Capture input mode with a rising or falling edge trigger at the T1CAP pin — PWM mode (T1PWM) Timer A has the following functional components: — Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer — External clock input pin (T1CLK) — 8-bit counter (TACNT), 8-bit comparator, and 8-bit reference data register (TADATA) — I/O pins for capture input (T1CAP) or PWM or match output (T1PWM, T1OUT) — Timer A overflow interrupt (IRQ1 vector E0H) and match/capture interrupt (IRQ1 vector DEH) generation — Timer A control register, TACON (set 1, bank 0, EBH, read/write) The 8-bit timer B is an 8-bit general-purpose timer. Timer B includes interval timer mode using appropriate TBCON setting. Timer B has the following functional components: — Clock frequency divider (fxx divided by 1024, 256, 64, 8, or 1) with multiplexer — 8-bit counter (TBCNT), 8-bit comparator, and 8-bit reference data register (TBDATA) — Timer B match interrupt (IRQ2, vector E2H) generation — Timer B control register, TBCON (set 1, bank 0, EAH, read/write) 273

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER A CONTROL REGISTER (TACON) You use the timer A control register, TACON, to — Enable the timer A (interval timer, capture mode, or PWM mode) — Select the timer A input clock frequency — Clear the timer A counter, TACNT — Select the timer A counting operation TACON is located in set 1, bank 0, at address EBH, and is read/write addressable using register addressing mode. A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables counting operation. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.2. TIMER INTERRUPT CONTROL REGISTER (TINTCON) You use the timer interrupt control register, TINTCON, to — Enable the timer 1/A overflow interrupt or timer 1/A match/capture interrupt TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode. The timer A overflow interrupt (T1OVF) is interrupt level IRQ1 and has the vector address E0H. When a timer A overflow interrupt occurs and is serviced by the CPU, the pending condition is cleared automatically by hardware or must be cleared by software. To enable the timer A match/capture interrupt (IRQ1, vector DEH), you must write TACON.0 to "0", TACON.1 and TINTCON.3 to "1". To detect a match/capture interrupt pending condition, the application program polls TINTPND.3. When a "1" is detected, a timer A match or capture interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A match/capture interrupt pending bit, TINTPND.3. 274

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer A Control Register (TACON) EBH, Set 1, Bank 0, R/W Timer A counter operating enable bit: 0 = DIsable counting operating 1 = Enable counting operating Timer A counter clear bit: 0 = No effect 1 = Clear the timer A counter (when write) Timer A clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx/1 101 = External clock (T1CLK) falling edge 110 = External clock (T1CLK) rising edge 111 = Not available Timer A operating mode selection bits: 00 = Interval mode (T1OUT) 01 = Capture mode (capture on rising edge, Counter running, OVF can occur) 10 = Capture mode (Capture on falling edge, Counter running, OVF can occur) 11 = PWM mode (OVF and match interrupt can occur) Timer A operating enable bit: 0 = Two 8-bit timer mode (Timer A/B) 1 = One 16-bit timer mdoe (Timer 1) Figure 12-8. Timer A Control Register (TACON) Timer Interrupt Control Register (TINTCON) EDH, Set 1, Bank 0, R/W Timer 0 overflow interuptNot used for the S3F82NB TINTCON bit configuration settings: Timer 0 match/capture interupt Timer 1/A overflow interupt Timer 1/A match/capture interupt Timer B match interupt Figure 12-9. Timer Interrupt Control Register (TINTCON) 275

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer Interrupt Pending Register (TINTPND) ECH, Set 1, Bank 0, R/W Timer 0 overflow interupt pending bitNot used for the S3F82NB 0 = Interrupt request is not pending, pending bit clear when write "0" 1 = Interrupt request is pending Timer 0 match/capture interupt pending bit Timer 1/A overflow interupt pending bit Timer 1/A match/capture interupt pending bit Timer B match interupt pending bit Figure 12-10. Timer Interrupt Pending Register (TINTPND) 276

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Pulse Width Modulation Mode Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the T1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the value written to the timer A data register. In PWM mode, however, the match signal does not clear the counter. Instead, it runs continuously, overflowing at "FFH", and then continues incrementing from "00H". Although you can use the match signal to generate a timer A overflow interrupt, interrupts are not typically used in PWM-type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data value is less than or equal to ( /g100 ) the counter value and then the pulse is held to High level for as long as the data value is greater than ( > ) the counter value. One pulse width is equal to t CLK /g117 256 (see Figure 12-12). Match Signal M U X 8-Bit Up Counter Timer A Buffer Register 8-Bit Comparator Timer A Data Register TACON.2 TACON.4-.3 TINTPND.3 Capture Signal TINTCON.3 TAINT (IRQ1) T1PWM Pending Interrupt Enable/Disable Match TAOVF(IRQ1) CLK TAOVF High level when data > counter, Lower level when data < counter (Match INT) TINTPND.2 TINTCON.2 (Overflow INT) Figure 12-12. Simplified Timer A Function Diagram: PWM Mode 278

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Capture Mode In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter value into the timer A data register. You can select rising or falling edges to trigger this operation. Timer A also gives you capture input source: the signal edge at the T1CAP pin. You select the capture input by setting the values of the timer A capture input selection bits in the port 0 control register, P0CONL.5–.4, (set 1, bank 1, E1H). When P0CONL.5–.4 is "00" the T1CAP input is selected. Both kinds of timer A interrupts can be used in capture mode: the timer A overflow interrupt is generated whenever a counter overflow occurs; the timer A match/capture interrupt is generated whenever the counter value is loaded into the timer A data register. By reading the captured data value in TADATA, and assuming a specific value for the timer A clock frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin (see Figure 12-13). M U X TACON.4-.3 TINTPND.3 TINTCON.3 TAINT (IRQ1) Pending Interrupt Enable/Disable Match Signal 8-Bit Up Counter Timer A Data Register CLK TACON.4-.3 T1CAP (Capture INT) TAOVF(IRQ1) TINTPND.2 TINTCON.2 (Overflow INT) Figure 12-13. Simplified Timer A Function Diagram: Capture Mode 279

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER A BLOCK DIAGRAM Timer A Data Register (TADATA) Timer A Buffer Register 8-bit Comparator 8-bit Up-Counter (Read Only) (TACNT) Clear Match TACON.7-.5 fXX/1024 fXX/64 fXX/8 T1CLK TINTCON.2 TACON.2 M U X TAOVF M U X TAINT TINTCON.3 T1OUT T1PWM TINTPND.3 TACON.4-.3 Data Bus Data Bus fXX/256 fXX/1 M U XT1CAP TACON.4-.3 TINTPND.2OVF (IRQ1) Match Signal TACON.2 TAOVF (IRQ1) R Pending Pending NOTE: When TACON.0 is "0", two 8-bit timer A/B. TACON.1 Figure 12-14. Timer A Functional Block Diagram 280

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER B CONTROL REGISTER (TBCON) You use the timer B control register, TBCON, to — Enable the timer B operating (interval timer) — Select the timer B input clock frequency — Clear the timer B counter, TBCNT — Select the timer B counting operation TBCON are located in set 1, bank 0, at address EAH, and is read/write addressable using register addressing mode. A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of fxx/1024, and disables counting operation. You can clear the timer B counter at any time during normal operation by writing a "1" to TBCON.2. TIMER INTERRUPT CONTROL REGISTER (TINTCON) You use the timer interrupt control register, TINTCON, to — Enable the timer B match interrupt TINTCON is located in set 1, Bank 0 at address EDH, and is read/write addressable using Register addressing mode. To enable the timer B match interrupt (IRQ2, vector E2H), you must write TACON.0 to "0", TBCON.1 and TINTCON.4 to "1". To detect a match interrupt pending condition, the application program polls TINTPND.4. When a "1" is detected, a timer B match interrupt is pending. When the interrupt request has been serviced, the pending condition must be cleared by software by writing a "0" to the timer B match interrupt pending bit, TINTPND.4. TIMER B FUNCTION DESCRIPTION Interval Timer Function The timer B module can generate an interrupt: the timer B match interrupt (TBINT). TBINT belongs to the interrupt level IRQ2 and is assigned a separate vector address, E2H. The TBINT pending condition should be cleared by software after they are serviced. In interval timer mode, a match signal is generated when the counter value is identical to the values written to the TB reference data registers, TBDATA. The match signal generates corresponding match interrupt (TBINT, vector E2H) and clears the counter. If, for example, you write the value 10H to TBDATA, "0" to TACON.0, and 06H to TBCON, the counter will increment until it reaches 10H. At this point, the TB interrupt request is generated, the counter value is reset, and counting resumes. 281

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer B Control Register (TBCON) EAH, Set 1, Bank 0, R/W Timer B counter operating enable bit: 0 = DIsable counting operating 1 = Enable counting operating Timer B counter clear bit: 0 = No effect 1 = Clear the timer B counter (when write) Timer B clock selection bits: 000 = fxx/1024 001 = fxx/256 010 = fxx/64 011 = fxx/8 100 = fxx/1 Others = Not available Not used for the S3F82NB Not used for the S3F82NB Figure 12-15. Timer B Control Register (TBCON) Timer Interrupt Control Register (TINTCON) EDH, Set 1, Bank 0, R/W Timer 0 overflow interuptNot used for the S3F82NB TINTCON bit configuration settings: Timer 0 match/capture interupt Timer 1/A overflow interupt Timer 1/A match/capture interupt Timer B match interupt Figure 12-16. Timer Interrupt Control Register (TINTCON) 282

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Timer Interrupt Pending Register (TINTPND) ECH, Set 1, Bank 0, R/W Timer 0 overflow interupt pending bitNot used for the S3F82NB 0 = Interrupt request is not pending, pending bit clear when write "0" 1 = Interrupt request is pending Timer 0 match/capture interupt pending bit Timer 1/A overflow interupt pending bit Timer 1/A match/capture interupt pending bit Timer B match interupt pending bit Figure 12-17. Timer Interrupt Pending Register (TINTPND) 283

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TIMER B BLOCK DIAGRAM TBCON.7-.5 TINTPND.4 TINTCON.4 TBINT Timer B Buffer Register 8-Bit Comparator Timer B Data Register (Read-Only) (TBDATA) 8-Bit Up Counter (Read-Only) (TBCNT) R Data BUS Data BUS Match MUX fxx/1024 fxx/256 fxx/64 fxx/8 fxx/1 Clear Pending TBCON.1 TBCON.2 (IRQ2) Match signal TBCON.2 NOTE: When TACON.0 is "0", two 8-bit timer A/B. Figure 12-18. Timer B Function Block Diagram 284

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

13 WATCH TIMER

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1". And if you want to service watch timer overflow interrupt (IRQ4, vector E6H), then set the WTCON.6 to “1”. The watch timer overflow interrupt pending condition (WTCON.0) must be cleared by software in the application’s interrupt service routine by means of writing a "0" to the WTCON.0 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (WTCON.0) is automatically set to "1", and interrupt requests commence in 3.91 ms, 0.125, 0.25 and 0.5-second intervals by setting Watch timer speed selection bits (WTCON.3–.2). The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences. The watch timer supplies the clock frequency for the LCD controller (f LCD). Therefore, if the watch timer is disabled, the LCD controller does not operate. Watch timer has the following functional components: — Real Time and Watch-Time Measurement — Using a Main Clock Source or Sub clock — Clock Source Generation for LCD Controller (f LCD) — I/O pin for Buzzer Output Frequency Generator (BUZ) — Timing Tests in High-Speed Mode — Watch timer overflow interrupt (IRQ4, vector E6H) generation — Watch timer control register, WTCON (set 1, bank 0, EEH, read/write) 285

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification WATCH TIMER CONTROL REGISTER (WTCON) The watch timer control register, WTCON is used to select the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in set 1, bank 0 at address EEH, and is read/write addressable using register addressing mode. A reset clears WTCON to "00H". This disable the watch timer. So, if you want to use the watch timer, you must write appropriate value to WTCON. Buzzer signal selection bits: 00 = 0.5 kHz 01 = 1 kHz 10 = 2 kHz 11 = 4 kHz Watch Timer Control Register (WTCON) EEH, Set 1, Bank 0, R/W Watch timer INT Enable/Disable bit: 0 = Disable watch timer INT 1 = Enable watch timer INT Watch timer interrupt pending bit: 0 = Interrupt request is not pending (Clear pending bit when write"0") 1 = Interrupt request is pending Watch timer speed selection bits: 00 = Set watch timer interrupt to 0.5 s 01 = Set watch timer interrupt to 0.25 s 10 = Set watch timer interrupt to 0.125 s 11 = Set watch timer interrupt to 3.91 ms Watch timer clock selection bit: 0 = Select main clock divided by 27 (fx/128) 1 = Select sub clock (fxt) Watch timer Enable/Disable bit: 0 = Disable watch timer (Clear frequency dividing circuits) 1 = Enable watch timer Figure 13-1. Watch Timer Control Register (WTCON) 286

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification WATCH TIMER CIRCUIT DIAGRAM WT INT Enable WTCON.1 WTCON.2 WTCON.3 WTCON.4 WTCON.5 WTCON.6 Enable/Disable Selector Circuit MUX WTCON.0 WTINT WTCON.6 3.91msec 0.125sec 0.25sec 0.5sec fw/64 (0.5 kHz) fw/32 (1 kHz) fw/16 (2 kHz) fw/8 (4 kHz) fx = Main clock (where fx = 4.19 MHz) fxt = Sub clock (32.768 kHz) fw = Watch timer frequency Clock Selector Frequency Dividing Circuit fw 32.768 kHz fxt fx/128 fLCD = 4096 Hz WTCON.7 WTCON.0 (Pending Bit) BUZ (IRQ4) Figure 13-2. Watch Timer Circuit Diagram 287

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

14 LCD CONTROLLER/DRIVER

The S3F82NB microcontroller can directly drive an up-to-1280-dot (80 segments x 16 commons) LCD panel. Its LCD block has the following components: — LCD controller/driver — Display RAM (F00H–FAFH) for storing display data in page 15 — 8 common/segment output pins (COM8/SEG0–COM15/SEG7) — 80 segment output pins (SEG8–SEG87) — 8 common output pins (COM0–COM7) — Five LCD operating power supply pins (V LC0–VLC4) — V LC0 pin for controlling the driver and bias voltage — LCD contrast control circuit by software (16 steps) The LCD control register, LCON, is used to turn the LCD display on and off, select frame frequency, LCD duty and bias. The LCD mode control register, LMOD, is used to control LCD bias voltage by 16 steps. Data written to the LCD display RAM can be automatically transferred to the segment signal pins without any program control. When a subsystem clock is selected as the LCD clock source, the LCD display is enabled even in the main clock stop or idle modes. LCD Controller/Driver 8-Bit Data Bus COM0-COM7 COM8-COM15 /SEG0-SEG7 SEG8-SEG87 VLC0-VLC4 Figure 14-1. LCD Function Diagram 288

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCD CIRCUIT DIAGRAM COM0 COM15/SEG7 COM8/SEG0 COM7 VLC1 VLC0 VLC2 Data Bus Port Latch SEG/Port Driver Timing Controller LCD Voltage Control fLCD LCON COM/Port Driver LCD Display RAM (F00H-FAFH) SEG23 SEG8 VLC3 LMOD SEG32/P9.0 SEG24/P10.0 SEG40/P8.0 SEG48/P7.0 SEG56/P2.0 SEG64/P3.0 SEG72/P4.0 SEG87/P5.7 VLC4 Contrast Controller Figure 14-2. LCD Circuit Diagram 289

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCD RAM ADDRESS AREA RAM addresses of 00H - AFH page 15 are used as LCD data memory. These locations can be addressed by 1- bit or 8-bit instructions. When the bit value of a display segment is "1", the LCD display is turned on; When the bit value is "0", the display is turned off. Display RAM data are sent out through the segment pins, SEG0–SEG87, using the direct memory access (DMA) method that is synchronized with the f LCD signal. RAM addresses in this location that are not used for LCD display can be allocated to general-purpose use. COM0 COM COM1 COM2 COM3 COM4 COM5 COM6 COM7 Bit SEG0 F00H SEG1 F02H SEG2 F04H SEG3 F06H SEG4 F08H SEG5 F0AH SEG85 FAAH SEG86 FACH SEG87 FAEH COM15 COM13 COM12 COM11 COM10 COM9 COM8 COM14 F01H F03H F05H F07H F09H F0BH FABH FADH FAFH Figure 14-3. LCD Display Data RAM Organization 290

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCD CONTROL REGISTER (LCON) A LCON is located in set1, bank0 at address EFH, and is read/write addressable using register addressing mode. It has the following control functions. — LCD duty and bias selection — LCD clock selection — LCD display control The LCON register is used to turn the LCD display on/off, to select duty and bias and select LCD clock. A reset clears the LCON registers to "00H", configuring turns off the LCD display, select 1/8 duty and 1/4 bias and select 256Hz for LCD clock. The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer should be enabled when the LCD display is turned on. NOTE: The clock and duty for LCD controller/driver is automatically initialized by hardware, whenever LCON register data value is re-write. So, the LCON register don’t re-write frequently. LCD Control Register (LCON) EFH, Set 1, Bank 0, R/W Not used for the S3F82NB LCD clock selection bits: LCD output control bit: 0 = Display off 1 = Display on LCD duty selection bit: 0 = 1/8 duty 1 = 1/16 duty LCD bias selection bit: 0 = 1/4 bias 1 = 1/5 bias 000 = fw/2 7 (256 Hz) 001 = fw/26 (512 Hz) 010 = fw/25 (1024 Hz) 011 = fw/24 (2048 Hz) Others = Not available 100 = fw/23 (4096 Hz) Figure 14-4. LCD Control Register (LCON) 291

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCD MODE CONTROL REGISTER (LMOD) A LMOD is located in set 1, bank 0 at address F0H, and is read/write addressable using Register addressing mode. It has the following control functions. — LCD contrast control circuit by software (16 steps) The LMOD register is used to control the LCD contrast up to 16 step contrast level. A reset clears the LMOD registers to "00H", configuring select 1/16 step contrast level and disable LCD contrast control. You can’t control LCD contrast by software when the VLCD voltage is supplied by external voltage source. Only when you use internal VDD for VLCD voltage, you can control LCD contrast by software. LCD Mode Control Register (LMOD) F0H, Set 1, Bank 0, R/W Not used for the S3F82NBLCD contrast level control bits: 0000 = 1/16 step (The dimmest level) 0001 = 2/16 step 0010 = 3/16 step 1111 = 16/16 step (The brightest level) LCD = VDD x (n+17)/32, where n = 0 - 15) LCD contrast enabel/disable selection bit: 0 = Disable LCD contrast control 1 = Enabel LCD contrast control Figure 14-5. LCD Mode Control Register (LMOD) 292

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification LCD VOLTAGE DIVIDING RESISTOR VLC0 LCON.0 VSS 1/5 bias "0" "1" 16 steps of voltage LCON.0 VSS VDD "0" "1" LMOD.3=0 Contrast Controller 16 steps of voltage 1/4 bias VDD LMOD.3=0 VLC4 VLC3 VLC2 VLC1 VLCD VLC0 VLC4 VLC3 VLC2 VLC1 VLCD Contrast Controller Application With Contrast Control VSS "0" "1" VLCD = VDD x (n+17)/32 VDD LCON.0 16 steps of voltage LMOD.3=1 Contrast Controller VLC0 VLC4 VLC3 VLC2 VLC1 VLCD Figure 14-6. LCD Voltage Dividing Resistor Connection 293

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COMMON (COM) SIGNALS The common signal output pin selection (COM pin selection) varies according to the selected duty cycle. — In 1/16 duty mode, COM0-COM15 (SEG8–SEG87) pins are selected. — In 1/8 duty mode, COM0-COM7 (SEG0–SEG87) pins are selected. SEGMENT (SEG) SIGNALS The 88 LCD segment signal pins are connected to corresponding display RAM locations at page 15. Bits of the display RAM are synchronized with the common signal output pins. When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal to the corresponding segment pin. 294

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COM0 SEG8 COM2 COM1

1 Frame

S E G S E G S E G S E G S E G COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 V SS VLC1 VLC2 VLC3 VLC4 VLC0 VSS VLC1 VLC2 VLC3 VLC4 VLC0 VSS VLC1 VLC2 VLC3 VLC4 VLC0 VSS VLC1 VLC2 VLC3 VLC4 VLC0 Figure 14-7. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) 295

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification -VLC2 -VLC1 -VLC0 -VLC4 -VLC3 -VLC2 -VLC1 -VLC0 -VLC4 -VLC3 VLC1 VLC2 VLC3 VLC4 VLC0 VLC1 VLC2 VLC3 VLC4 VLC0 Figure 14-7. LCD Signal Waveforms (1/16 Duty, 1/5 Bias) (Continued) 296

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification S E G S E G S E G S E G S E G COM1 SEG0 COM2 COM0 SEG0-COM0 0 12 3 746 50 12 3 746 5 VLC2 (VLC3) VLC4 VSS VLC0 VLC1 VLC2 (VLC3) VLC4 VSS VLC0 VLC1 VLC2 (VLC3) VLC4 VSS VLC0 VLC1 VLC2 (VLC3) VLC4 VSS VLC0 VLC1 VLC2 (VLC3) VLC0 VLC1 VLC4 -VLC4 -VLC2 (-VLC3) -VLC1 -VLC0 Figure 14-8. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) 297

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification VLC2(VLC3) VLC4 VSS VLC0 VLC1 VLC0 VLC2(VLC3) VLC4 -VLC4 -VLC2(-VLC3) -VLC0 VLC1 -VLC1 Figure 14-8. LCD Signal Waveforms (1/8 Duty, 1/4 Bias) (Continued) 298

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification 15 10-BIT ANALOG-TO-DIGITAL CONVERTER OVERVIEW The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components: — Analog comparator with successive approximation logic — D/A converter logic (resistor string type) — ADC control register (ADCON) — Eight multiplexed analog data input pins (AD0–AD7) — 10-bit A/D conversion data output register (ADDATAH/L) — 8-bit digital input port (Alternately, I/O port) — AV REF and VSS pins FUNCTION DESCRIPTION To initiate an analog-to-digital conversion procedure, at the first you must set ADCEN signal for ADC input enable at port 0, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4–.6 to select one of the eight analog input pins (AD0–7) and set the conversion start or disable bit, ADCON.0. The read-write ADCON register is located in set 1, bank 0 at address E2H. The pins which are not used for ADC can be used for normal I/O. During a normal conversion, ADC logic initially sets the successive approximation register to 200H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.6–.4) in the ADCON register. To start the A/D conversion, you should set the start bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion (EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/L register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/L before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result. NOTE Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0–AD7 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished. 299

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification CONVERSION TIMING The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 8 MHz fxx clock frequency, one clock cycle is 1 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows: 4 clocks/bit /g117 10 bits + set-up time = 50 clocks, 50 clock /g117 1us = 50 /g80s at 1 MHz A/D CONVERTER CONTROL REGISTER (ADCON) The A/D converter control register, ADCON, is located at address E2H in set1, bank 0. It has three functions: — Analog input pin selection (ADCON.6–.4) — End-of-conversion status detection (ADCON.3) — ADC clock selection (ADCON.2–.1) — A/D operation start or disable (ADCON.0) After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0–AD7) can be selected dynamically by manipulating the ADCON.4–6 bits. And the pins not used for analog input can be used for normal I/O function. Start or disable bit: 0 = Disable operation 1 = Start operation A/D Converter Control Register (ADCON) E2H, Set1, Bank 0, R/W (EOC bit is read-only) End-of-conversion bit: 0 = Conversion not complete 1 = Conversion complete Always logic "0" A/D input pin selection bits: 0 0 0 = AD0 0 0 1 = AD1 0 1 0 = AD2 0 1 1 = AD3 1 0 0 = AD4 1 0 1 = AD5 1 1 0 = AD6 1 1 1 = AD7 Clock Selection bit: 0 0 = fxx/16 0 1 = fxx/8 1 0 = fxx/4 1 1 = fxx/1 Figure 15-1. A/D Converter Control Register (ADCON) 300

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification A/D Converter Data Register, High Byte (ADDATAH) E0H, Set 1, Bank 0, Read Only A/D Converter Data Register, Low Byte (ADDATAL) E1H, Set1, Bank 0, Read Only .1 .0MSB LSB Figure 15-2. A/D Converter Data Register (ADDATAH/L) INTERNAL REFERENCE VOLTAGE LEVELS In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range AVSS to AVREF (usually, AVREF /g100 VDD, AVSS /g32 VSS). Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 AV REF. 301

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BLOCK DIAGRAM Input Pins AD0-AD7 (P0.0-P0.7) Clock Selector Conversion Result (ADDATAH/L) Upper 8-bit is loaded to A/D Conversion Data Register To ADCON.3 (EOC Flag) Successive Approximation Logic & Register AVREF AVSS(VSS) Analog Comparator 10-bit D/A Converter M U X ADCON.6-.4 (Select one input pin of the assigned pins) P0CONH/L (Assign Pins to ADC Input) ADCON.0 (AD/C Enable) ADCON.0 (AD/C Enable) ADCON.2-.1 Figure 15-3. A/D Converter Functional Block Diagram 302

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification AVSS(VSS) S3F82NB AD0-AD7 AVREF Reference Voltage Input Analog Input Pin VDD VDD 10 /g80F 103C 101C -(AVREF /g100 VDD) Figure 15-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy 303

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

16 SERIAL I/O INTERFACE

Serial I/O module, SIO can interface with various types of external device that require serial data transfer. The components of each SIO function block are: — 8-bit control register (SIOCON) — Clock selector logic — 8-bit data buffer (SIODATA) — 8-bit pre-scaler (SIOPS) — 3-bit serial clock counter — Serial data I/O pins (SI, SO) — Serial clock input/output pins (SCK) The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source. PROGRAMMING PROCEDURE To program the SIO modules, follow these basic steps: 1. Configure the I/O pins at port (SO, SCK, SI) by loading the appropriate value to the P6CONH register if necessary. 2. Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter. 3. For interrupt generation, set the serial I/O interrupt enable bit (SIOCON.1) to "1". 4. When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts. 5. When the shift operation (transmit/receive) is completed, the SIO pending bit (SIOCON.0) is set to "1" and an SIO interrupt request is generated. 304

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SIO CONTROL REGISTER (SIOCON) The control register for serial I/O interface module, SIOCON, is located at F3H in set 1, bank 0. It has the control settings for SIO module. — Clock source selection (internal or external) for shift clock — Interrupt enable — Edge selection for shift operation — Clear 3-bit counter and start shift operation — Shift operation (transmit) enable — Mode selection (transmit/receive or receive-only) — Data direction selection (MSB first or LSB first) A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first. Serial I/O Module Control Register (SIOCON) F3H, Set 1, Bank 0, R/W SIO interrupt enable bit: 0 = Disable SIO interrupt 1 = Enable SIO interrupt SIO interrupt pending bit: 0 = No interrupt pending 0 = Clear pending condition (when write) 1 = Interrupt is pending SIO shift operation enable bit: 0 = Disable shifter and clock counter 1 = Enable shifter and clock counter Shift clock edge selection bit: 0 = T X at falling edges, Rx at rising edges 1 = TX at rising edges, Rx at falling edges Data direction control bit: 0 = MSB-first mode 1 = LSB-first mode SIO mode selection bit: 0 = Receive only mode 1 = Transmit/receive mode SIO counter clear and shift start bit: 0 = No action 1 = Clear 3-bit counter and start shifting SIO shift clock selection bit: 0 = Internal clock (P.S Clock) 1 = External clock (SCK)Figure 16-1. Serial I/O Module Control Registers (SIOCON) 305

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

17 COMPARATOR

P6.0, P6.1 and P6.2 can be used as an analog input port for a comparator. The reference voltage for the 4-channel comparator can be supplied either internally or externally at P6.2. When an internal reference voltage is used, four channels (P6.0-P6.2) are used for analog inputs and the internal reference voltage is varied in 16 When a conversion is completed, the result is saved in the comparison result register CMPREG. The initial values of the CMPREG are undefined and the comparator operation is disabled by a RESET. The comparator module has the following components: — Comparator — Internal reference voltage generator (4-bit resolution) — External reference voltage source at P6.2 — Comparator mode register (CMPCON) — Comparator result register (CMPREG) 308

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COMPARATOR CONTROL REGISTER (CMPCON) The comparator mode register CMPCON is an 8-bit register that is used to select operation mode of the comparator. It is located in set 1, bank 0 at address F1H, and is read/write addressable using register addressing mode. A reset clears CMPCON to "00H". This disable the comparator, selects conversion time of 8 x 2 5/fx, the P6.0- P6.2 (CIN0-CIN2) can be used analog input. CMPCON.6 bit controls conversion timer while CMPCON.7 bit enables or disables comparator operation to reduce power consumption. Based on the CMPCON.5 bit setting, an internal or an external reference voltage is input for the comparator, as follows: When CMPCON.5 is set to logic “0”: — A reference voltage is selected by the CMPCON.0 to CMPCON.3 bit settings. — P6.0-P6.2 (CIN0-CIN2) are used as analog input pins. — The internal digital to analog converter generates 16 reference voltages. — The comparator can detect 150-mV differences between the reference voltage and the analog input voltages. — Comparator results are written into bit0-bit2 of the comparison result register (CMPREG) When CMPCON.5 is set to logic “1”: — A external reference voltage is supplied from P6.2/CIN2. — P6.0 and P6.1 (CIN0-CIN1) are used as the analog input pins. — The internal digital to analog converter generates 16 reference voltages. — The comparator can detect 150-mV differences between the reference voltage and the analog input voltages. — Bit0 and bit1 in the CMPREG register contain the results. Comparator Control Register F1H, Set 1, Bank 0, R/W Reference Voltage Selection bits: Selected VREF = VDD X (N+0.5)/16, N = 0 to 15 External/Internal reference selection bit: 0 = Internal reference, CIN0-CIN2; analog input 1 = CIN2; External reference, CIN0-CIN1; analog input Comparator enable bit: 0 = Disable comparator 1 = Enable comparator Not used, But you must keep "0" Conversion time selection bit: 0 = 8 X 2 /fx 1 = 8 X 2 /fx Figure 17-1. Comparator Control Register (CMPCON) 309

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BLOCK DIAGRAM P6.0/CIN0 P6.2/CIN2 P6.1/CIN1 MUX MUX Comparison Result Register (CMPREG) VREF (External) CMPCON.7 MUX VDD 1/2R R R CMPCON.6 CMPCON.5 CMPCON.3 CMPCON.2 CMPCON.1 CMPCON.0 VREF (Internal) 1/2R NOTE: The comparison result of CIN0, CIN1 and CIN2 are respectively stored in CMPREG.0, CMPREG.1 and CMPREG.2. Figure 17-2. Comparator Circuit Diagram 310

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification COMPARATOR OPERATION The comparator compares analog voltage input at CIN0-CIN2 with an external or internal reference voltage (VREF) that is selected by the CMPCON register. The result is written to the comparison result register CMPREG at address F2H, set 1, bank 0. The comparison result at internal reference is calculated as follows: If “1” Analog input voltage ˻ VREF + 150mV If “0” Analog input voltage ˺ VREF - 150mV To obtain a comparison result, the data must be read out from the CMPREG register after VREF is updated by changing the CMPCON value after a conversion time has elapsed. Comparsion Time (CMPCLK x8) Analog Input Voltage (CIN0-CIN2) Reference Voltage (VREF) Comparator Clock (CMPCLK, fx/16, fx/32) Comparison Result (CMPREG) Comparsion Start Comparsion End ValidInvalid 011 Invalid Figure 17-3. Conversion Characteristics 311

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification /g41 PROGRAMMING TIP — Programming the Comparator The following code converts the analog voltage input at the CIN0-CIN2 pins into 3-bit digital code: LD R0,#0FH LD CMPCON,#0CXH ; Analog input selection (CIN0-CIN2) ; X = 0 – F, comparator enable ; internal reference, conversion time (8 x 2 5/fx) WAIT0 LD R2,#02H WAIT1 LD R1,R0 LD R3,#10H WAIT2 NOP DJNZ R3,WAIT2 LD R0,CMPREG ; Read the result NOP NOP DJNZ R2,WAIT1 CP R0,R1 JR NE,WAIT0 SB1 LD P2,R0 ; Output the result from port 2 312

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

18 EMBEDDED FLASH MEMORY INTERFACE

The S3F82NB has an on-chip flash memory internally instead of masked ROM. The flash memory is accessed by 'LDC' instruction and the type of sector erase and a byte programmable flash, a user can program the data in a flash memory area any time you want. The S3F82NB's embedded 64K-bytes memory has two operating features as below: — User Program Mode — Tool Program Mode: Refer to the chapter 21. S3F82NB FLASH MCU. 313

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification USER PROGRAM MODE This mode supports sector erase, byte programming, byte read and one protection mode (Hard lock protection). The read protection mode is available only in Tool Program mode. So in order to make a chip into read protection, you need to select a read protection option when you program an initial your code to a chip by using Tool Program mode by using a programming tool. The S3F82NB has the pumping circuit internally; therefore, 12.5V into V PP (Test) pin is not needed. To program a flash memory in this mode several control registers will be used. There are four kind functions – programming, reading, sector erase and hard lock protection NOTES 1. The user program mode cannot be used when the CPU operates with the subsystem clock. 2. Be sure to execute the DI instruction before starting user program mode. The user program mode checks the interrupt request register (IRQ). If an interrupt request is generated, user program mode is stopped. 3. User program mode is also stopped by an interrupt request that is masked even in the DI status. To prevent this, Be disable the interrupt by using the each peripheral interrupt enable bit. 314

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification FLASH MEMORY CONTROL REGISTERS (User Program Mode) Flash Memory Control Register FMCON register is available only in user program mode to select the Flash Memory operation mode; sector erase, byte programming, and to make the flash memory into a hard lock protection. Flash Memory Control Register (FMCON) F9H, Set 1, Bank 0, R/W Flash operation start bit: 0 = Operation stop 1 = Operation start (This bit will be cleared automatically just after the corresponding operation completed).Sector erase status bit: 0 = Success sector erase 1 = Fail sector erase Flash memory mode selection bits: 0101 = Programming mode 1010 = Sector erase mode 0110 = Hard lock mode others = Not available Not used for S3F82NB Figure 18-1. Flash Memory Control Register (FMCON) The bit0 of FMCON register (FMCON.0) is a start bit for Erase and Hard Lock operation mode. Therefore, operation of Erase and Hard Lock mode is activated when you set FMCON.0 to "1". Also you should wait a time of Erase (Sector erase) or Hard lock to complete it's operation before a byte programming or a byte read of same sector area by using "LDC" instruction. When you read or program a byte data from or into flash memory, this bit is not needed to manipulate. The sector erase status bit is read only. Even if IMR bits are “0”, the interrupt is serviced during the operation of "Sector erase", when the each peripheral interrupt enable bit is set “1” and interrupt pending bit is set “1”. If an interrupt is requested during the operation of "Sector erase", the operation of "Sector erase" is discontinued, and the interrupt is served by CPU. Therefore, the sector erase status bit should be checked after executing "Sector erase". The "sector erase" operation is success if the bit is logic "0", and is failure if the bit is logic "1". NOTE When the ID code, "A5H", is written to the FMUSR register. A mode of sector erase, user program, and hard lock may be executed unfortunately. So, it should be careful of the above situation. 315

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory. This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise. After reset, the user-programming mode is disabled, because the value of FMUSR is "00000000B" by reset operation. If necessary to operate the flash memory, you can use the user programming mode by setting the value of FMUSR to "10100101B". The other value of "10100101b", User Program mode is disabled. Flash Memory User Programming Enable Register (FMUSR) F8H, Set 1, Bank 0, R/W Flash memory user programming enable bits: 10100101: Enable user programming mode Other values: Disable user programming mode Figure 18-2. Flash Memory User Programming Enable Register (FMUSR) 316

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ISPTM (ON-BOARD PROGRAMMING) SECTOR ISPTM sectors located in program memory area can store On Board Program software (Boot program code for upgrading application code by interfacing with I/O port pin). The ISPTM sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software. The ISP sectors are available only when the ISP enable/disable bit is set 0, that is, enable ISP at the Smart Option. If you don't like to use ISP sector, this area can be used as a normal program memory (can be erased or programmed by LDC instruction) by setting ISP disable bit ("1") at the Smart Option. Even if ISP sector is selected, ISP sector can be erased or programmed in the Tool Program mode, by Serial programming tools. The size of ISP sector can be varied by settings of Smart Option. You can choose appropriate ISP sector size according to the size of On Board Program software. (HEX) FFFFH 3FH Smart Option Area FFH 8FFH Interrupt Vector Area 64K-bytes Internal Program Memory Area Available ISP Sector Area 3CH 00H (Decimal) 65,535 255 Byte Figure 18-5. Program Memory Address Space 318

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 18-1. ISP Sector Size Smart Option(003EH) ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bit 2 Bit 1 Bit 0 1 x x – 0 0 0 0 100H – 1FFH (256 Byte) 256 Bytes 0 0 1 100H – 2FFH (512 Byte) 512 Bytes 0 1 0 100H – 4FFH (1024 Byte) 1024 Bytes 0 1 1 100H – 8FFH (2048 Byte) 2048 Bytes NOTE: The area of the ISP sector selected by Smart Option bit (003EH.2 – 003EH.0) can not be erased and programmed by LDC instruction in User Program mode. ISP RESET VECTOR AND ISP SECTOR SIZE If you use ISP sectors by setting the ISP Enable/Disable bit to "0" and the Reset Vector Selection bit to “0” at the Smart Option, you can choose the reset vector address of CPU as shown in Table 18-2 by setting the ISP Reset Vector Address Selection bits. Table 18-2. Reset Vector Address Smart Option (003EH) ISP Reset Vector Address Selection Bit Reset Vector Address After POR Usable Area for ISP Sector ISP Sector Size Bit 7 Bit 6 Bit 5 1 x x 0100H – – 0 0 0 0200H 100H – 1FFH 256 Bytes 0 0 1 0300H 100H – 2FFH 512 Bytes 0 1 0 0500H 100H – 4FFH 1024 Bytes 0 1 1 0900H 100H – 8FFH 2048 Bytes NOTE: The selection of the ISP reset vector address by Smart Option (003EH.7 – 003EH.5) is not dependent of the selection of ISP sector size by Smart Option (003EH.2 – 003EH.0). 319

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode. The only unit of flash memory to be erased and programmed in User Program Mode is called sector. The program memory of S3F82NB is divided into 512 sectors for unit of erase and programming, respectively. Every sector has all 128-byte sizes of program memory areas. So each sector should be erased first to program a new data (byte) into a sector. Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit (FMCON.0). Sector Erase is not supported in Tool Program Modes (MDS mode tool or Programming tool). 0000H FFFFH S3F82NB Sector 511 (128 byte) FF7FH FEFFH 3FFFH 05FFH 057FH 0500H 3F7FH Sector 510 (128 byte) Sector 127 (128 byte) Sector 11 (128 byte) Sector 10 (128 byte) Sector 0-9 (128 byte x 10) 04FFH Figure 18-6. Sector Configurations in User Program Mode 320

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification The Sector Erase Procedure in User Program Mode 1. If the procedure of Sector Erase needs to be stopped by any interrupt, set the appropriately bit of Interrupt Mask Enable Register (IMR) and the appropriately peripheral interrupt enable bit. Otherwise clear all bits of Interrupt Mask Enable Register (IMR) and all peripheral interrupt enable bits. 2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 3. Set Flash Memory Sector Address Register (FMSECH/ FMSECL). 4. Check user’s ID code (written by user) 5. Set Flash Memory Control Register (FMCON) to “10100001B”. 6. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”. 7. Check the “Sector erase status bit” whether “Sector erase” is success or not. /g41/g3PROGRAMMING TIP — Sector Erase /g120 /g120 SB0 reErase: LD FMUSR,Temp0 ; User Program mode enable ; Temp0 = #0A5H ; Temp0 variable is must be setting another routine LD FMSECH,#10H LD FMSECL,#00H ; Set sector address (1000H–107FH) CP UserID_Code,#User_value ; Check user’s ID code (written by user) ; User_value is any value by user JR NE,Not_ID_Code ; If not equal, jump to Not_ID_Code LD FMCON,Temp1 ; Start sector erase ; Temp1 = #0A1H ; Temp1 variable is must be setting another routine NOP ; Dummy Instruction, This instruction must be needed NOP ; Dummy Instruction, This instruction must be needed LD FMUSR,#0 ; User Program mode disable TM FMCON,#00001000B ; Check “Sector erase status bit” JR NZ,reErase ; Jump to reErase if fail /g120 /g120 /g120 /g120 Not_ID_Code: SB0 LD FMUSR,#0 ; User Program mode disable LD FMCON,#0 ; Sector erase mode disable /g120 /g120 /g120 NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine. Temp0~Temp(n) variables are should be defined by user. 321

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification PROGRAMMING A flash memory is programmed in one byte unit after sector erase. And for programming safety's sake, must set FMSECH and FMSECL to flash memory sector value. The write operation of programming starts by 'LDC' instruction. You can write until 128 byte, because this flash sector's limit is 128 byte. So, if you written 128 byte, must reset FMSECH and FMSECL. The Program Procedure in User Program Mode 1. Must erase sector before programming. 2. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 3. Set Flash Memory Sector Register (FMSECH, FMSECL) to sector value of write address. 4. Load a flash memory upper address into upper register of pair working register. 5. Load a flash memory lower address into lower register of pair working register. 6. Load a transmission data into a working register. 7. Check user’s ID code (written by user) 8. Set Flash Memory Control Register (FMCON) to “01010001B”. 9. Load transmission data to flash memory location area on ‘LDC’ instruction by indirectly addressing mode 10. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”. 322

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification /g41/g3PROGRAMMING TIP — Programming /g120 /g120 S B 0 LD FMUSR,Temp0 ; User Program mode enable ; Temp0 = #0A5H ; Temp0 variable is must be setting another routine LD FMSECH,#17H LD FMSECL,#80H ; Set sector address (1780H-17FFH) LD R2,#17H ; Set a ROM address in the same sector 1780H–17FFH LD R3,#84H LD R4,#78H ; Temporary data CP UserID_Code,#User_value ; Check user’s ID code (written by user) ; User_value is any value by user JR NE,Not_ID_Code ; If not equal, jump to Not_ID_Code LD FMCON,Temp1 ; Start program ; Temp1 = #51H ; Temp1 variable is must be setting another routine LDC @RR2,R4 ; Write the data to a address of same sector(1784H) NOP ; Dummy Instruction, This instruction must be needed LD FMUSR,#0 ; User Program mode disable /g120 /g120 /g120 /g120 Not_ID_Code: SB0 LD FMUSR,#0 ; User Program mode disable LD FMCON,#0 ; Programming mode disable /g120 /g120 /g120 /g120 NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine. Temp0~Temp(n) variables are should be defined by user. 323

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification READING The read operation of programming starts by ‘LDC’ instruction. The Reading Procedure in User Program Mode 1. Load a flash memory upper address into upper register of pair working register. 2. Load a flash memory lower address into lower register of pair working register. 3. Load receive data from flash memory location area on ‘LDC’ instruction by indirectly addressing mode /g41/g3PROGRAMMING TIP — Reading /g120 /g120 LD R2,#3H ; Load flash memory upper address ; to upper of pair working register LD R3,#0 ; Load flash memory lower address ; to lower pair working register LOOP: LDC R0,@RR2 ; Read data from flash memory location ; (Between 300H and 3FFH) INC R3 CP R3,#0H JP NZ,LOOP /g120 /g120 /g120 /g120 324

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification HARD LOCK PROTECTION User can set Hard Lock Protection by write ‘0110’ in FMCON.7-4. If this function is enabled, the user cannot write or erase the data in a flash memory area. This protection can be released by the chip erase execution (in the tool program mode). In terms of user program mode, the procedure of setting Hard Lock Protection is following that. Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection. Please refer to the manual of serial program writer tool provided by the manufacturer. The Hard Lock Protection Procedure in User Program Mode 1. Set Flash Memory User Programming Enable Register (FMUSR) to “10100101B”. 2. Check user’s ID code (written by user) 3. Set Flash Memory Control Register (FMCON) to “01100001B”. 4. Set Flash Memory User Programming Enable Register (FMUSR) to “00000000B”. /g41/g3PROGRAMMING TIP — Hard Lock Protection /g120 /g120 SB0 LD FMUSR,Temp0 ; User Program mode enable ; Temp0 = #0A5H ; Temp0 variable is must be setting another routine CP UserID_Code,#User_value ; Check user’s ID code (written by user) ; User_value is any value by user JR NE,Not_ID_Code ; If not equal, jump to Not_ID_Code LD FMCON,Temp1 ; Hard Lock mode set & start ; Temp1 = #61H ; Temp1 variable is must be setting another routine NOP ; Dummy Instruction, This instruction must be needed LD FMUSR,#0 ; User Program mode disable /g120 /g120 /g120 /g120 Not_ID_Code: SB0 LD FMUSR,#0 ; User Program mode disable LD FMCON,#0 ; Hard Lock Protection mode disable /g120 /g120 /g120 /g120 NOTE: In case of Flash User Mode, the Tmep0~Temp1’s data values are must be setting another routine. Temp0~Temp(n) variables are should be defined by user. 325

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

19 ELECTRICAL DATA

In this chapter, S3F82NB electrical characteristics are presented in tables and graphs. The information is arranged in the following order: — Absolute maximum ratings — Input/output capacitance — D.C. electrical characteristics — A.C. electrical characteristics — Oscillation characteristics — Oscillation stabilization time — Data retention supply voltage in stop mode — LVR timing characteristics — A/D converter electrical characteristics — Serial I/O timing characteristics — Comparator electrical characteristics — LCD contrast controller electrical characteristics — Internal Flash ROM electrical characteristics — Operating voltage range 326

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-1. Absolute Maximum Ratings (TA = 25 /g113C) Parameter Symbol Conditions Rating Unit Supply voltage VDD – – 0.3 to + 6.5 Input voltage VI Ports 0-10 – 0.3 to VDD + 0.3 Output voltage VO – – 0.3 to VDD + 0.3 V One I/O pin active – 15 Output current high IOH All I/O pins active – 60 One I/O pin active + 30 (Peak value) Output current low IOL Total pin current for ports + 100 (Peak value) mA Operating temperature TA – – 40 to + 85 Storage temperature TSTG – – 65 to + 150 /g113C Table 19-2. D.C. Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Input high voltage VIH1 All input pins except V IH2, 3 0.7V DD – VDD VIH2 P0.0-P0.1, P1, P5.4-P5.7, P6, nRESET 0.8VDD VDD VIH3 X IN, XOUT, XTIN, XTOUT V DD–0.1 VDD Input low voltage VIL1 All input pins except V IL2, 3 – – 0.3VDD VIL2 P0.0-P0.1, P1, P5.4-P5.7, P6, nRESET 0.2V DD VIL3 X IN, XOUT, XTIN, XTOUT 0.1 327

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-2. D.C. Electrical Characteristics (Continued) (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Output high voltage VOH V DD = 4.5V to 5.5V IOH = – 1 m A All output ports VDD–1.0 – – VDD = 4.5V to 5.5V IOL = 15mA All output ports – – 2.0 Output low voltage VOL VDD = 1.8V to 5.5V IOL = 1.6mA 0.4 V ILIH1 V IN = VDD All input pins except ILIH2 – – 3 Input high leakage current ILIH2 V IN = VDD XIN, XOUT, XTIN, XTOUT ILIL1 V IN = 0 V All input pins except for nRESET, ILIL2 – – –3 Input low leakage current ILIL2 V IN = 0 V XIN, XOUT, XTIN, XTOUT –20 Output high leakage current I LOH V OUT = VDD All output pins – – 3 Output low leakage current I LOL V OUT = 0 V All output pins – – –3 /g80A LCD voltage dividing resistor R LCD TA = 25 /g113C 40 60 80 ROSC1 VDD = 5 V, TA= 25 /g113C XIN = VDD, XOUT = 0 V 420 850 1700 Oscillator feed back resistors R OSC2 VDD = 5 V, TA= 25 /g113C XTIN = VDD, XTOUT = 0 V 2200 4500 9000 VIN = 0 V; VDD = 5 V TA = 25 /g113C, Ports 0–10 25 50 100 RL1 VIN = 0 V; VDD = 3 V TA = 25 /g113C, Ports 0–10 50 100 150 VIN = 0 V; VDD = 5 V TA = 25 /g113C, nRESET 150 250 400 k/g58 Pull-up resistor RL2 VIN = 0 V; VDD = 3 V TA = 25 /g113C, nRESET 300 500 700 328

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-2. D.C. Electrical Characteristics (Continued) (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Middle output voltage (note) VLC4 VDD = 2.4V to 5.5V, 1/5 Bias LCD clock = 0Hz, VLC0 = VDD V |VLCD – COMi| Voltage drop (i = 0 – 15) VDC –15 /g80A per common pin – – 120 |VLCD – SEGx| Voltage drop (x = 0 – 87) V DS –15 /g80A per segment pin –– 120 mV NOTE: It is middle output voltage when the V DD and VLC0 pin are connected. 329

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-2. D.C. Electrical Characteristics (Concluded) (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit 12.0 MHz – 2.2 4.0 Run mode: VDD = 5.0V Crystal oscillator C1 = C2 = 22pF 4.2 MHz 1.2 2.0 IDD1 (2) VDD = 3.0V 4.2 MHz 0.8 1.5 12.0 MHz – 1.3 2.3 Idle mode: VDD = 5.0V Crystal oscillator C1 = C2 = 22pF 4.2 MHz 0.8 1.5 IDD2 (2) VDD = 3.0V 4.2 MHz 0.4 0.8 mA IDD3 (3) Sub Operating mode: VDD = 3.0V 32kHz crystal oscillator – 65.0 100.0 IDD4 (3) Sub Idle mode: V DD = 3.0V 32kHz crystal oscillator – 6.0 15.0 Supply current (1) IDD5 (4) Stop mode: VDD = 5.0V – 0.3 6.0 /g80A NOTES: 1. Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, the LVR block, and external output current loads. 2. I DD1 and IDD2 include a power consumption of sub clock oscillation. 3. I DD3 and IDD4 are the current when the main clock oscillation stops and the sub clock is used. 4. I DD5 is the current when the main and sub clock oscillation stops. 5. Every value in this table is measured when bits 4-3 of the system clock control register (CLKCON.4–.3) is set to 11B. 330

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-3. A.C. Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Interrupt input high, low width t INTH, tINTL All interrupt, V DD = 5 V 500 – – ns nRESET input low width tRSL Input, V DD = 5 V 10 – – /g80s NOTE: If width of interrupt or reset pulse is greater than min. value, pulse is always recognized as valid pulse. tINTHtINTL

0.8 VDD

0.2 VDD

Figure 19-1. Input Timing for External Interrupts nRESET tRSL Figure 19-2. Input Timing for nRESET 331

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-4. Input/Output Capacitance (TA = – 40 /g113C to + 85 /g113C, VDD = 0 V ) Parameter Symbol Conditions Min Typ Max Unit Input capacitance CIN f = 1 MHz; unmeasured pins are returned to VSS – – 10 pF Output capacitance COUT I/O capacitance CIO Table 19-5. Data Retention Supply Voltage in Stop Mode (TA = – 40 /g113C to + 85 /g113C) Parameter Symbol Conditions Min Typ Max Unit Data retention supply voltage V DDDR 1.8 – 5.5 V Data retention supply current I DDDR Stop mode, TA = 25 /g113C VDDDR = 1.8V Disable LVR block – – 1 /g80A 332

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Execution of STOP Instrction nRESET Occurs VDDDR Stop Mode Oscillation Stabilization Time Normal Operating ModeData Retention Mode tWAIT nRESET VDD NOTE: tWAIT is the same as 4096 x 16 x 1/fxx. Figure 19-3. Stop Mode Release Timing Initiated by nRESET tWAIT Normal Operation Mode 0.2VDD VDDDR Data Retention Mode ~~ Stop Mode Execution of STOP Instruction VDD Interrupt NOTE: tWAIT is the same as 16 x 1/fBT. (fBT is basic timer clock selected) IDLE Mode Oscillation Stabillization TIme Figure 19-4. Stop Mode Release Timing Initiated by Interrupts 333

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-6. A/D Converter Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 2.7 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Resolution – – – 10 – bit Total accuracy – – – – /g1143 LSB Integral linearity error ILE – – /g1142 Differential linearity error DLE – /g1141 Offset error of top EOT /g1141 /g1143 Offset error of bottom EOB VDD = 5.120 V VSS = 0 V CPU clock = 12.0 MHz /g1141 /g1143 Conversion time (1) TCON – 25 – – /g80S Analog input voltage VIAN – VSS – AVREF V Analog input impedance R AN – 2 1000 – M/g58 Analog reference voltage AV REF – 1.8 – VDD V Analog input current IADIN V DD = 5.0 V – – 10 /g80A IADC V DD = 5.0 V – 0.5 1.5 mA Analog block current (2) VDD = 5.0 V When power down mode 100 500 nA NOTES: 1. 'Conversion time' is the time required from the moment a conversion operation starts until it ends. 2. I ADC is an operating current during A/D converter. 334

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-7. Synchronous SIO Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit SCK Cycle time tKCY External SCK source 1,000 – – ns Internal SCK source 1,000 SCK high, low width tKH, tKL External SCK source 500 Internal SCK source tKCY/2-50 SI setup time to SCK high tSIK External SCK source 250 Internal SCK source 250 SI hold time to SCK high tKSI External SCK source 400 Internal SCK source 400 Output delay for SCK to SO tKSO External SCK source – 300 Internal SCK source 250 Output Data Input Data SCK tKH tKCY tKL Figure 19-5. Serial Data Transfer Timing 335

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-8. Low Voltage Reset Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Test Condition Min Typ Max Unit Voltage of LVR VLVR – 1.9 2.0 2.1 V VDD voltage rising time t R – 10 – – /g80S VDD voltage off time t OFF – 0.5 – – S Hysteresis LVR ୞V – – 10 100 mV Current consumption ILVR V DD = 3.0 V – 30 60 /g80A NOTE: The current of LVR circuit is consumed when LVR is enabled by “Smart Option”. VDD tOFF 0.1VDD 0.9VDD tR Figure 19-6. LVR (Low Voltage Reset) Timing 336

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-9. Comparator Converter Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 4.0 V to 5.5 V) Parameter Symbol Condition Min Typ Max Unit Input voltage range – – 0 – VDD V Reference voltage range VREF – 0 – VDD V 8 x 25/fx, @0.4 ~ 12.0 MHz Input voltage accuracy VCIN 8 x 24/fx, @0.4 ~ 6.0 MHz – – /g114150 mV Input leakage current ICIN, IREF – – 3 – 3 /g80A Table 19-10. LCD Contrast Controller Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 4.5 V to 5.5 V) Parameter Symbol Condition Min Typ Max Unit Resolution – – – – 4 Bits Linearity RLIN V DD = 5.0 V – – /g114150 mV Max output voltage VLPP V LC0 = VDD = 5.0 V LMOD = #F8H 4.9 – VLC0 V 337

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 19-11. Main Oscillator Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Main oscillation frequency 2.2 V – 5.5 V 0.4 – 12.0 MHzCrystal XIN XOUT Main oscillation frequency 2.2 V – 5.5 V 0.4 – 12.0 Ceramic Oscillator XIN XOUT XIN input frequency 2.2 V – 5.5 V 0.4 – 12.0 External Clock XIN XOUT Frequency 3.0 V 0.4 – 1 RC Oscillator XIN XOUT R 5.0 V 0.4 – 2 MHz Table 19-12. Sub Oscillation Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Oscillator Clock Configuration Parameter Test Condition Min Typ Max Units Crystal XTIN XTOUT Sub oscillation frequency 1.8 V – 5.5 V – 32.768 – kHz External clock XTIN XTOUT XTIN input frequency 1.8 V – 5.5 V 32 – 100 338

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Supply Voltage (V) CPU Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16) Instruction Clock 400 kHz 1.8V 3

12.0 MHz

Main oscillation frequency 3.0MHz

1.05 MHz

4.2 MHz

5.5V 2.0 MHz0.5 MHz 5 4 2.2V Figure 19-9. Operating Voltage Range Table 19-15. Internal Flash ROM Electrical Characteristics (TA = – 40 /g113C to + 85 /g113C, VDD = 1.8 V to 5.5 V) Parameter Symbol Conditions Min Typ Max Unit Programming Time (1) Ftp – 20 25 30 /g80s Chip Erasing Time (2) Ftp1 32 50 70 ms Sector Erasing Time (3) Ftp2 4 8 12 ms Read frequency fR – – – 12 MHz Number of Writing/Erasing FNWE – – – 10,000(4) Times NOTES: 1. The Programming time is the time during which one byte (8-bit) is programmed. 2. The Chip erasing time is the time during which all 64K byte block is erased. 3. The Sector erasing time is the time during which all 128 byte block is erased. 4. The Chip erasing is available in Tool Program Mode only. 340

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification NOTES 341

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

20 MECHANICAL DATA

The S3F82NB microcontroller is currently available in 128-pin-QFP package. 128-QFP-1420 #128 20.00 /g114/g30.20 22.00/g3/g114/g30.30 14.00 /g114/g30.20 16.00/g3/g114/g30.30 0.15 + 0.10 - 0.05 0-8

0.10 MAX

NOTE: Dimensions are in millimeters. (0.75) 0.50 /g114/g30.20

0.05 MIN

2.10 /g114/g30.10

2.40 MAX

0.50 0.20 + 0.10 - 0.05 (0.75) Figure 20-1. Package Dimensions (128-QFP-1420) 342

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

21 S3F82NB FLASH MCU

The S3F82NB single-chip CMOS microcontroller is the Flash MCU. It has an on-chip Flash MCU ROM. The Flash ROM is accessed by serial data format. NOTE This chapter is about the Tool Program Mode of Flash MCU. If you want to know the User Program Mode, refer to the chapter 18. Embedded Flash Memory Interface. 343

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification S3F82NB 128-QFP-1420 COM9/SEG1 COM8/SEG0 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 VLC4 VLC3 VLC2 VLC1 VLC0 P1.7/SCK/INT7 P1.6/SO/INT6 SDAT/P1.5/SI/INT5 SCLK/P1.4/BUZ/INT4 VDD/VDD VSS/VSS XOUT XIN VPP/TEST XTIN XTOUT nRESET/nRESET P1.3/INT3 P1.2/INT2 P1.1/INT1 P1.0/AVREF/INT0 P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/T0OUT/T0PWM/T0CAP/AD3 P0.2/T1OUT/T1PWM/T1CAP/AD2 P0.1/T0CLK/AD1 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 P10.4/SEG28 P10.5/SEG29 P10.6/SEG30 P10.7/SEG31 P9.0/SEG32 P9.1/SEG33 P9.2/SEG34 P9.3/SEG35 P9.4/SEG36 P9.5/SEG37 P9.6/SEG38 P9.7/SEG39 P8.0/SEG40 P8.1/SEG41 P8.2/SEG42 P8.3/SEG43 P8.4/SEG44 P8.5/SEG45 P8.6/SEG46 P8.7/SEG47 P7.0/SEG48 P7.1/SEG49 P7.2/SEG50 P7.3/SEG51 P7.4/SEG52 P7.5/SEG53 P7.6/SEG54 P7.7/SEG55 P2.0/SEG56 P2.1/SEG57 P2.2/SEG58 P2.3/SEG59 P2.4/SEG60 P2.5/SEG61 P2.6/SEG62 P2.7/SEG63 P3.0/SEG64 P3.1/SEG65 102 101 100 P0.0/T1CLK/AD0 P6.2/CIN2 P6.1/CIN1 P6.0/CIN0 P5.7/INT11/SEG87 P5.6/INT10/SEG86 P5.5/INT9/SEG85 P5.4/INT8/SEG84 P5.3/SEG83 P5.2/SEG82 P5.1/SEG81 P5.0/SEG80 P4.7/SEG79 P4.6/SEG78 P4.5/SEG77 P4.4/SEG76 P4.3/SEG75 P4.2/SEG74 P4.1/SEG73 P4.0/SEG72 P3.7/SEG71 P3.6/SEG70 P3.5/SEG69 P3.4/SEG68 P3.3/SEG67 P3.2/SEG66 COM10/SEG2 COM11/SEG3 COM12/SEG4 COM13/SEG5 COM14/SEG6 COM15/SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 P10.0/SEG24 P10.1/SEG25 P10.2/SEG26 P10.3/SEG27 Figure 21-1. S3F82NB Pin Assignments (100-QFP-1420) 344

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 21-1. Descriptions of Pins Used to Read/Write the Flash ROM Main Chip During Programming Pin Name Pin Name Pin No. I/O Function P1.5 SDAT 18 I/O Serial data pin. Output port when reading and input port when writing. Can be assigned as a Input/push-pull output port. P1.4 SCLK 19 I/O Serial clock pin. Input only pin. TEST VPP 24 I Tool mode selection when TEST/ V PP pin sets Logic value ‘1’. If user uses the flash writer tool mode (ex.spw2+ etc..), user should be connected TEST/ V PP pin to VDD. (S3F82NB supplies high voltage 12.5V by internal high voltage generation circuit.) nRESET nRESET 27 I Chip Initialization VDD, VSS V DD, VSS 20, 21 /g16/g3Power supply pin for logic circuit. VDD should be tied to 5.0V during programming. Test Pin Voltage The TEST pin on socket board for MTP writer must be connected to VDD (5.0V) with RC delay as the figure 21-2 (only when SPW 2+ and GW-pro2 are used to). The TEST pin on socket board must not be connected Vpp (12.5V) which is generated from MTP Writer. So the specific socket board for S3F82NB must be used, when writing or erasing using MTP writer. }ww VDD R (330ȳ) C (0.1uF) Figure 21-2. RC Delay Circuit 345

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification ON BOARD WRITING The S3F82NB needs only 6 signal lines including VDD and VSS pins for writing internal flash memory with serial protocol. Therefore the on-board writing is possible if the writing signal lines are considered when the PCB of application board is designed. Circuit Design Guide At the flash writing, the writing tool needs 6 signal lines that are VSS, VDD, nRESET, TEST, SDAT and SCLK. When you design the PCB circuits, you should consider the usage of these signal lines for the on-board writing. In case of TEST pin, normally test pin is connected to VSS but in writing mode the programming these two cases, a resistor should be inserted between the TEST pin and VSS. The nRESET, SDAT and SCLK should be treated under the same consideration. Please be careful to design the related circuit of these signal pins because rising/falling timing of V PP, SCLK and SDAT is very important for proper programming. G VDD VSS VDD GND SCLK SDAT nRESET VPP C nRESET and C VPP are used to improve the noise effect. R SCLK To Application circuitSCLK(I/O) R SDAT SDAT(I/O) R nRESET nRESET R VPP VPP(TEST) C VPP C nRESET ,SPW-uni , AS-pro, US-proGW-uni To Application circuit To Application circuit NOTE: If writer tool is the SPW 2+ and GW-pro2, reference to the page 21-3. Figure 21-3. PCB Design Guide for on Board Programming 346

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Reference Table for Connection Table 21-2. Reference Table for Connection Pin Name I/O mode in Applications Resistor (need) Required value VPP (TEST) Input Yes RVpp is 10 Kohm ~ 50 Kohm. CVpp is 0.01uF ~ 0.02uF. nRESET Input Yes RnRESET is 2 Kohm ~ 5 Kohm. CnRESET is 0.01uF ~ 0.02uF. Input Yes R SDAT is 2 Kohm ~ 5 Kohm. SDAT(I/O) Output No (NOTE) /g16/g3 Input Yes R SCLK is 2 Kohm ~ 5 Kohm. SCLK(I/O) Output No (NOTE) /g16/g3 NOTES: 1. In on-board writing mode, very high-speed signal will be provided to pin SCLK and SDAT. And it will cause some damages to the application circuits connected to SCLK or SDAT port if the application circuit is designed as high speed response such as relay control circuit. If possible, the I/O configuration of SDAT, SCLK pins had better be set to input mode. 2. The value of R, C in this table is recommended value. It varies with circuit of system. 347

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification

22 DEVELOPMENT TOOLS

Samsung provides a powerful and easy-to-use development support system on a turnkey basis. The development support system is composed of a host system, debugging tools, and supporting software. For a host system, any standard computer that employs Win95/98/2000/XP as its operating system can be used. A sophisticated debugging tool is provided both in hardware and software: the powerful in-circuit emulator, OPENice-i500 and SK- 1200, for the S3C7-, S3C9-, and S3C8- microcontroller families. Samsung also offers supporting software that includes, debugger, an assembler, and a program for setting options. TARGET BOARDS Target boards are available for all the S3C8/S3F8-series microcontrollers. All the required target system cables and adapters are included on the device-specific target board. TB82NB is a specific target board for the development of application systems using S3F82NB. PROGRAMMING SOCKET ADAPTER When you program S3F82NB’s flash memory by using an emulator or OTP/MTP writer, you need a specific programming socket adapter for S3F82NB. 348

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification BUS Emulator [SK-1200 (RS-232, USB) or OPENice i-500 (RS-232) ]RS-232C/USB POD Probe Adapter OTP/MTP Writer Block RAM Break/Display Block Trace/Timer Block SAM8 Base Block Power Supply Block IBM-PC AT or Compatible TB82NB Target Board EVAChip Target Application System Figure 22-1. Emulator Product Configuration 349

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification TB82NB TARGET BOARD The TB82NB target board can be used for development of the S3F82NB microcontroller. The TB82NB target board is operated as target CPU with Emulator (SK-1200, OPENice-i500)). TB82NB RESET IDLE + STOP 7411U2 VDDGND (sub-clock) J101 64-Pin Connector 63 64 64-Pin Connector 6665 127 128 J102

208 QFP

To User_VCC Off On 100-Pin Connector In-Circuit Emulator (SK-1200, OPENice-i500) VDD VCC AVREF CN4 VLC1 VLC0 VLC2 VLC3 CN2 VLC4 VDD Smart Option Selection ON SW1 1 23 45 6 78 91 0 "0" "1" JP2 TP1External Internal JP1 (Smart Option Source) CN1 nRESET VSS VDD VPP SDAT SCLK CN6 (TB Mode Selection) Main Mode Eva Mode Figure 22-2. TB82NB Target Board Configuration NOTE: The symbol ‘ ‘ marks start point of jumper signals. 350

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 22-1. Components of TB82NB Symbols Usage Description J2 100-pin connector Connection between emulator and TB82NB target board. J101, J102 64-pin connector Connection between target board and user application system RESET Push button Generation low active reset signal to S3F82NB EVA-chip VDD, GND POWER connector External power connector for TB82NB STOP, IDLE LED STOP/IDLE Display Indicate the status of STOP or IDLE of S3F82NB EVA-chip on TB82NB target board CN1 Flash serial programming Signal points for programming Flash ROM by external programmer. Don’t use this one in user mode. CN6 TB Mode Selection Selection of EVA/MAIN-chip mode 351

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Table 22-2. Setting of the Jumper in TB82NB JP# Description 1-2 Connection 2-3 Connection Default Setting VDD User power Join 2-3 CN4 AV REF power source You should activate AVREF on the TB82NB by setting the related TP1. TP1 P1.0/INT0 or AV REF selection TP1 should be used P1.0/INT0 normally. If user wants to use the AVREF, user should be connected to VSS. CN6 Target board mode selection H: MAIN-Mode L: EVA-Mode Join 2-3 JP2 Clock source selection When using the internal clock source which is generated from Emulator, join connector 2-3 and 4-5 pin. If user wants to use the external clock source like a crystal, user should change the jumper setting from 1-2 to 5-6 and connect J1 to an external clock source. J1 External clock source Connecting points for external clock source Emulator 2-3 4-5 JP1 Smart option source selection The Smart Option is selected by external smart option switch (SW1) The Smart Option is selected by internal smart option area (003EH–0003FH of ROM). But this selection is not available. Join 1-2 SW1 Smart option selection The Smart Option can be selected by this switch when the Smart Option source is selected by external. The B2–B0 are comparable to the 003EH.2–.0. The B7–B5 are comparable to The B4–B3 and B9 are not connected. The TP1 is comparable to the 003FH.7. Refer to the page 2-3. CN1 Header for flash serial programming signals To program an internal flash, connect the signals with flash writer tool. To User_Vcc Target System is supplied VDD Target Board is not supplied VDD from user System. Target Board is supplied VDD from user System. Join 2-3 /g120 IDLE LED This LED is ON when the evaluation chip (S3E82N0) is in idle mode. /g120 STOP LED This LED is ON when the evaluation chip (S3E82N0) is in stop mode 352

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification J101 COM9/SEG1 COM7 COM5 COM3 COM1 VLC4 VLC2 VLC0 P1.6/INT6/SO P1.4/INT4/BUZ VSS N.C N.C nRESET P1.2/INT2 P1.0/INT0/AV REF P0.6/AD6 P0.4/AD4 P0.2/T1OUT/T1PWM/T1CAP/AD2 P0.0/T1CLK/AD0 P6.1/CIN1 P5.7/INT11/SEG87 P5.5/INT9/SEG85 P5.3/SEG83 P5.1/SEG81 P4.7/SEG79 P4.5/SEG77 P4.3/SEG75 P4.1/SEG73 P3.7/SEG71 P3.5/SEG69 P3.3/SEG67 COM8/SEG0 COM6 COM4 COM2 COM0 V LC3 VLC1 P1.7/INT7/SCK P1.5/INT5/SI VDD N.C N.C N.C P1.3/INT3 P1.1/INT1 P0.7/AD7 P0.5/AD5 P0.3/AD3/T0OUT/T0PWM/T0CAP P0.1/AD1/T0CLK P6.2/CIN2 P6.0/CIN0 P5.6/INT10/SEG86 P5.4/INT8/SEG84 P5.2/SEG82 P5.0/SEG80 P4.6/SEG78 P4.4/SEG76 P4.2/SEG74 P4.0/SEG72 P3.6/SEG70 P3.4/SEG68 P3.2/SEG66 64-Pin DIP Connector Figure 22-3. 64-Pin Connectors (J101, J102) for TB82NB 353

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification J102 P3.1/SEG65 P2.7/SEG63 P2.5/SEG61 P2.3/SEG59 P2.1/SEG57 P7.7/SEG55 P7.5/SEG53 P7.3/SEG51 P7.1/SEG49 P8.7/SEG47 P8.5/SEG45 P8.3/SEG43 P8.1/SEG41 P9.7/SEG39 P9.5/SEG37 P9.3/SEG35 P9.1/SEG33 P10.7/SEG31 P10.5/SEG29 P10.3/SEG27 P10.1/SEG25 SEG23 SEG21 SEG19 SEG17 SEG15 SEG13 SEG11 SEG9 COM15/SEG7 COM13/SEG5 COM11/SEG3 P3.0/SEG64 P2.6/SEG62 P2.4/SEG60 P2.2/SEG58 P2.0/SEG56 P7.6/SEG54 P7.4/SEG52 P7.2/SEG50 P7.0/SEG48 P8.6/SEG46 P8.4/SEG44 P8.2/SEG42 P8.0/SEG40 P9.6/SEG38 P9.4/SEG36 P9.2/SEG34 P9.0/SEG32 P10.6/SEG30 P10.4/SEG28 P10.2/SEG26 P10.0/SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 COM14/SEG6 COM12/SEG4 COM10/SEG2 64-Pin DIP Connector Figure 22-3. 64-Pin Connectors (J101, J102) for TB82NB (Continued) 354

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification Target Board 64-Pin DIP Connector Target System J102 65 66 127 128 J101 63 64 Target Cable for 64-Pin Connector 64-Pin DIP Connectors 65 66 127 128 63 64 J102 J101 Figure 22-4. S3F82NB Cables for 128-QFP Package 355

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification THIRD PARTIES FOR DEVELOPMENT TOOLS SAMSUNG provides a complete line of development tools for SAMSUNG's microcontroller. With long experience in developing MCU systems, our third parties are leading companies in the tool's technology. SAMSUNG In-circuit emulator solution covers a wide range of capabilities and prices, from a low cost ICE to a complete system with an OTP/MTP programmer. In-Circuit Emulator for SAM8 family /g120 OPENice-i500 /g120 SmartKit SK-1200 OTP/MTP Programmer /g120 SPW-uni /g120 GW-uni /g120 AS-pro /g120US-pro Development Tools Suppliers Please contact our local sales offices or the 3rd party tool suppliers directly as shown below for getting development tools. 8-bit In-Circuit Emulator AIJI System OPENice - i500 /g120 TEL: 82-31-223-6611 /g120 FAX: 82-331-223-6613 /g120 E-mail : openice@aijisystem.com /g120 URL : http://www.aijisystem.com SeminixSK-1200 /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819 /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com 356

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OTP/MTP PROGRAMMER (WRITER) SPW-uni Single OTP/ MTP/FLASH Programmer /g120 Download/Upload and data edit function /g120 PC-based operation with USB port /g120 Full function regarding OTP/MTP/FLASH MCU programmer (Read, Program, Verify, Blank, Protection..) /g120 Fast programming speed (4Kbyte/sec) /g120 Support all of SAMSUNG OTP/MTP/FLASH MCU devices /g120 Low-cost /g120 NOR Flash memory (SST, Samsung…) /g120 NAND Flash memory (SLC) /g120 New devices will be supported just by adding device files or upgrading the software. SEMINIX /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819. /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com GW-uni Gang Programmer for OTP/MTP/FLASH MCU /g120 8 devices programming at one time /g120 Download/Upload and data edit function /g120 PC-based operation with USB port /g120 Full function regarding OTP/MTP/FLASH MCU programmer (Read, Program, Verify, Blank, Protection..) /g120 Fast programming speed (4Kbyte/sec) /g120 Support all of SAMSUNG OTP/MTP/FLASH MCU devices /g120 Low-cost /g120 NOR Flash memory (SST, Samsung…) /g120 NAND Flash memory (SLC) /g120 New devices will be supported just by adding device files or upgrading the software. /g120 Will be developed in March, 2008. SEMINIX /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819. /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com 357

PS031601-0813 P R E L I M I N A R Y S3F82NB Product Specification OTP/MTP PROGRAMMER (WRITER) (Continued) AS-pro On-board programmer for Samsung Flash MCU /g120 Portable & Stand alone Samsung OTP/MTP/FLASH Programmer for After Service /g120 Small size and Light for the portable use /g120 Support all of SAMSUNG OTP/MTP/FLASH devices /g120 HEX file download via USB port from PC /g120 Very fast program and verify time ( OTP:2Kbytes per second, MTP:10Kbytes per second) /g120 Internal large buffer memory (118M Bytes) /g120 Driver software run under various O/S (Windows 95/98/2000/XP) /g120 Full function regarding OTP/MTP programmer (Read, Program, Verify, Blank, Protection..) /g120 Two kind of Power Supplies (User system power or USB power adapter) /g120 Support Firmware upgrade SEMINIX /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819. /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com US-pro Portable Samsung OTP/MTP/FLASH Programmer /g120 Portable Samsung OTP/MTP/FLASH Programmer /g120 Small size and Light for the portable use /g120 Support all of SAMSUNG OTP/MTP/FLASH devices /g120 Convenient USB connection to any IBM compatible PC or Laptop computers. /g120 Operated by USB power of PC /g120 PC-based menu-drive software for simple operation /g120 Very fast program and verify time ( OTP:2Kbytes per second, MTP:10Kbytes per second) /g120 Support Samsung standard Hex or Intel Hex format /g120 Driver software run under various O/S (Windows 95/98/2000/XP) /g120 Full function regarding OTP/MTP programmer (Read, Program, Verify, Blank, Protection..) /g120 Support Firmware upgrade SEMINIX /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819. /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com Flash writing adapter board /g120 Specific flash writing socket only for S3F82NB - 128QFP SEMINIX /g120 TEL: 82-2-539-7891 /g120 FAX: 82-2-539-7819. /g120 E-mail: sales@seminix.com /g120 URL: http://www.seminix.com 358