S10200-02

S10200-02 HAMAMATSU | Alldatasheet

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Technical content

Features

/K6C TDI mode gives high sensitivity /K6C High-speed, continuous image acquisition /K6C Back-thinned structure ensures high sensitivity from UV to near IR /K6C Multiple ports for high-speed line rate

Applications

/K6C Sequential imaging of high-speed moving samples /K6C Inspection tasks on electronic parts production line /K6C Semiconductor inspection /K6C Flow cytometery IMAGE SENSOR Back-thinned TDI-CCD Operating the back-thinned CCD in TDI mode delivers high sensitivity. S10200-02, S10201-04, S10202-08, S10202-16 PRELIMINARY DATA Jan. 2007 I Selection guide Type No. Pixel size (µm) Number of total pixels (H) × (V) Number of active pixels (H) × (V) Number of ports Pixel rate (MHz/port) Line rate (kHz) Vertical transfer S10200-02 1040 × 128 1024 × 128 2 S10201-04 2080 × 128 2048 × 128 4 S10202-08 4160 × 128 4096 × 128 8 S10202-16 12 × 12 4224 × 128 4096 × 128 16 100 Bidirectional I Specifications Parameter Specification TDI stage 128 Anti-blooming FW × 100 (Min.) Vertical clock 3 phases Horizontal clock 2 phases Output circuit Two-stage MOSFET source follower Package Ceramic DIP Window Quarts glass G Schematic diagram showing integrated exposure by TDI mode Time1 Time2 Time3 FIRST STAGE LAST STAGE M CHARGE TRANSFER OBJECT MOVEMENTCHARGE KMPDC0139EA v = f × d v: Object moving speed, Charge transfer speed, f: Vertical transfer frequency, d: Pixel size TDI (Time Delay Integration) mode In FFT-CCD, signal charges in each line are vertically transferred during charge readout. TDI mode synchronizes this vertical transfer timing with the movement of the object, so that signal charges are integrated a number of times equal to the number of vertical stages of the CCD pixels. In the TDI mode, the signal charges must be transferred in the same direction at the same speed as those of the object to be imaged. These speeds are expressed by the following equation: In the right figure, when the first stage charges are transferred to the second stage, an additional charges are produced in the second stage by photoelectric conversion and accumulated. When this operation is continuously repeated until reaching the last stage M (the number of vertical stages), signal charges which are M times greater than the initial charges are accumu- lated. Since the signal charges on each line are output from the CCD horizontal shift register, a two-dimensional image can be continuously acquired. In this way the TDI mode achieves sensitivity which is M times higher than linear image sensors (S/N is improved times). The TDI mode also improves sensitivity variations compared to frame mode op- eration. M

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 I Sensor structure TGb P3V P2V P1V TGa RG RD OD AGND OG SG P2H P1H OSa1 OSa2 OSb1 OSb2 OFD OFG DGND B PORT SIDE 512 pixels A PORT SIDE BIDIRECTIONAL TRANSFER 128 pixels KMPDC0251EA TGb P3V P2V P1V TGa RG RD OD AGND OG SG P2H P1H OSa1 OSa2 OSb1 OSb2 OSa3 OSb3 OSa4 OSb4 OFD OFG DGND B PORT SIDE 512 pixels A PORT SIDE BIDIRECTIONAL TRANSFER 128 pixels KMPDC0260EA WAVELENGTH (nm) PHOTO SENSITIVITY (V/µJ · cm2) 500 1000 1500 2000 2500 200 400 600 900 800 1000300 500 700 1100 3000 (Typ. Ta=25 ˚C) I Spectral response (without window) KMPDB0268EA WAVELENGTH (nm) QUANTUM EFFICIENCY (%) 200 300 400 500 600 700 800 900 1000 1100 1200 100 (Typ. Ta=25 ˚C) BACK-THINNED CCD S10200-02 S10201-04 S10202-08 S10202-16 FRONT -ILLUMINATED CCD KMPDB0269EA S10201-04 S10200-02

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 TGb P3V P2V P1V TGa RG RD OD AGND OG SG P2H P1H OSa1 OSa2 OSb1 OSb2 OSa3 OSb3 OSa4 OSb4 OFD OFG DGND B PORT SIDE 512 pixels A PORT SIDE OSa5 OSb5 OSa8 OSb8 BIDIRECTIONAL TRANSFER 128 pixels S10202-08 KMPDC0261EA TGb P3V P2V P1V TGa RG RD OD AGND OG SG P2H P1H OSa1 OSa2 OSb1 OSb2 OSa3 OSb3 OSa4 OSb4 OFD OFG DGND B PORT SIDE 256 pixels A PORT SIDE OSa5 OSb5 OSa16 OSb16 OSa6 OSb6 OSa7 OSb7 OSa8 OSb8 OSa9 OSb9 OSa15 OSb15 BIDIRECTIONAL TRANSFER 128 pixels KMPDC0262EA I Absolute maximum ratings (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Operating temperature Topr -50 - 60 °C Storage temperature Tstg -50 - 70 °C Output transistor drain voltage V OD -0.5 - 25 V Reset drain voltage VRD -0.5 - 18 V Overflow drain voltage V OFD -0.5 - 18 V Overflow gate voltage VOFG -10 - 15 V Summing gate voltage V SG -10 - 15 V Output gate voltage VOG -10 - 15 V Reset gate voltage V RG -10 - 15 V Transfer gate voltage VTG -10 - 15 V Vertical clock voltage V P1V, VP2V, VP3V -10 - 15 V Horizontal clock voltage VP1H, VP2H -10 - 15 V S10202-16

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 I Operating conditions (TDI mode, Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Output transistor drain voltage V OD 12 15 18 V Reset drain voltage VRD 11 12 13 V Output gate voltage V OG 357 V Substrate voltage VDGND , VAGND - 0 - V Overflow drain voltage VOFD 4 6 9 V Overflow gate voltage VOFG 0 4 6 V High V P1VH , VP2VH , VP3VH 468Vertical shift register clock voltage Low V P1VL , VP2VL , VP3VL -6 -5 -4 V High VP1HH , VP2HH 4 6 8Horizontal shift register clock voltage Low VP1HL , VP2HL -6 -5 -4 V High VSGH 4 6 8Summing gate voltage Low VSHL -6 -5 -4 V High VRGH 7 8 9Reset gate voltage Low VRGL -6 0 - V High VTGH 4 6 8Transfer gate voltage Low VTGL -6 -5 -4 V I Electrical and optical characteristics (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Saturation output voltage Vsat - FW × Sv - V Full well capacity * 1 FW 100 120 140 ke- CCD node sensitivity Sv 3 3.5 4 µV/e - Dark current * 1, *2 DS - 100 300 e-/pixel Readout noise /G20*3 Nr - 100 200 e - rms Dynamic range DR - 1200 - - Photo response non-uniformity * 4 PRNU - ±3 ±10 % Spectral response range λ - 200 to 1100 - nm *1: TDI mode *2: Line rate 50 kHz, accumulated dark signal after 128-stage transfer *3: Readout frequency 30 MHz *4: Measured at one-half of the full well. In TDI mode. I Electrical characteristics (Ta=25 °C) Parameter Symbol Min. Typ. Max. Unit Signal output frequency fc - 30 40 MHz Reset clock frequency frg - 30 40 MHz S10200-02 - 250 - S10201-04 - 400 -Vertical shift register capacitance S10202-08/-16 CP1V , CP2V , CP3V - 650 - pF S10200-02 - 50 - S10201-04 - 50 - S10202-08 - 50 -Line rate S10202-16 LR - 100 - kHz S10200-02 - 50 - S10201-04 - 90 -Horizontal shift register capacitance S10202-08/-16 CP1H , CP2H -9 0- pF S10200-02 - 40 - S10201-04 - 60 -Transfer gate capacitance S10202-08/-16 CTG - 100 - pF S10200-02 - 20 - S10201-04 - 40 -Summing gate capacitance S10202-08/-16 CSG -4 0- pF S10200-02 - 20 - S10201-04 - 40 -Reset gate capacitance S10202-08/-16 CRG - 40 - pF Charge transfer efficiency * 5 CTE 0.99995 0.99999 - - Output level * 6 Vout - 6.5 - V Output impedance * 7 Zo - 300 - Ω Output MOSFET supply current/node Ido - 5 10 mA Power consumption * 6, *7 P- 7 5 - m W *5: Charge transfer efficiency per pixel, measured at half of the full well capacity. *6: V OD =15 V, Load resistance=2.2 k Ω *7: Power consumption of the on-chip amplifier plus load resistance.

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 I Device structure (Typical example: S10202-08) Conceptual drawing of top view OSb6 OSb7 OSb8 OSa6 OSa7 OSa8 THINNING V=128 H=512 × 8 (Number of ports) THINNING OSa1 OSa2 OSa3 OSb1 OSb2 OSb3

8 BLANK

512 PIXELS

128 TDI STAGE

P2Hb, SGb P1Hb TGb P1V P2V P3V TGa P1Ha P2Ha, SGa RGa OSa S510 S254 S511 S255 Tprr, Tpwr, Tpfr D2 D3..D8, S1..S509 D3..D8, S1..S253 S512 : S10200-02, S10201-04, S10202-08 S256 : S10202-16 Tprs, Tpws, Tpfs Tprh, Tpwh, TpfhTovr 518 262 519 263 520 264 S10200-02, S10201-04, S10202-08: S10202-16: 1 2 3 4..517 4..261 TovrvTprv, Tpwv, Tpfv

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 KMPDC0254EB A port side readout OSb RGb P2Hb, SGb P1Hb TGb P1V P2V P3V TGa P1Ha P2Ha, SGa RGa OSa S510 S254 S511 S255 D1 D2 D3..D8, S1..S509 D3..D8, S1..S253 S512 : S10200-02, S10201-04, S10202-08 S256 : S10202-16 518 262 519 263 520 : S10200-02, S10201-04, S10202-08 264 : S10202-16 4..517 4..261 123 Parameter Symbol Min. Typ. Max. Unit Pulse width Tpwv 120 770 - ns Rise and fall time Tprv, Tpfv 2 10 - nsP1V, 2V, 3V, TG Overlap time Tovrv 30 300 - ns Pulse width *8 Tpwh 12.5 16.5 - ns Rise and fall time *8 Tprh, Tpfh 3 6 - nsP1H, P2H Duty ratio *8 - - 50 - % Pulse width Tpws 12.5 16.5 - ns Rise and fall time Tprs, Tpfs 2 4 - nsSG Duty ratio - - 50 - % Pulse width Tpwr 5 6 - nsRG Rise and fall time Tprr, Tpfr 1 2 - ns TG - P1H Overlap time Tovr 30 1000 - ns *8: Symmetrical clock pulses should be overlapped at 50 % of maximum pulse amplitude. I Dimensional outlines (unit: mm) S10200-02 KMPDA0218EA ACTIVE AREA 12.288 27.94 ± 0.33 30.48 ± 0.35 40 21 INDEX MARK * Distance between window surface and photosensitive surface 10.16 ± 0.25 3 ± 0.1 9.91 ± 0.25 2.5 ± 0.1 ACTIVE AREA 1.536 3.3 ± 0.25 1.48 ± 0.15 * 0.25 +0.05 -0.03

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10201-04 KMPDA0219EA S10202-08/-16 KMPDA0220EA ACTIVE AREA 24.576 38.1 ± 0.43 40.64 ± 0.45 40 21 INDEX MARK 10.16 ± 0.25 3 ± 0.1 9.91 ± 0.25 2.5 ± 0.1 ACTIVE AREA 1.536 3.3 ± 0.25 1.48 ± 0.15 * 0.25 +0.05 -0.03 * Distance between window surface and photosensitive surface ACTIVE AREA 49.152 100 51 55 ± 0.1 63.5 ± 0.64 66.04 ± 0.66 9.91 ± 0.25 6.5 ± 0.1 2.5 ± 0.25 ACTIVE AREA 1.536 INDEX MARK 3 ± 0.3 0.8 ± 0.05 2.18 ± 0.2 * 2.2 ± 0.22 3.5 ± 0.35 0.25 +0.05 -0.03 10.16 ± 0.25 * Distance between window surface and photosensitive surface

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 I Pin connections S10200-02 S10201-04 Pin No. Symbol Function Pin No. Symbol Function 1P 2 V CCD vertical register clock-2 1P 2 V CCD vertical register clock-2

2 P3V CCD vertical register clock-3 2 P3V CCD vertical register clock-3

3P 1 V CCD vertical register clock-1 3P 1 V CCD vertical register clock-1

4 TGa Transfer gate-a 4 TGa Transfer gate-a

5D G N D Digital GND 5D G N D Digital GND

6 AGND Analog GND 6 AGND Analog GND

7- 7 O S a 1 Output transistor source-a1

8 OSa1 Output transistor source-a 1 8 OSa2 Output transistor source-a2

9O S a 2 Output transistor source-a 2 9O S a 3 Output transistor source-a3 10 - 10 OSa4 Output transistor source-a4

11 AGND Analog GND 11 AGND Analog GND

12 OD Output drain 12 OD Output drain

13 RD Reset drain 13 RD Reset drain

14 OG Output gate 14 OG Output gate

15 OFD Overflow drain 15 OFD Overflow drain

16 DGND Digital GND 16 DGND Digital GND

17 RGa Reset gate-a 17 RGa Reset gate-a

18 SGa Summing gate-a 18 SGa Summing gate-a

19 P1Ha CCD horizontal register-a

clock-/G50 19 P1Ha CCD horizontal register-a clock-/G50

20 P2Ha CCD horizontal register-a

clock-2 20 P2Ha CCD horizontal register-a clock-2

21 P2Hb CCD horizontal register-b

clock-2 21 P2Hb CCD horizontal register-b clock-2

22 P1Hb CCD horizontal register-b

clock-1 22 P1Hb CCD horizontal register-b clock-1

23 SGb Summing gate-b 23 SGb Summing gate-b

24 RGb Reset gate-b 24 RGb Reset gate-b

25 DGND Digital GND 25 DGND Digital GND

26 OFG Overflow gate 26 OFG Overflow gate

27 OG Output gate 27 OG Output gate

28 RD Reset drain 28 RD Reset drain

29 OD Output drain 29 OD Output drain

30 AGND Analog GND 30 AGND Analog GND

31 - 31 OSb4 Output transistor source-b4

32 OSb2 Output transistor source-b2 32 OSb3 Output transistor source-b3

33 OSb1 Output transistor source-b1 33 OSb2 Output transistor source-b2

34 - 34 OSb1 Output transistor source-b1

35 AGND Analog GND 35 AGND Analog GND

36 DGND Digital GND 36 DGND Digital GND

37 TGb Transfer gate-b 37 TGb Transfer gate-b

38 P1V CCD vertical register clock-1 38 P1V CCD vertical register clock-1

39 P3V CCD vertical register clock-3 39 P3V CCD vertical register clock-3

40 P2V CCD vertical register clock-2 40 P2V CCD vertical register clock-2

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10202-08 Pin No. Symbol Function Pin No. Symbol Function 1P 2 V CCD vertical register clock-2 51 P2V CCD vertical register clock-2

2 P3V CCD vertical register clock-3 52 P3V CCD vertical register clock-3

3P 1 V CCD vertical register clock-1 53 P1V CCD vertical register clock-1

4 TGa Transfer gate-a 54 TGb Transfer gate-b

5D G N D Digital GND 55 SGb2 Summing gate-b 2

6 OFG Overflow gate 56 RGb2 Reset gate-b 2

7O F D Overflow drain 57 DGND Digital GND

8 RD Reset drain 58 OFG Overflow gate

9O D Output drain 59 OFD Overflow drain

10 AGND Analog GND 60 OG Output gate

11 OSa1 Output transistor source-a1 61 RD Reset drain

13 OSa2 Output transistor source-a2 63 AGND Analog GND

15 OSa3 Output transistor source-a3 65 OSb8 Output transistor source-b8

17 OSa4 Output transistor source-a4 67 OSb7 Output transistor source-b7

19 AGND Analog GND 69 OSb6 Output transistor source-b6

20 OG Output gate 70 -

21 DGND Digital GND 71 OSb5 Output transistor source-b5

22 RGa1 Reset gate-a 1 72 AGND Analog GND

23 SGa1 Summing gate-a 1 73 DGND Digital GND

24 P1Ha1 CCD horizontal register-a1

clock-/G50 74 P1Hb2 CCD horizontal register-b2 clock-/G50

25 P2Ha1 CCD horizontal register-a1

clock-2 75 P2Hb2 CCD horizontal register-b2 clock-2

26 P2Ha2 CCD horizontal register-a2

clock-2 76 P2Hb1 CCD horizontal register-b1 clock-2

27 P1Ha2 CCD horizontal register-a2

clock-1 77 P1Hb1 CCD horizontal register-b1 clock-/G50

28 DGND Digital GND 78 SGb1 Summing gate-b 1

29 AGND Analog GND 79 RGb1 Reset gate-b 1

30 OSa5 Output transistor source-a5 80 DGND Digital GND

32 OSa6 Output transistor source-a6 82 AGND Analog GND

34 OSa7 Output transistor source-a7 84 OSb4 Output transistor source-b4

36 OSa8 Output transistor source-a8 86 OSb3 Output transistor source-b3

38 AGND Analog GND 88 OSb2 Output transistor source-b2

39 OD Output drain 89 -

40 RD Reset drain 90 OSb1 Output transistor source-b1

41 OG Output gate 91 AGND Analog GND

42 OFD Overflow drain 92 OD Output drain

43 OFG Overflow gate 93 RD Reset drain

44 DGND Digital GND 94 OFD Overflow drain

45 RGa2 Reset gate-a 2 95 OFG Overflow gate

46 SGa2 Summing gate-a 2 96 DGND Digital GND

47 TGa Transfer gate-a 97 TGb Transfer gate-b

48 P1V CCD vertical register clock-1 98 P1V CCD vertical register clock-1

49 P3V CCD vertical register clock-3 99 P3V CCD vertical register clock-3

50 P2V CCD vertical register clock-2 100 P2V CCD vertical register clock-2

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 S10202-16 Pin No. Symbol Function Pin No. Symbol Function 1P 2 V CCD vertical register clock-2 51 P2V CCD vertical register clock-2 3P 1 V CCD vertical register clock-1 53 P1V CCD vertical register clock-1 5D G N D Digital GND 55 SGb2 Summing gate-b 2 7O F D Overflow drain 57 DGND Digital GND 9O D Output drain 59 OFD Overflow drain

12 OSa2 Output transistor source-a2 62 OD Output drain

13 OSa3 Output transistor source-a3 63 AGND Analog GND

14 OSa4 Output transistor source-a4 64 OSb16 Output transistor source-b16

15 OSa5 Output transistor source-a5 65 OSb15 Output transistor source-b15

16 OSa6 Output transistor source-a6 66 OSb14 Output transistor source-b14

17 OSa7 Output transistor source-a7 67 OSb13 Output transistor source-b13

18 OSa8 Output transistor source-a8 68 OSb12 Output transistor source-b12

19 AGND Analog GND 69 OSb11 Output transistor source-b11

20 OG Output gate 70 OSb10 Output transistor source-b10

21 DGND Digital GND 71 OSb9 Output transistor source-b9

clock-/G50 74 P1Hb2 CCD horizontal register-b2 clock-/G50 clock-2 75 P2Hb2 CCD horizontal register-b2 clock-2 clock-2 76 P2Hb1 CCD horizontal register-b1 clock-2 clock-1 77 P1Hb1 CCD horizontal register-b1 clock-/G50

30 OSa9 Output transistor source-a9 80 DGND Digital GND

31 OSa10 Output transistor source-a10 81 OG Output gate

32 OSa11 Output transistor source-a11 82 AGND Analog GND

33 OSa12 Output transistor source-a12 83 OSb8 Output transistor source-b8

34 OSa13 Output transistor source-a13 84 OSb7 Output transistor source-b7

35 OSa14 Output transistor source-a14 85 OSb6 Output transistor source-b6

36 OSa15 Output transistor source-a15 86 OSb5 Output transistor source-b5

37 OSa16 Output transistor source-a16 87 OSb4 Output transistor source-b4

38 AGND Analog GND 88 OSb3 Output transistor source-b3

39 OD Output drain 89 OSb2 Output transistor source-b2

Back-thinned TDI-CCD S10200-02, S10201-04, S10202-08, S10202-16 HAMAMATSU PHOTONICS K.K., Solid State Division 1126-1 Ichino-cho, Hamamatsu City, 435-8558 Japan, Telephone: (81) 053-434-3311, Fax: (81) 053-434-5184, www.hamamatsu.com Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 08152-3750, Fax: (49) 08152-2658 France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10 United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777 North Europe: Hamamatsu Photonics Norden AB: Smidesvägen 12, SE-171 41 Solna, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01 Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1/E, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741 Information furnished by HAMAMATSU is believed to be reliable. However, no responsibility is assumed for possible inaccuracies or omissions. Specifications are subject to change without notice. No patent rights are granted to any of the circuits described herein. ©2007 Hamamatsu Photonics K.K. I Precaution for use (Electrostatic countermeasures) G Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth ring, in order to prevent electrostatic damage due to electrical charges from friction. G Avoid directly placing these sensors on a work-desk, etc. that may carry an electrostatic charge. G Provide ground lines or ground connection with the work-floor, work-desk and work-bench to allow static electricity to discharge. G Ground the tools used to handle these sensors, such as tweezers and soldering irons. It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of damage that occurs. Cat. No. KMPD1098E02 Apr. 2007 DN TDI camera C10000 series The TDI camera C10000 series is useful in a wide range of imaging applications that require both high speed and high sensitiv- ity, including in-line monitoring and inspec- tion. I Specifications Parameter C10000-301 C10000-401 Pixel number 1024 (H) × 128 (V) 2048 (H) × 128 (V) Device structure Back-thinned type Pixel size 12 µm (H) × 12 µm (V) Effective area 12.29 mm (H) × 1.536 mm (V) 24.58 mm (H) × 1.536 mm (V) TDI transfer direction Bi direction Readout mode TDI readout mode or Frame readout mode *9 TDI output channel 2 ports (512 × 2) 4 ports (512 × 4) Anti-blooming Lateral overflow drain (× 100) TDI pixel clock rate 30 MHz TDI line rate 0.45 kHz to 50 kHz Full-well capacity (Typ.) 100000 electrons Readout noise (Typ.) 130 electrons rms Dynamic range (Typ.) 770 : 1 A/D converter 12-bit / 8-bit *10 Image processing Real-time shading correction with internal DSP Lens mount C-mount F-mount Interface Base configuration Camera output clock 60 MHz Camera output channel 1 port (1024 × 1) 2 ports (1024 × 2) TDI line rate control Internal setting by serial command * 11 External trigger Analog enhancement gain 0 dB to 14 dB Power / Power consumption DC +12 V / 20 V · A Camera control Serial control in Camera link *9: Frame readout mode is useful for easy focusing, but it is not suitable for measurement. Please consult with our sales office for details. *10: Selectable by serial command. *11: Internal TDI line rate can be set in 33 ns steps.