RFD3055 HARRIS | Alldatasheet

Document overview

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Technical content

Features

  • 12A, 60V
  • r DS(ON) = 0.150Ω
  • Temperature Compensating PSPICE Model
  • Peak Current vs Pulse Width Curve
  • UIS Rating Curve
  • +175 oC Operating Temperature

Description

The RFD3055, RFD3055SM and RFP3055 N-Channel power MOSFETs are manufactured using the MegaFET pro- cess. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use in applications such as switching regula- tors, switching converters, motor drivers, relay drivers and emitter switches for bipolar transistors. These transistors can be operated directly from integrated circuits. The RFD3055 is supplied in the JEDEC TO-251AA plastic package, the RFD3055SM is supplied in the JEDEC TO-252AA plastic package and the RFP3055 is supplied in the JEDEC TO-220AB plastic package. Due to space limitations the RFD3055 and RFD3055SM are branded FD3055. When ordering use the entire part number; eg. RFD3055SM. Developmental type TA49082. February 1994 Absolute Maximum Ratings (TC = +25oC), Unless Otherwise Specified RFD3055, RFD3055SM, RFP3055 UNITS Drain Current D 12 A Power Dissipation File Number 3648

Specifications RFD3055, RFD3055SM, RFP3055 Electrical SpecificationsTC = +25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITSMIN TYP MAX Drain-Source Breakdown Voltage BV DSS ID = 0.25mA, VGS = 0V 60 - - V Gate Threshold Voltage V GS(TH) VGS = VDS , ID = 0.25mA 2 - 4 V Zero Gate Voltage Drain Current I DSS VDS = 60V, VGS = 0V TC = +25oC- - 1 µA TC = +150oC- -5 0 µA Gate-Source Leakage Current I GSS VGS =±20V - - 100 nA On Resistance r DS(ON) ID = 12A, VGS = 10V - - 0.150 W Turn-On Time t ON VDD = 30V, ID = 12A R L = 2.5Ω , VGS = +10V R GS = 10Ω - - 40 ns Turn-On Delay Time t D(ON) -7-n s Rise Time t R -2 1- n s Turn-Off Delay Time t D(OFF) -1 6- n s Fall Time t F -1 0- n s Turn-Off Time t OFF - - 40 ns Total Gate Charge Q G(TOT) VGS = 0 to 20V VDD = 48V, ID = 12A, R L = 4Ω -1 9 2 3n C Gate Charge at 10V Q G(10) VGS = 0 to 10V - 10 12 nC Threshold Gate Charge Q G(TH) VGS = 0 to 2V - 0.6 0.8 nC Plateau Voltage V (PLATEAU) ID = 12A, VDS = 15V - - 7.5 V Input Capacitance C ISS VDS = 25V, VGS = 0V f = 1MHz - 300 - pF Output Capacitance C OSS - 100 - pF Reverse Transfer Capacitance C RSS -3 0- p F Thermal Resistance Junction to Case R θJC - - 2.8 oC/W Thermal Resistance Junction to Ambient RθJA TO-251 and TO-252 Package - - 100 oC/W Source-Drain Diode Ratings and Characteristics PARAMETER SYMBOL TEST CONDITIONS LIMITS UNITSMIN TYP MAX Forward Voltage V SD ISD = 12A - - 1.5 V Reverse Recovery Time t RR ISD = 12A, dISD /dt = 100A/µs - - 100 ns

FIGURE 1. SAFE- OPERATING AREA CURVE FIGURE 2. NORMALIZED MAXIMUM TRANSIENT THERMAL FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs FIGURE 4. PEAK CURRENT CAPABILITY FIGURE 5. TYPICAL SATURATION CHARACTERISTICS FIGURE 6. TYPICAL TRANSFER CHARACTERISTICS

175 T C–

FIGURE 7. NORMALIZED R DS(ON) vs JUNCTION FIGURE 8. NORMALIZED GATE THRESHOLD VOLTAGE vs FIGURE 9. NORMALIZED DRAIN SOURCE BREAKDOWN FIGURE 10. NORMALIZED POWER DISSIPATION vs FIGURE 11. TYPICAL CAPACITANCE vs VOLTAGE FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR

0.75 BVDSS

0.50 BVDSS

0.25 BVDSS

RFD3055, RFD3055SM, RFP3055 PSpice Model Listing Temperature Compensated PSPICE Model for the RFD3055, RFD3055SM, RFP3055 .SUBCKT RFP3055 2 1 3 ; rev 10/26/93 CA 12 8 0.540e-9 CB 15 14 0.540e-9 CIN 6 8 0.300e-9 DBODY 7 5 DBDMOD DBREAK 5 11 DBKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 67.9 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTO 20 6 18 8 1 IT 8 17 1 LDRAIN 2 5 1e-9 LGATE 1 9 4.61e-9 LSOURCE 3 7 4.61e-9 MOS1 16 6 8 8 MOSMOD M=0.99 MOS2 16 21 8 8 MOSMOD M=0.01 RBREAK 17 18 RBKMOD 1 RDRAIN 50 16 RDSMOD 1e-4 RGATE 9 20 7.23 RIN 6 8 1e9 RSCL1 5 51 RSLVCMOD 1e-6 RSCL2 5 50 1e3 RSOURCE 8 7 RDSMOD 108e-3 RVTO 18 19 RVTOMOD 1 S1A 6 12 13 8 S1AMOD S1B 13 12 13 8 S1BMOD S2A 6 15 14 13 S2AMOD S2B 13 15 14 13 S2BMOD VBAT 8 19 DC 1 VTO 21 6 0.5 ESCL 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/30,6.5))} .MODEL DBKMOD D (RS=0.676 TRS1=1.94e-3 TRS2=-1.09e-6) .MODEL DPLCAPMOD D (CJO=0.238e-9 IS=1e-30 N=10) .MODEL MOSMOD NMOS (VTO=4.078 KP=12 IS=1e-30 N=10 TOX=1 L=1u W=1u) .MODEL RBKMOD RES (TC1=1.06e-3 TC2=-1.92e-6) .MODEL RDSMOD RES (TC1=5.03e-3 TC2=1.53e-5) .MODEL RSLVCMOD RES (TC1=2.2e-3 TC2=-5e-6) .MODEL RVTOMOD RES (TC1=-5.02e-3 TC2=-9.16e-6) .MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.5 VOFF=-3.5) .MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-6.5) .MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.50 VOFF=2.50) .MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.50 VOFF=-2.50) .ENDS NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFet Featuring Global Temperature Options; authored by William J. Hepp and C. Frank Wheatley. GATE LGATE RGATE EVTO 12 13 S1A S1B S2A S2B CA CB EGS EDS R IN C IN MOS1 MOS2 RDRAIN DBREAK EBREAK DBODY LDRAIN DRAIN RSOURCE LSOURCE SOURCE RBREAK RVTO VBAT IT VTO ESG DPLCAP ESCL RSCL1 RSCL2 17 18

RFD3055, RFD3055SM, RFP3055 Packaging EØP Q D H 1 L 60o b 1 2 3 e A c 45o D 1 A 1 TERM. 4 TO-220AB

3 LEAD JEDEC TO-220AB PLASTIC PACKAGE

A 0.170 0.180 4.32 4.57 - A1 0.048 0.052 1.22 1.32 - b 0.030 0.034 0.77 0.86 3, 4 b1 0.045 0.055 1.15 1.39 2, 3 c 0.014 0.019 0.36 0.48 2, 3, 4 D 0.590 0.610 14.99 15.49 - D 1 - 0.160 - 4.06 - E 0.395 0.410 10.04 10.41 - e 0.100 TYP 2.54 TYP 5 e1 0.200 BSC 5.08 BSC 5 H 1 0.235 0.255 5.97 6.47 - J1 0.100 0.110 2.54 2.79 6 L 0.530 0.550 13.47 13.97 - L1 0.130 0.150 3.31 3.81 2 ØP 0.149 0.153 3.79 3.88 - Q 0.102 0.112 2.60 2.84 - NOTES: 1. These dimensions are within allowable dimensions of Rev. J of JEDEC TO-220AB outline dated 3-24-87. 2. Lead dimension and finish uncontrolled in L1. 3. Lead dimension (without solder). 4. Add typically 0.002 inches (0.05mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bot- tom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bot- tom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93. E A c SEATING D L b e 12 3 H 1 A 1 TERM. 4 PLANE TO-251AA

3 LEAD JEDEC TO-251AA PLASTIC PACKAGE

A 0.086 0.094 2.19 2.38 - A1 0.018 0.022 0.46 0.55 3, 4 b 0.028 0.032 0.72 0.81 3, 4 b1 0.033 0.040 0.84 1.01 3 b2 0.205 0.215 5.21 5.46 3, 4 c 0.018 0.022 0.46 0.55 3, 4 D 0.270 0.290 6.86 7.36 - E 0.250 0.265 6.35 6.73 - e 0.090 TYP 2.28 TYP 5 e1 0.180 BSC 4.57 BSC 5 H 1 0.035 0.045 0.89 1.14 - J1 0.040 0.045 1.02 1.14 6 L 0.355 0.375 9.02 9.52 - L1 0.075 0.090 1.91 2.28 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. C of JEDEC TO-251AA outline dated 9-88. 2. Solder finish uncontrolled. 3. Dimension (without solder). 4. Add typically 0.0006 inches (0.015mm) for solder coating. 5. Position of lead to be measured 0.250 inches (6.35mm) from bot- tom of dimension D. 6. Position of lead to be measured 0.100 inches (2.54mm) from bot- tom of dimension D. 7. Controlling dimension: Inch. 8. Revision 1 dated 1-93.

Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries. Sales Office Headquarters For general information regarding Harris Semiconductor and its products, call1-800-4-HARRIS UNITED STATES Harris Semiconductor P. O. Box 883, Mail Stop 53-210 Melbourne, FL 32902 TEL: 1-800-442-7747 (407) 729-4984 FAX: (407) 729-5321 EUROPE Harris Semiconductor Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2-724-2111 SOUTH ASIA Harris Semiconductor H.K. Ltd. 13/F Fourseas Building 208-212 Nathan Road Tsimshatsui, Kowloon Hong Kong TEL: (852) 723-6339 NORTH ASIA Harris K.K. Kojimachi-Nakata Bldg. 4F 5-3-5 Kojimachi Chiyoda-ku, Tokyo 102 Japan TEL: (81) 3-3265-7571 TEL: (81) 3-3265-7572 (Sales) SEMICONDUCTOR RFD3055, RFD3055SM, RFP3055 Packaging (Continued) E D L e b1b A L c SEATING BACK VIEW H 1 A 1 e1 J1 TERM. 4 0.265 MINIMUM PAD SIZE RECOMMENDED FOR SURFACE-MOUNTED APPLICATIONS (6.7) 0.265 (6.7) 0.070 (1.8) 0.118 (3.0) 0.063 (1.6) 0.090 (2.3) 0.063 (1.6) 0.090 (2.3) PLANE TO-252AA

2 LEAD JEDEC TO-252AA PLASTIC PACKAGE

A 0.086 0.094 2.19 2.38 - A1 0.018 0.022 0.46 0.55 4, 5 b 0.028 0.032 0.72 0.81 4, 5 b1 0.033 0.040 0.84 1.01 4 b2 0.205 0.215 5.21 5.46 4, 5 b3 0.190 - 4.83 - 2 c 0.018 0.022 0.46 0.55 4, 5 D 0.270 0.290 6.86 7.36 - E 0.250 0.265 6.35 6.73 - e 0.090 TYP 2.28 TYP 7 e1 0.180 BSC 4.57 BSC 7 H 1 0.035 0.045 0.89 1.14 - J1 0.040 0.045 1.02 1.14 - L 0.100 0.115 2.54 2.92 - L1 0.075 0.090 1.91 2.28 3 L2 0.025 0.040 0.64 1.01 - L3 0.020 - 0.51 - 4, 6 L4 0.170 - 4.32 - 2 NOTES: 1. These dimensions are within allowable dimensions of Rev. B of JEDEC TO-252AA outline dated 9-88. 2. L4 and b3 dimensions establish a minimum mounting surface for terminal 4. 3. Solder finish uncontrolled. 4. Dimension (without solder). 5. Add typically 0.0006 inches (0.015mm) for solder coating. 6. L 3 is the terminal length for soldering. 7. Position of lead to be measured 0.090 inches (2.28mm) from bottom of dimension D. 8. Controlling dimension: Inch. 9. Revision 2 dated 6-93.