82C37 HARRIS | Alldatasheet
Document overview
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Technical content
Features
- Compatible with the NMOS 8237A
- Four Independent Maskable Channels with Autoinitial- ization Capability
- Cascadable to any Number of Channels
- High Speed Data Transfers: - Up to 4MBytes/sec with 8MHz Clock - Up to 6.25MBytes/sec with 12.5MHz Clock
- Memory-to-Memory Transfers
- Static CMOS Design Permits Low Power Operation - ICCSB = 10µA Maximum - ICCOP = 2mA/MHz Maximum
- Fully TTL/CMOS Compatible
- Internal Registers may be Read from Software
Description
The 82C37A is an enhanced version of the industry standard 8237A Direct Memory Access (DMA) controller, fabricated using Harris’ advanced 2 micron CMOS process. Pin compatible with NMOS designs, the 82C37A offers increased functionality, improved performance, and dramatically reduced power consumption. The fully static design permits gated clock operation for even further reduction of power. The 82C37A controller can improve system performance by allowing external devices to transfer data directly to or from system memory. Memory-to-memory transfer capability is also provided, along with a memory block initialization fea- ture. DMA requests may be generated by either hardware or software, and each channel is independently programmable with a variety of features for flexible operation. The 82C37A is designed to be used with an external address latch, such as the 82C82, to demultiplex the most significant 8-bits of address. The 82C37A can be used with industry standard microprocessors such as 80C286, 80286, 80C86, 80C88, 8086, 8088, 8085, Z80, NSC800, 80186 and others. Multimode programmability allows the user to select from three basic types of DMA services, and reconfiguration under program control is possible even with the clock to the controller stopped. Each channel has a full 64K address and word count range, and may be programmed to autoinitialize these registers following DMA termination (end of process).
Ordering Information
RANGE PKG. NO.5MHz 8MHz 12.5MHz CP82C37A-5 CP82C37A CP82C37A-12 40 Ld PDIP 0 oC to +70oC E40.6 IP82C37A-5 IP82C37A IP82C37A-12 -40 oC to +85oC E40.6 CS82C37A-5 CS82C37A CS82C37A-12 44 Ld PLCC 0 oC to +70oC N44.65 IS82C37A-5 IS82C37A IS82C37A-12 -40 oC to +85oC N44.65 CD82C37A-5 CD82C37A CD82C37A-12 40 Ld CERDIP 0 oC to +70oC F40.6 ID82C37A-5 ID82C37A ID82C37A-12 -40 oC to +85oC F40.6 MD82C37A-5/B MD82C37A/B MD82C37A-12/B -55 oC to +125oC F40.6 5962-9054301MQA 5962-9054302MQA 5962-9054303MQA SMD# F40.6 MR82C37A-5/B MR82C37A/B MR82C37A-12/B 44 Pad CLCC -55 oC to +125oC J44.A 5962-9054301MXA 5962-9054302MXA 5962-9054303MXA SMD# J44.A CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 File Number 2967.1
82C37A (PDIP/CERDIP) TOP VIEW 82C37A (CLCC/PLCC) TOP VIEW IOR IOW MEMR MEMW NC READY HLDA ADSTB AEN HRQ CS CLK RESET DACK2 DACK3 DREQ3 DREQ2 DREQ1 DREQ0 (GND) VSS EOP VCC DB0 DB1 DB2 DB3 DB4 DACK0 DACK1 DB5 DB6 DB7 46 3 1 4041424344 2827262524232221201918 CS DACK2 NC NC CLK HRQ NC VCC DB0 DB1 DB2 DB3 NC DB4 READY NC MEMW EOP DACK3 DREQ3 DREQ2 DREQ1 DREQ0 GND DB5 DACK1 DB7 DACK0 DB6 MEMR ADSTB AEN IOW RESET HLDA IOR A4 - A7 EOP RESET CS READY CLK AEN ADSTB MEMR MEMW IOR IOW TIMING AND CONTROL DREQ0 - HLDA HRQ DACK0 - PRIORITY ENCODER AND ROTATING PRIORITY LOGIC DACK3 DREQ3
4 COMMAND
(8) MASK (4) REQUEST (4) MODE (4 x 6) STATUS (8) TEMPORARY (8) INTERNAL DATA BUS DECREMENTOR COUNT REG (16) TEMP WORD INC/DECREMENTOR REG (16) TEMP ADDRESS BUFFER IO 16-BIT BUS READ BUFFER ADDRESS BASE (16) WORD BASE COUNT (16) READ WRITE BUFFER ADDRESS CURRENT (16) WORD CURRENT COUNT (16) 16-BIT BUS BUFFER WRITE BUFFER READ A8 - A15 BUFFER OUTPUT CONTROL COMMAND D0 - D1 A0 - A3 BUFFER IODB0 - DB7
VCC 31 V CC : is the +5V power supply pin. A 0.1µF capacitor between pins 31 and 20 is recommended for decoupling. GND 20 Ground CLK 12 I CLOCK INPUT: The Clock Input is used to generate the timing signals which control 82C37A operations. This input may be driven from DC to 12.5MHz for the 82C37A-12, from DC to 8MHz for the 82C37A, or from DC to 5MHz for the 82C37A-5. The Clock may be stopped in either state for standby operation. CS 11 I CHIP SELECT: Chip Select is an active low input used to enable the controller onto the data bus for CPU communications. RESET 13 I RESET: This is an active high input which clears the Command, Status, Request, and Temporary registers, the First/Last Flip-Flop, and the mode register counter. The Mask register is set to ignore requests. Following a Reset, the controller is in an idle cycle. READY 6 I READY: This signal can be used to extend the memory read and write pulses from the 82C37A to accommodate slow memories or I/O devices. READY must not make transitions during its specified set-up and hold times. See Figure 12 for timing. READY is ignored in verify transfer mode. HLDA 7 I HOLD ACKNOWLEDGE: The active high Hold Acknowledge from the CPU indicates that it has relinquished control of the system busses. HLDA is a synchronous input and must not transition during its specified set-up time. There is an implied hold time (HLDA inactive) of TCH from the rising edge of CLK, during which time HLDA must not transition. DREQ0- DREQ3 16-19 I DMA REQUEST: The DMA Request (DREQ) lines are individual asynchronous channel request inputs used by peripheral circuits to obtain DMA service. In Fixed Priority, DREQ0 has the highest priority and DREQ3 has the lowest priority. A request is generated by activating the DREQ line of a channel. DACK will acknowledge the recognition of a DREQ signal. Polarity of DREQ is programmable. RESET initializes these lines to active high. DREQ must be maintained until the corresponding DACK goes active. DREQ will not be recognized while the clock is stopped. Unused DREQ inputs should be pulled High or Low (inactive) and the corresponding mask bit set. DB0-DB7 21-23 26-30 I/O DATA BUS: The Data Bus lines are bidirectional three-state signals connected to the system data bus. The outputs are enabled in the Program condition during the I/O Read to output the contents of a register to the CPU. The outputs are disabled and the inputs are read during an I/O Write cycle when the CPU is programming the 82C37A control registers. During DMA cycles, the most signifi- cant 8-bits of the address are output onto the data bus to be strobed into an external latch by ADSTB. In memory-to-memory operations, data from the memory enters the 82C37A on the data bus during the read-from-memory transfer, then during the write-to-memory transfer, the data bus outputs write the data into the new memory location. IOR 1 I/O I/O READ: I/O Read is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to read the control registers. In the Active cycle, it is an output control signal used by the 82C37A to access data from the peripheral during a DMA Write transfer. IOW 2 I/O I/O WRITE: I/O Write is a bidirectional active low three-state line. In the Idle cycle, it is an input con- trol signal used by the CPU to load information into the 82C37A. In the Active cycle, it is an output control signal used by the 82C37A to load data to the peripheral during a DMA Read transfer.
EOP 36 I/O END OF PROCESS: End of Process ( EOP) is an active low bidirectional signal. Information concerning the completion of DMA services is available at the bidirectionalEOP pin. The 82C37A allows an external signal to terminate an active DMA service by pulling theEOP pin low. A pulse is generated by the 82C37A when terminal count (TC) for any channel is reached, except for channel 0 in memory-to-memory mode. During memory-to-memory transfers, EOP will be output when the TC for channel 1 occurs. The EOP pin is driven by an open drain transistor on-chip, and requires an external pull-up resistor to VCC . When an EOP pulse occurs, whether internally or externally generated, the 82C37A will terminate the service, and if autoinitialize is enabled, the base registers will be written to the current registers of that channel. The mask bit and TC bit in the status word will be set for the currently active channel by EOP unless the channel is programmed for autoinitialize. In that case, the mask bit remains clear. A0-A3 32-35 I/O ADDRESS: The four least significant address lines are bidirectional three-state signals. In the Idle cycle, they are inputs and are used by the 82C37A to address the control register to be loaded or read. In the Active cycle, they are outputs and provide the lower 4-bits of the output address. A4-A7 37-40 O ADDRESS: The four most significant address lines are three-state outputs and provide 4-bits of address. These lines are enabled only during the DMA service. HRQ 10 O HOLD REQUEST: The Hold Request (HRQ) output is used to request control of the system bus. When a DREQ occurs and the corresponding mask bit is clear, or a software DMA request is made, the 82C37A issues HRQ. The HLDA signal then informs the controller when access to the system busses is permitted. For stand-alone operation where the 82C37A always controls the busses, HRQ may be tied to HLDA. This will result in one S0 state before the transfer. DACK0- DACK3 14, 15 24, 25 O DMA ACKNOWLEDGE: DMA acknowledge is used to notify the individual peripherals when one has been granted a DMA cycle. The sense of these lines is programmable. RESET initializes them to active low. AEN 9 O ADDRESS ENABLE: Address Enable enables the 8-bit latch containing the upper 8 address bits onto the system address bus. AEN can also be used to disable other system bus drivers during DMA transfers. AEN is active high. ADSTB 8 O ADDRESS STROBE: This is an active high signal used to control latching of the upper address byte. It will drive directly the strobe input of external transparent octal latches, such as the 82C82. During block operations, ADSTB will only be issued when the upper address byte must be updated, thus speeding operation through elimination of S1 states. ADSTB timing is referenced to the falling edge of the 82C37A clock. MEMR 3 O MEMORY READ: The Memory Read signal is an active low three-state output used to access data from the selected memory location during a DMA Read or a memory-to-memory transfer. MEMW 4 O MEMORY WRITE: The Memory Write signal is an active low three-state output used to write data to the selected memory location during a DMA Write or a memory-to-memory transfer. NC 5 NO CONNECT: Pin 5 is open and should not be tested for continuity. Pin Description (Continued) SYMBOL PIN NUMBER TYPE DESCRIPTION
The 82C37A can assume seven separate states, each composed of one full clock period. State I (SI) is the idle state. It is entered when the 82C37A has no valid DMA requests pending, at the end of a transfer sequence, or when a Reset or Master Clear has occurred. While in SI, the DMA controller is inactive but may be in the Program Condition (being programmed by the processor). State 0 (S0) is the first state of a DMA service. The 82C37A has requested a hold but the processor has not yet returned an acknowledge. The 82C37A may still be programmed until it has received HLDA from the CPU. An acknowledge from the CPU will signal the DMA transfer may begin. S1, S2, S3, and S4 are the working state of the DMA service. If more time is needed to complete a transfer than is available with normal timing, wait states (SW) can be inserted between S3 and S4 in normal transfers by the use of the Ready line on the 82C37A. For compressed transfers, wait states can be inserted between S2 and S4. See timing Figures 14 and 15. Note that the data is transferred directly from the I/O device to memory (or vice versa) with IOR and MEMW (or MEMR and IOW) being active at the same time. The data is not read into or driven out of the 82C37A in I/O-to-memory or memory-to-I/O DMA transfers. Memory-to-memory transfers require a read-from and a write- to memory to complete each transfer. The states, which resemble the normal working states, use two-digit numbers for identification. Eight states are required for a single transfer. The first four states (S11, S12, S13, S14) are used for the read-from-memory half and the last four state (S21, S22, S23, S24) for the write-to-memory half of the transfer. Idle Cycle When no channel is requesting service, the 82C37A will enter the idle cycle and perform “SI” states. In this cycle, the 82C37A will sample the DREQ lines on the falling edge of every clock cycle to determine if any channel is requesting a DMA service. Note that for standby operation where the clock has been stopped, DMA requests will be ignored. The device will respond to CS (chip select), in case of an attempt by the microprocessor to write or read the internal registers of the 82C37A. When CS is low and HLDA is low, the 82C37A enters the Program Condition. The CPU can now establish, change or inspect the internal definition of the part by read- ing from or writing to the internal registers. The 82C37A may be programmed with the clock stopped, pro- vided that HLDA is low and at least one rising clock edge has occurred after HLDA was driven low, so the controller is in an SI state. Address lines A0-A3 are inputs to the device and select which registers will be read or written. The IOR and IOW lines are used to select and time the read or write operations. Due to the number and size of the internal registers, an internal flip-flop called the First/Last Flip-Flop is used to generate an additional bit of address. The bit is used to determine the upper or lower byte of the 16-bit Address and Work Count registers. The flip- flop is reset by Master Clear or RESET. Separate software commands can also set or reset this flip-flop. Special software commands can be executed by the 82C37A in the Program Condition. These commands are decoded as sets of addresses with CS, IOR, andIOW. The commands do not make use of the data bus. Instructions include Set and Clear First/Last Flip-Flop, Master Clear, Clear Mode Register Counter, and Clear Mask Register. Active Cycle When the 82C37A is in the Idle cycle, and a software request or an unmasked channel requests a DMA service, the device will issue HRQ to the microprocessor and enter the Active cycle. It is in this cycle that the DMA service will take place, in one of four modes: Single Transfer Mode -In Single Transfer mode, the device is programmed to make one transfer only. The word count will be decremented and the address decremented or incremented following each transfer. When the word count “rolls over” from zero to FFFFH, a terminal count bit in the status register is set, an EOP pulse is generated, and the channel will autoinitialize if this option has been selected. If not programmed to autoinitialize, the mask bit will be set, along with the TC bit and EOP pulse. DREQ must be held active until DACK becomes active. If DREQ is held active throughout the single transfer, HRQ will go inactive and release the bus to the system. It will again go active and, upon receipt of a new HLDA, another single transfer will be performed, unless a higher priority channel takes over. In 8080A, 8085A, 80C88, or 80C86 systems, this will ensure one full machine cycle execution between DMA transfers. Details of timing between the 82C37A and other bus control protocols will depend upon the characteristics of the microprocessor involved. Block Transfer Mode -In Block Transfer mode, the device is activated by DREQ or software request and continues making transfers during the service until a TC, caused by word count going to FFFFH, or an external End of Process EOP) is encountered. DREQ need only be held active until DACK becomes active. Again, an Autoinitialization will occur at the end of the service if the channel has been programmed for that option. Demand Transfer Mode -In Demand Transfer mode the device continues making transfers until a TC or external EOP is encountered, or until DREQ goes inactive. Thus, transfer may continue until the I/O device has exhausted its data capacity. After the I/O device has had a chance to catch up, the DMA service is reestablished by means of a DREQ. During the time between services when the microprocessor is allowed to oper- ate, the intermediate values of address and word count are stored in the 82C37A Current Address and Current Word Count registers. Higher priority channels may intervene in the demand process, once DREQ has gone inactive. Only an EOP can cause an Autoinitialization at the end of service. EOP is generated either by TC or by an external signal. Cascade Mode -This mode is used to cascade more than one 82C37A for simple system expansion. The HRQ and HLDA signals from the additional 82C37A are connected to the DREQ and DACK signals respectively of a channel for
Current Word Count Register - Each channel has a 16-bit Current Word Count register. This register determines the number of transfers to be performed. The actual number of transfers will be one more than the number programmed in the Current Word Count register (i.e., programming a count of 100 will result in 101 transfers). The word count is decremented after each transfer. When the value in the register goes from zero to FFFFH, a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. See Figure 6 for programming information. Following the end of a DMA service it may also be reinitialized by an Autoinitialization back to its original value. Autoinitialization can occur only when an EOP occurs. If it is not Autoinitialized, this register will have a count of FFFFH after TC. Base Address and Base Word Count Registers - Each channel has a pair of Base Address and Base Word Count registers. These 16-bit registers store the original value of their associated current registers. During Autoinitialize these values are used to restore the current registers to their original values. The base registers are written simulta- neously with their corresponding current register in 8-bit bytes in the Program Condition by the microprocessor. See Figure 6 for programming information. These registers can- not be read by the microprocessor. Command Register - This 8-bit register controls the opera- tion of the 82C37A. It is programmed by the microprocessor and is cleared by RESET or a Master Clear instruction. The following diagram lists the function of the Command register bits. See Figure 4 for Read and Write addresses. Mode Register - Each channel has a 6-bit Mode register associated with it. When the register is being written to by the microprocessor in the Program condition, bits 0 and 1 determine which channel Mode register is to be written. When the processor reads a Mode register, bits 0 and 1 will both be ones. See the following diagram and Figure 4 for Mode register functions and addresses. Request Register - The 82C37A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are non-maskable and subject to prioritization by the Priority Encoder network. Each register bit is set or reset separately under software control. The entire register is cleared by a Reset or Master Clear instruction. To set or reset a bit, the software loads the proper form of the data word. See Figure 4 for register address coding, and the following diagram for Request register format. A software request for DMA operation can be made in block or single modes. For memory-to-memory transfers, the software request for channel 0 should be set. When reading the Request register, bits 4-7 will always read as ones, and bits 0-3 will display the request bits of channels 0-3 respectively. Command Register
76543210 BIT NUMBER
X Channel 0 address hold disable Channel 0 address hold enable If bit 0 = 0 Controller enable Controller disable X Normal timing Compressed timing If bit 0 = 1 Fixed priority Rotating priority X Late write selection Extended write selection If bit 3 = 1 DREQ sense active high DREQ sense active low DACK sense active low DACK sense active high Mode Register If bits 6 and 7 = 11 Autoinitialization disable Autoinitialization enable Address increment select Address decrement select Demand mode select Single mode select Block mode select Cascade mode select Request Register Don’t Care, Write Bits 4-7 All Ones, Read
ister command (see software commands section). 4-7 are cleared upon RESET or Master Clear.
1 Channel 0 has reached TC
1 Channel 1 has reached TC
1 Channel 2 has reached TC
1 Channel 3 has reached TC
1 Channel 0 request
1 Channel 1 request
1 Channel 2 request
1 Channel 3 request
FIGURE 4. SOFTWARE COMMAND CODES AND REGISTER CODES
read type commands, the data value is not guaranteed. upper and lower bytes in the correct sequence. address and word count registers. is set. The 82C37A will enter the idle cycle. of all four channels, enabling them to accept DMA requests. all Mode registers will read as ones. driven by external signals to terminate DMA operation. will not be recognized, since the 82C37A is in an SI state.
0 Base and Current Address Write 0100000 0 A0-A7
1 Base and Current Address Write 0100010 0 A0-A7
2 Base and Current Address Write 0100100 0 A0-A7
3 Base and Current Address Write 0100110 0 A0-A7
00101101 A8-A15
01001111 W8-W15
00101111 W8-W15
FIGURE 5. WORD COUNT AND ADDRESS REGISTER COMMAND CODES
Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W) oC to +150oC Maximum Lead Temperature Package (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -40oC to +85oC (I82C37A) TA = -55oC to +125oC (M82C37A) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2 - v C82C37A, I82C37A 2.2 - V M82C37A VIL Logical Zero Input Voltage - 0.8 V VIHC CLK Input Logical One Voltage V CC -0.8 - V VILC CLK Input Logical Zero Voltage - 0.8 V VOH Output HIGH Voltage 3.0 - V IOH = -2.5mA VCC -0.4 - V IOH = -100 µA VOL Output LOW Voltage - 0.4 V IOL = +2.5mA all output except EOP, IOL = +3.2mA forEOP pin 36 only. II Input Leakage Current -1 +1 µA VIN = GND or V CC , Pins 6, 7, 11-13, 16-19 IO Output Leakage Current -10 +10 µA VOUT = GND or V CC , Pins 1-4, 21-23, 26-30, 32-40 ICCSB Standby Power Supply Current -1 0 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open ICCOP Operating Power Supply Current - 2 mA/MHz V CC = 5.5V, CLK FREQ = Maximum, VIN = VCC or GND, Outputs Open Capacitance TA = +25oC SYMBOL PARAMETER TYP UNITS TEST CONDITIONS CIN Input Capacitance 25 pF FREQ = 1MHz, All measurements are referenced to device GND COUT Output Capacitance 40 pF CI/O I/O Capacitance 25 pF
TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX DMA (MASTER) MODE (1)TAEL AEN HIGH from CLK LOW (S1) Delay Time - 175 - 105 - 50 ns (2)TAET AEN LOW from CLK HIGH (SI) Delay Time - 130 - 80 - 50 ns (3)TAFAB ADR Active to Float Delay from CLK HIGH -9 0 -5 5-5 5 n s (4)TAFC READ or WRITE Float Delay from CLK HIGH - 120 - 75 - 50 ns (5)TAFDB DB Active to Float Delay from CLK HIGH - 170 - 135 - 90 ns (6)TAHR ADR from READ HIGH Hold Time TCY-100 - TCY-75 - TCY-65 - ns (7)TAHS DB from ADSTB LOW Hold Time TCL-18 - TCL-18 - TCL-18 - ns (8)TAHW ADR from WRITE HIGH Hold Time TCY-65 - TCY-65 - TCY-50 - ns (9)TAK DACK Valid from CLK LOW Delay Time - 170 - 105 - 69 ns EOP HIGH from CLK HIGH Delay Time - 170 - 105 - 90 ns EOP LOW from CLK HIGH Delay Time - 100 - 60 - 35 ns (10)TASM ADR Stable from CLK HIGH - 110 - 60 - 50 ns (11)TASS DB to ADSTB LOW Setup Time TCH-20 - TCH-20 - TCH-20 - ns (12)TCH CLK HIGH Time (Transitions 10ns) 70 - 55 - 30 - ns (13)TCL CLK LOW Time (Transitions 10ns) 50 - 43 - 30 - ns (14)TCY CLK Cycle Time 200 - 125 - 80 - ns (15)TDCL CLK HIGH to READ or WRITE LOW Delay - 190 - 130 - 120 ns (16)TDCTR READ HIGH from CLK HIGH (S4) Delay Time - 190 - 115 - 80 ns (17)TDCTW WRITE HIGH from CLK HIGH (S4) Delay Time - 130 - 80 - 70 ns (18)TDQ HRQ Valid from CLK HIGH Delay Time - 120 - 75 - 30 ns (19)TEPH EOP Hold Time from CLK LOW (S2) 90 - 90 - 50 - ns (20)TEPS EOP LOW to CLK LOW Setup Time 40 - 25 - 0 - ns
(21)TEPW EOP Pulse Width 220 - 135 - 50 - ns (22)TFAAB ADR Valid Delay from CLK HIGH - 110 - 60 - 50 ns (23)TFAC READ or WRITE Active from CLK HIGH - 150 - 90 - 50 ns (24)TFADB DB Valid Delay from CLK HIGH - 110 - 60 - 45 ns (25)THS HLDA Valid to CLK HIGH Setup Time 75 - 45 - 10 - ns (26)TIDH Input Data from MEMR HIGH Hold Time 0- 0-0- n s (27)TIDS Input Data to MEMR HIGH Setup Time 155 - 90 - 45 - ns (28)TODH Output Data from MEMW HIGH Hold Time 15 - 15 - TCY-50 - ns (29)TODV Output Data Valid to MEMW HIGH TCY-35 - TCY-35 - TCY-10 - ns (30)TQS DREQ to CLK LOW (SI, S4) Setup Time 0- 0-0- n s (31)TRH CLK to READY LOW Hold Time 20 - 20 - 10 - ns (32)TRS READY to CLK LOW Setup Time 60 - 35 - 15 - ns (33)TCLSH ADSTB HIGH from CLK LOW Delay Time -8 0 -7 0-7 0 n s (34)TCLSL ADSTB LOW from CLK LOW Delay Time - 120 - 120 - 60 ns (35)TWRRD READ HIGH Delay fromWRITE HIGH 0 - 0 - 5 - ns (36)TRLRH READ Pulse Width, Normal Timing 2TCY-60 - 2TCY-60 - 2TCY-55 - ns (37)TSHSL ADSTB Pulse Width TCY-80 - TCY-50 - TCY-35 - ns (38)TWLWHA Extended WRITE Pulse Width 2TCY-100 - 2TCY-85 - 2TCY-80 - ns (39)TWLWH WRITE Pulse Width TCY-100 - TCY-85 - TCY-80 - ns (40)TRLRHC READ Pulse Width, Compressed TCY-60 - TCY-60 - TCY-55 - ns (56)TAVRL ADR Valid to READ LOW 17 - 17 - 17 - ns (57)TAVWL ADR Valid to WRITE LOW 7 - 7 - 7 - ns (58)TRHAL READ HIGH to AEN LOW 15 - 15 - 15 - ns (59)TRHSH READ HIGH to ADSTB HIGH 13 - 13 - 13 - ns (60)TWHSH WRITE HIGH to ADSTB HIGH 15 - 15 - 15 - ns (61)TDVRL DACK Valid to READ LOW 25 - 25 - 25 - ns TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) (Continued) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX
(62)TDVWL DACK Valid to WRITE LOW 25 - 25 - 25 - ns (63)TRHDI READ HIGH to DACK Inactive 12 - 12 - 12 - ns (64)TAZRL ADR Float to READ LOW -2.5 - -2.5 - -2.5 - ns PERIPHERAL (SLAVE) MODE (41)TAR ADR Valid or CS LOW to READ LOW 10 - 10 - 0 - ns (42)TAWL ADR Valid to WRITE LOW Setup Time 0 - 0 - 0 - ns (43)TCWL CS LOW to WRITE LOW Setup Time 0 - 0 - 0 - ns (44)TDW Data Valid to WRITE HIGH Setup Time 150 - 100 - 60 - ns (45)TRA ADR or CS Hold fromREAD HIGH 0 - 0 - 0 - ns (46)TRDE Data Access from READ - 140 - 120 - 80 ns (47)TRDF DB Float Delay from READ HIGH 5 85 5 85 5 55 ns (48)TRSTD Power Supply HIGH to RESET LOW Setup Time 500 - 500 - 500 - ns (49)TRSTS RESET to First IOR orIOW 2TCY - 2TCY - 2TCY - ns (50)TRSTW RESET Pulse Width 300 - 300 - 300 - ns (51)TRW READ Pulse Width 200 - 155 - 85 - ns (52)TWA ADR from WRITE HIGH Hold Time 0 - 0 - 0 - ns (53)TWC CS HIGH fromWRITE HIGH Hold Time 0- 0-0- n s (54)TWD Data from WRITE HIGH Hold Time 10 - 10 - 10 - ns (55)TWWS WRITE Pulse Width 150 - 100 - 45 - ns TA = -40oC to +85oC (I82C37A), TA = -55oC to +125oC (M82C37A) (Continued) SYMBOL PARAMETER 82C37A-5 82C37A 82C37A-12 UNITSMIN MAX MIN MAX MIN MAX
FIGURE 10. DMA TRANSFER
NOTES: 1. VCC = 5.5V± 0.5V 2. VIH = 4.5V± 10% 3. VIL = -0.2V to 0.4V 4. GND = 0V 5. R1 = 1.2kΩ± 5% 6. R2 = 47kΩ± 5% 7. C1 = 0.01µF minimum 8. C2 = 0.1µF minimum 9. D1 = 1N4002 10. F0 = 100kHz±10% 12. DO0 - DO6 are outputs from the 82C82 Octal Latching Bus Driver DO5 VCC/2 VCC/2 VCC/2 A DO5 VCC/2 VCC/2 VCC/2 DO5 DO6 VCC/2 F12 F13 F14 F15 GND VCC VCC/2 VCC/2 VCC/2 A VCC DO1 VCC DO0 B DO2 DO3 DO4 F10 VCC/2 VCC/2 DO4 VCC/2 VCC/2 F9 VCC/2 VCC/2 F14 F13 F12 VCC/2 F15 GND DO4 OPEN DO5 VCC/2 VCC/2 DO5 D06 VCC/2 OPEN VCC/2 46 3 1 4041424344 A VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 A VCC DO1 B DO2 DO3 DO4 F10 VCC VCC/2 VCC DO5 OPEN OPEN DO4 2827262524232221201918 VCC VCC C1C1 AB
DIE DIMENSIONS: 148 x 159 x 19 ±1mils (3760- x 4040 x 525µm) METALLIZATION: Type: SiAlCu Thickness: Metal 1: 8kÅ ± 0.75kÅ Thickness: Metal 2: 12kÅ ± 1.0kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å ± 3kÅ WORST CASE CURRENT DENSITY: 0.6 x 105 A/cm2 Metallization Mask Layout 82C37A 82C37A