RF9678

RF9678 RFMD | Alldatasheet

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Functional Block Diagram RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA T el (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS/Gfc SiGe HBT Si CMOS 1VGC 2VCC2 3MOD+ 4MOD- 5IS I G + 6IS I G - 7QS I G + 8QS I G -

9 LO-

10 LO+

S Quad

11 BG OUT

W-CDMA TRANSMIT MODULATOR AND IF AGC

• W-CDMA Systems  EDGE Systems  CDMA Systems  TDMA Systems The RF9678 is an integrated complete quadrature modu- lator and IF AGC amplifier designed for the transmit sec- tion of W-CDMA applications. It is designed to modulate baseband I and Q signals, and amplify the resulting IF signals while providing 55dB of gain control range. This circuit is designed as part of RFMD’s single mode W-CDMA Chipset, which also includes the RF2679 W-CDMA Receive IF AGC and Demodulator. The IC is manufactured on an advanced Silicon Bi-CMOS process, and is supplied in a16-pin leadless chip carrier.  Digitally Controlled Power Down Modes  2.7V to 3.3V Operation  Digital LO Quadrature Divider  AGC Linearity/Current Consumption Var. I FA G CA m pw i t h5 5 d BG a i nC o n t r o l RF9678 W-CDMA Transmit Modulator and IF AGC RF9678 PCBA Fully Assembled Evaluation Board Rev A4 010622 Dimensions in mm. 1.85 1.55 sq. .60 .24 typ .75 .50 .23 .13

4 PLCS

.65 .30 4.00 sq. 2 .35 .23 .65.05 .01 12° max 1.00 0.85 .80 .65 NOTES: Shaded Pin is Lead 1.1 5 Die thickness allowable: 0.305 mm max. Package Warpage: 0.05 max.4 Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. Dimension applies to plated terminal and is measured between 0.02 mm and 0.25 mm from terminal end.2 Package Style: LCC, 16-Pin, 4x4

Supply Voltage -0.5 to +5 V DC Power Down Voltage (VPD ) - 0 . 5t oV CC +0 . 7 V I and Q Levels, per pin 1.2 V PP LO1 Level, balanced +3 dBm Operating Ambient Temperature -40 to +85 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. Overall T=25°C, VCC =3.0V; ZLOAD =200 Ω ; I=Q=500mV PP, 1000mVPP Differential; Output externally matched I/Q Input Frequency Range 0 to 10 MHz Balanced I/Q Input Impedance 20 k Ω Balanced I/Q Input Reference Level 1.3 V DC Per Pin LO1 Frequency Range 0 to 1200 MHz LO1 Input Level -15 -8 -5 dBm Specifications LO1 Input Impedance 200 Ω Balanced (Evaluation Board Schematic) 2k Ω Balanced, IC input Sideband Suppression 45 50 dBc I/Q Amplitude adjusted to within ± 20mV 25 30 dBc Unadjusted Carrier Suppression 45 50 dBc I/Q DC Offset adjusted to within ± 20mV 20 28 dBc Unadjusted IF=380MHz I=Q=500mV PP, 1000mVPP Differential; LO1=760MHz; Output externally matched Max Output Power, W-CDMA Mode -6 -4.5 -3 dBm W-CDMA ACPR=-50dBc, V GC =2.4VDC , T=-20°C to +85°C Min Output Power, CDMA Mode -63 -59 -56 dBm V GC =0.2VDC Output Power Accuracy -3 +3 dB T=-20 to +85 °C, Ref=25 °C Adjacent Channel Power Rejec- tion @ 5MHz -46 dBc W-CDMA Modulation, V GC =0.2VDC to 2.4VDC Adjacent Channel Power Rejec- tion @ 10MHz -56 dBc W-CDMA Modulation, V GC =0.2VDC to 2.4VDC Output Noise Power -135 dBm/Hz @ 20MHz offset, V GC =2.4VDC Output Impedance 200 Ω Balanced IF=570MHz I=Q=700mV PP, 1400mVPP Differential; LO1=1140MHz; Output externally matched Max Output Power, W-CDMA Mode -4 dBm W-CDMA ACPR=-50dBc, V GC =2.4VDC , T=-20°C to +85°C Adjacent Channel Power Rejec- tion @ 5MHz -46 dBc W-CDMA Modulation, V GC =0.2VDC to 2.4VDC Adjacent Channel Power Rejec- tion @ 10MHz -56 dBc W-CDMA Modulation, V GC =0.2VDC to 2.4VDC Power Supply Supply Voltage 2.7 3.0 3.3 V Current Consumption 30 39 46 mA Over temperature Power Down Current <10 µA VPD HIGH Voltage V CC -1.0 V VPD LOW Voltage 0.9 V Gain Control Range 0.2 2.4 V VGC Current 40 µA Caution!ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Pin Function Description Interface Schematic 1V G C Analog gain control for AGC amplifiers. Valid control voltage ranges are from 0.2VDC to 2.4VDC . The gain range for the AGC is 55dB. These voltages are valid ONLY for a 39kΩ source impedance. A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. 2V C C 2 DC supply. This pin should be bypassed to ground with a 10nF capaci- tor. 3M O D + Same as pin 4, except complementary output. See pin 4. 4M O D - One half of the balanced AGC output port. The impedance of this port is 200Ω balanced. This pin requires an inductor to V CC to achieve full dynamic range. In order to maximize gain, this inductor should be a high-Q type and should be parallel resonated out with a capacitor (see application schematic). This pin is NOT DC blocked. A blocking capaci- tor of 2200pF is needed when this pin is connected to a DC path. An appropriate matching network may be needed if an IF filter is used. 5 I SIG+ One half of the balanced baseband input to the I mixer. This pin is DC- coupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10kΩ minimum. For maximum carrier suppression, DC voltage on this pin relative to ISIG- DC voltage may be adjusted. (In case a balun is needed, a seperate balun board (RD0102 PCBA) could be ordered as an accessory.) See pin 8. 6 I SIG- One half of the balanced baseband input to the I mixer. This pin is DC- coupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10kΩ minimum. For maximum carrier suppression, DC voltage on this pin relative to ISIG+ DC voltage may be adjusted. 7 Q SIG+ One half of the balanced baseband input to the Q mixer. This pin is DC- coupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10kΩ minimum. For maximum carrier suppression, DC voltage on this pin relative to QSIG- DC voltage may be adjusted. See pin 10. 8 Q SIG- One half of the balanced baseband input to the Q mixer. This pin is DC- coupled and must be supplied with 1.3VDC to bias the input transistor. Input impedance of this pin is 10kΩ minimum. For maximum carrier suppression, DC voltage on this pin relative to QSIG+ DC voltage may be adjusted. 9L O - One half of the balanced modulator LO1 input. In single-ended applica- tions (100Ω input impedance), this pin is AC grounded with a 1nF capacitor. See pin 10. 10 LO+ One half of the balanced modulator LO1 input. The other half of the input, LO1-, is AC grounded for single-ended input applications. The frequency on these pins is divided by a factor of 2, hence the carrier frequency for the modulator becomes one half of the applied frequency. The single-ended input impedance is 1kΩ (balanced is 2kΩ ). This pin is NOT internally DC blocked. An external blocking capacitor (1nF rec- ommended) must be provided if the pin is connected to a device with DC present. 11 BG OUT Bandgap voltage reference. This voltage, constant over temperature and supply variation, is used to bias internal circuits. A 10nF external bypass capacitor is required. 12 NC No connection. 13 VCC1 DC supply. This pin should be bypassed to ground with a 10nF capaci- tor. 14 AGC DEC AGC decoupling pin. An external bypass capacitor of 10nF capacitor is required. The trace length between the pin and the bypass capacitors should be minimized. The ground side of the bypass capacitors should connect immediately to ground plane. VGC BIAS BIAS BIAS MOD OUT- MOD OUT+ I SIG-I SIG+ Q SIG-Q SIG+ LO1+, FM+ LO1-, FM- BIAS BIAS

Pin Function Description Interface Schematic 15 ISET Connected to ground through an external resistor. The value can be varied to change the current in the AGC for optimum linearity and cur- rent consumption. 16 PD Power down control for overall circuit. When logic “high” (≥VCC -0.7V), all circuits are operating; when logic “low” (≤ 0.5V), all circuits are turned off. The input impedance of this pin is >10kΩ . A DC voltage less than or equal to the maximum allowable VCC may be applied to this pin when no voltage is applied to the VCC pins. Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. PD

by examining the relative powers of the carrier signal and the W-CDMA channel power. The following equations may be used to calculate W-CDMA channel and carrier feedthrough levels. mizing the modulator input signals. Figure 3. DC Offset Error (Carrier Feedthrough)

rier and sideband suppression is known as optimization. thereby canceled and maximum carrier suppression is achieved.

380.01503006 MHz

Figure 4. W-CDMA Spectral Plot

9) Repeating Steps 7 and 8 may yield slightly better suppression. The output spectrum should look similar to Figure 7. 10) Adjust the AC amplitude of the "ISIG+" signal in as small an increment as the test equipment will allow (~1mV). 11) Adjust the AC amplitude of the "QSIG+" signal in as small an increment as the test equipment will allow (~1mV). mum. The minimum sideband signal level should occur within ±20mV adjustment (0.500±0.02V). output of the spectrum analyzer. Adjust the phase of the "QSIG+" signal until the sideband suppression is at a minimum. The sideband signal should reach a minimum within ±1° of adjustment (90±1°).

379.84987475 MHz

Figure 7. Optimized Carrier Suppression

Figure 8. Optimized Carrier and Sideband Suppression

39 kΩ VGC 1n F VPD 1500 Ω 10 nF VCC 10 nF 10 nF 1n F 1n F LO IN IS I G + 15 nH QS I G + 5 6 7 8 13141516 Gain Control Σ Quad QS I G - IS I G -

Evaluation Board Schematic (Download Bill of Materialsfrom www.rfmd.com.) 39 kΩ VGC VPD 1500 Ω 10 nF 10 nF VCC 1:4 VCCNC 50 Ωµ stripJ1 MOD 4:1 50 Ωµ strip J6 LO IN 200 Ω 10 nF 50 Ωµ strip J5 QS I G - 50 Ωµ strip J4 QS I G + 50 Ωµ stripJ2 IS I G + 50 Ωµ stripJ3 IS I G - GND P1-2 VCC1 P1-1 PD CON3 GND GND P2-1 VGC CON3 5 6 7 8 13141516 Gain Control Σ Qua d

Board Size 2.0” x 2.0” Board Thickness 0.031”, Board Material FR-4

(1 VP-P, 380 MHz) 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 VGC (VDC ) ICC (mA) +25C POUT versus VIN (VGC =2 . 4 VDC ,380 Mhz, W-CDMA) -16 -14 -12 -10 VIN (VP Differential) POUT (dbm) (25°C) Performance versus VBIAS VIN=300mV PP (Differential) 0.00 10.00 20.00 30.00 40.00 50.00 60.00 VBIAS (VDC ) ACPR (dBc) -30.00 -25.00 -20.00 -15.00 -10.00 -5.00 0.00 Channel Power Out (dBm) ACPup (dbc) ACPlow (dbc) ALTup (dbc) ALTlow (dbc) ChPout (dbm) ACPR versus VGC (W-CDMA, 3GPP, Temp. +25oC, - 40oC, +85oC) (LO Freq. 760MHz@-8dBm, VCC =3.0V, VGC =2.4 to 0.2V) -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 VGC (V) Adjacent Channel Power (dBc) ACPR [dBc] @ +25C ACPR [dBc] @ - 40C ACPR [dBc] @ +85C Channel Output Power versus VGC (W-CDMA-3GPP, Temp. +25oC) -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 VGC (V) Channel Output Power (dBm) Ch.Power out [dBm] @ 3V Ch.Power out [dBm] @ 2.7V Ch.Power out [dBm] @ 3.3V Altr. Channel Power versus VGC (W-CDMA-3GPP, Temp. +25oC, -40oC, +85oC) (LO Freq. 760MHz@-8dBm, VCC =3.0V, VGC =2.4V to 0.2V) -90.0 -80.0 -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 VGC (V) Alternate Channel Power (dBc) ALTR.Ch.Power [dBc] @ +25C ALTR.Ch.Power[dBc] @ - 40C ALTR.Ch.Power[dBc] @ +85C

(LO Freq. 760MHz@-8dBm, VCC =VPD =3.0V, VGC =2.4 to 0.2V) -30.0 -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 VGC (V) IGC (uA) Igc [uA] Channel Output Power versus VGC (W-CDMA 3GPP, Temp.+25 o C, -40 o C, +85 o (LO Freq. 760MHz@-8dBm, VCC =3.0V, VGC =2.4 to 0.2V) -70.0 -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 VGC (V) Channel Output Power (dBm) Ch.Power out [dBm] @ +25C Ch.Power out [dBm] @ - 40C Ch.Power out [dBm] @ +85C EVM versus VGC (W-CDMA-3GPP, Temp. +25oC, - 40oC, +85oC) (LO Freq. 760MHz@-8dBm, VCC =3.0V, VGC =2.4 to 1.0V) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 VGC (V) EVM (%) EVM [%] @ +25C EVM [%] @ - 40C EVM [%] @ +85C