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Fully Compliant to LTE Modulation LTE Bands 11, 21 Best-in-Class Efficiency 47%, +28.5dBm Rel 99 output power High Power Gain : 28dB E-UTRA ACLR : -38dBc UTRA ACLR : -39dBc All LTE Channel Bandwidths (5 MHz up to 20 MHz) Optimized use with DC-DC converter Operation Three Power States with Digital Control Interface Integrated Power Coupler Integrated Blocking and Decoupling Capacitors
Applications
LTE Handsets LTE Datacards RF7321 3V LTE Band 11, 21 Linear PA Module RF7321PCBA-410 Fully Assembled Evaluation Board DS120906 Package Style: Module, 10-Pin, 3mm x 3mm x 0.8mm
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. POUT = 28. dBm Absolute Maximum Ratings Parameter Rating Unit Supply Voltage in Standby Mode 6.0 V Supply Voltage in Idle Mode 6.0 V Supply Voltage in Operating Mode 6.0 V Supply Voltage, V BAT 6.0 V Control Voltage: VMODE0, VMODE1 3.5 V Control Voltage: VEN 3.5 V RF - Input Power +10 dBm RF - Output Power +30 dBm Output Load VSWR (Ruggedness) 10:1 Operating Ambient Temperature -30 to +85 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. Recommended Operating Conditions Operating Frequency Range 1427.9 1462.9 MHz VEN, low level 0 0.5 V PA disabled VEN, High level 1.5 1.8 3.1 V PA enabled VMODE0, VMODE1, low level 0 0.5 V For a logic "low" VMODE0, VMODE1, high level 1.5 1.8 3.1 V For a logic "high" Output Power (POUT) Rel 99 Maximum Linear Output (HP) +28.52 dBm High Power Mode (HP) Rel 99 Maximum Linear Output (MP) +172 dBm Medium Power Mode (MP) Rel 99 Maximum Linear Output (LP) +72 dBm Low Power Mode (LP) LTE Maximum Linear Output (HP) +27.52 dBm High Power Mode (HP), MPR=0 LTE Maximum Linear Output (MP) +162 dBm Medium Power Mode (MP), MPR=0 LTE Maximum Linear Output (LP) +62 dBm Low Power Mode (LP), MPR=0 Ambient Temperature -30 25 +85 °C Notes: [1] VCC down to 0.5V may be used for backed-off power when using DC-DC converter to reduce low power current drain. [2] For operation at VCC=3.0V, de-rate POUT by 1.0dB and at VCC=3.2V de-rate POUT by 0.5dB Caution! ESD sensitive device. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical perfor- mance or functional operation of the device under Absolute Maximum Rating condi- tions is not implied. The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended appli- cation circuitry and specifications at any time without prior notice. RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric materials and red phosphorus as a flame retardant, and <2% antimony in solder.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Parameter Specification Unit ConditionMin. Typ. Max. Electrical Specifications Temp = +25C, VBAT= +3.8V, VEN = +1.8V, 50 system, LTE Modulation used: QPSK, 10MHz channel,
12 Resource Blocks with MPR = 0, unless otherwise
specified. Gain 26.5 28 31.5 dB HP, P OUT = 27.5dBm, VCC = 3.4V 17 19.5 23 dB MP, P OUT ≤ 16dBm, VCC = 1.3V 11 14 17 dB LP, P OUT ≤ 6dBm, VCC = 0.7V Gain Flatness ±0.25 dB All modes over any 13.5MHz BW Gain Linearity ±1 dB All modes ACLR - E-UTRA (±10MHz) -39 -35 dBc HP, P OUT = 27.5dBm, VCC = 3.4V (MPR=0) -39 -35 dBc HP, POUT = 26.5dBm, VCC = 3.4V1 -41 -35 dBc MP, P OUT ≤ 16dBm, VCC = 1.3V -44 -35 dBc LP, P OUT ≤ 6dBm, VCC = 0.7V ACLR1 - UTRA (±7.5MHz) -39 -36 dBc HP, P OUT = 27.5dBm, VCC = 3.4V (MPR=0) -39 -36 dBc HP, POUT = 26.5dBm, VCC = 3.4V1 -41 -36 dBc MP, P OUT ≤ 16dBm, VCC = 1.3V -44 -36 dBc LP, P OUT ≤ 6dBm, VCC = 0.7V ACLR2 - UTRA (±12.5MHz) -62 -49 dBc HP, P OUT = 27.5dBm, VCC = 3.4V (MPR=0) -42 -39 dBc HP, POUT = 26.5dBm, VCC = 3.4V1 -62 -49 dBc MP, P OUT ≤ 16dBm, VCC = 1.3V -62 -49 dBc LP, P OUT ≤ 6 dBm, VCC = 0.7V PA Efficiency (PAE) 39 43 % HP, P OUT = 27.5 dBm, VCC = 3.4V 35 40 % HP, POUT = 26.5dBm, VCC = 3.4V1 25 29 % MP, P OUT = 16 dBm, VCC = 1.3V 10 12 % LP, P OUT = 6 dBm, VCC = 0.7V PA Current Drain 375 404 mA HP, P OUT = 27.5 dBm, VCC = 3.4V 320 375 mA HP, POUT = 26.5dBm, VCC = 3.4V1 105 126 mA MP, P OUT = 16 dBm, VCC = 1.3V 39 46 mA LP, P OUT = 6 dBm, VCC = 0.7V PA + DC-DC Current Drain (MP) 42.3 mA P OUT = 16dBm, Assumes VBAT = 3.8V, 85% DC-DC PA + DC-DC Current Drain (LP) 9.6 mA P OUT = 6dBm, Assumes VBAT = 3.8V, 75% DC-DC Quiescent Current (PA only) 53 70 mA HP, DC only, No RF applied 37 50 mA MP, DC only, No RF applied 23 28 mA LP, DC only, No RF applied Quiescent Current (PA + DC-DC) 5.0 mA No RF, with V CC= 0.6V, VBAT = 3.8V, and DC-DC Efficiency = 73%. Noise Power in Duplex Rx Band 11 -135 dBm/Hz All power outs, then measured at Rx Duplex Band 11 (Rx = 1476.9MHz to 1495.9MHz) Noise Power in Duplex Rx Band 21 -135 dBm/Hz All power outs, then measured at Rx Duplex Band 21 (Rx = 1495.9MHz to 1510.9MHz) Noise Power in GPS Rx Band -135 dBm/Hz GPS Band RX at 1575.42MHz ± 1MHz Noise Power in Band 1 -140 dBm/Hz Measured in the 2110 - 2170 MHz band NOTES: [1] ACLR measurements were performed using 10MHz, QPSK LTE modulation with 50 resource blocks (MPR = 1dB) (reference 3GPP TS36.101)
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Parameter Specification Unit ConditionMin. Typ. Max. Electrical Specifications (continued) Temp = +25C, VBAT= +3.8V, VEN = +1.8V, 50 system, LTE Modulation used: QPSK, 10MHz channel, specified. Noise Power in 2.4 GHz ISM Band -143 dBm/Hz Measured in the 2400 - 2483 MHz band Noise Power in 5 GHz ISM Band -146 dBm/Hz Measured in the 4.9MHz to 5.9MHz band, excludes 3rd harmonic contributions EVM 2.5 5 % P OUT ≤ +27.5 dBm, all power outs Intermodulation (Channel BW offset) -35 dBc CW interferer at -42dBc at Channel BW Offset from carrier, POUT ≤ 27.5dBm Intermodulation (2x Channel BW offset) -41 dBc CW interferer at -42dBc at (2 x Channel BW) Offset from carrier, POUT ≤ 27.5dBm Input VSWR 1.8:1 VSWR All modes Spurious Output Levels -70 dBc All spurious, P OUT ≤ 27.5dBm, all conditions, load VSWR at 6:1, all phase angles Insertion Phase Shift ±25 ° Phase shift at +16dBm when switching from HP to MP, and then from MP to LP at +6dBm Insertion Phase Shift Variation ±10 ° Part to part DC Enable time 10 S Applied DC only, Time from V EN = HIGH to stable idle current (90% of steady state value) RF Rise time / RF Fall time 2 S Coupling Factor 20 dB P OUT ≤ +27.5 dBm, all power outs Coupling Accuracy - Temp/Voltage ±0.5 dB P OUT ≤ 27.5 dBm, all modes, -20°C ≤ T ≤ +85, VCC as required , referenced back to 25°C, 3.4V nominal condition Coupling Accuracy - VSWR ±0.25 dB P OUT ≤ 27.5 dBm, all modes, load VSWR 2:1, ± 0.25dB accuracy corresponds to 20dB coupler directivity Coupler Insertion Loss 0.25 dB For the daisy-chain couplers (PA-to-PA): CPL IN to CPL OUT; 698MHz to 2620MHz Rel 99 UMTS ACLR1 (±5MHz) -40 dBc HP, P OUT = 28.5 dBm, VCC = 3.4V -40 dBc MP, P OUT ≤ 17dBm, VCC= 1.3V -40 dBc LP, P OUT ≤ 7dBm, VCC= 0.7V UMTS ACLR2 (±10MHz) -52 dBc HP, P OUT = 28.5dBm, VCC = 3.4V -52 dBc MP, P OUT ≤ 17dBm, VCC= 1.3V -52 dBc LP, POUT ≤ 7dBm, VCC= 0.7V PA Efficiency (PAE) 47 % HP, P OUT = 28.5dBm, VCC = 3.4V 32 % MP, P OUT = 17dBm, VCC= 1.3V 17 % LP, P OUT = 7dBm, VCC= 0.7V PA Current Drain 443 mA HP, P OUT = 28.5dBm, VCC = 3.4V 120 mA MP, P OUT = 17dBm, VCC= 1.3V 40 mA LP, P OUT = 7dBm, VCC= 0.7V PA + DC-DC Current Drain (MP) 48 mA P OUT = 17dBm, Assumes VBAT = 3.8V, 85% DC-DC PA + DC-DC Current Drain (LP) 10 mA P OUT = 7dBm, Assumes VBAT = 3.8V, 75% DC-DC UMTS EVM 2 % All modes Harmonics, 2FO -35 dBc P OUT = +28.5 dBm Harmonics,3FO -42 dBc P OUT = +28.5 dBm
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Pin-Out Description Pin Function Description 1V B A T Supply voltage for the bias circuitry. 2R F I N RF input internally matched to 50 and DC blocked. 3V M O D E 1 Digital control input for power mode selection. 4V M O D E 0 Digital control input for power mode selection. 5V E N Digital control input for PA enable and disable. 6C P L O U T Coupler output. 7G N D This pin must be grounded. 8C P L I N Coupler input used for cascading couplers in series. Terminate this pin with a 50 resistor if not connected to another coupler. 9R F O U T RF output internally matched to 50 and DC blocked. 10 VCC Supply voltage for the first and second stage amplifiers which can be connected to the battery supply or output of the DC-DC converter. Pkg Base GND Ground connection - this package backside should be soldered to a topside ground pad connecting to the PCB ground plane with multiple ground vias. The pad should have a low thermal resistance and low electrical imped- ance to the ground plane. Operating Logic Table VEN VMODE0 VMODE1 VBAT VCC Conditions/Comments Low Low Low 3.0V to 4.4V 0.5V to 4.35V Power down mode Low X X 3.0V to 4.4V 0.5V to 4.35V Standby Mode High Low Low 3.0V to 4.4V 0.5V to 4.35V High Power State High High Low 3.0V to 4.4V 0.5V to 4.35V Medium Power State High High High 3.0V to 4.4V 0.5V to 4.35V Low Power State
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Package Drawing
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Preliminary Application Schematic Evaluation Board Schematic VBAT VMODE1 VMODE0 VEN 4.7uF VCC 4.7uF (2) NOTES: 1. The 50resistor should be removed if pin 8 is connected to another coupler for daisy chaining multiple couplers. 2. This capacitance value can be reduced for multi-PA with DC to DC converter applications where a total maximum capacitive load is required to be met. Keeping at least a 1uF capacitor close to the PA Vcc pin is recommended. RF OUT CPL OUT RF IN 50 (1) AMP Bias Control & PA/VMODE Enable VCC1 VMODE1 VMODE0 VEN 4.7uF VCC2 4.7uF NOTES: 1. VCC2S is a sense line to be used if the test power supply has voltage sensing capability. This compensates for any resistive voltage drop that occurs between the power supply and the PA and thus ensures that the voltage at the PA is set as expected. RF OUT CPL OUT RF IN 51 AMP Bias Control & PA/VMODE Enable 22uF 10nF 10nF 10nF C10 10nF C11 10nF P1_4 VMODE1 P1_5 VCC1 P1_6 P1_7 VCC2 P1_8 VCC2S (1) P1_9 P1_3 VMODE0 P1_2 VEN P1_1
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. PCB Design Requirements PCB Surface Finish The PCB surface finish used for RFMD's qualification process is electroless nickel, immersion gold. Typical thickness is 3inch to 8inch gold over 180inch nickel. PCB Land Pattern Recommendation PCB land patterns for RFMD components are based on IPC-7351 standards and RFMD empirical data. The pad pattern shown has been developed and tested for optimized assembly at RFMD. The PCB land pattern has been developed to accommodate lead and package tolerances. Since surface mount processes vary from company to company, careful process development is recommended. PCB Metal Land Pattern (Top View)
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. PCB Solder Mask Pattern Liquid Photo-Imageable (LPI) so lder mask is recommended. The solder mask fo otprint will match what is shown for the PCB metal land pattern with a 2mil to 3mil expansion to accommodate solder mask registration clearance around all pads. The center-grounding pad shall also have a solder mask clearance. Expansion of the pads to create solder mask clearance can be provided in the master data or requested from the PCB fabrication supplier. PCB Solder Mask Pattern (Top View) Thermal Pad and Via Design The PCB land pattern has been designed with a thermal pad that matches the die paddle size on the bottom of the device. Thermal vias are required in the PCB layout to effectively conduct heat away from the package. The via pattern has been designed to address thermal, power dissipa tion and electrical requirements of the device as well as accommodating routing strategies. The via pattern used for the RFMD qualification is based on thru-hole vias with 0.203mm to 0.330mm finished hole size on a 0.5mm to 1.2mm grid pattern with 0.025mm plating on via walls. If micro vias are used in a design, it is suggested that the quantity of vias be increased by a 4:1 ratio to achieve similar results.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. PCB Stencil Pattern (Top View)