RF6100-1 RFMD | Alldatasheet
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RF Micro Devices, Inc.
7628 Thorndike Road
Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS Bias VREG VMODE GND RF IN VCC1 GND RF OUT VCC2 GND GND RF6100-1 3V 900MHZ LINEAR POWER AMPLIFIER MODULE
- 3V CDMA/AMPS Cellular Handset
- 3V CDMA20001/X Cellular Handset
- Spread-Spectrum System The RF6100-1 is a high-power, high-efficiency linear amplifier module specifically designed for 3V handheld systems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V IS-95/CDMA 2000 1X/AMPS handheld digital cellular equipment, spread- spectrum systems, and other applications in the 824MHz to 849MHz band. The RF6100-1 has a digital control line for low power applications to lower quiescent current. The device is self-contained with 50 Ω input and output that is matched to obtain optimum power, efficiency and linear- ity. The module is a 4mmx4mm land grid array with back- side ground. The RF6100-1 is footprint compatible with industry standard 4mmx4mm CDMA modules, and requires only one decoupling capacitor.
- Input/Output Internally Matched@50 Ω
- 28dBm Linear Output Power
- 40% Peak Linear Efficiency
- -50dBc ACPR @ 885kHz
- 29dB Linear Gain
- 53% AMPS Efficiency RF6100-1 3V 900MHz Linear Power Amplifier Module RF6100-1 PCBA Fully Assembled Evaluation Board Rev A0 031219 0.450 ± 0.075 1.40 1.254.00 ± 0.10 4.00 ± 0.10 1 3.549 3.500 3.050 2.650
2.400 TYP
2.200 1.800 1.650 1.350 0.950 0.725 0.125 R0.20 TYP
0.100 TYP
3.900 TYP
2.425 2.200 1.800 1.525 1.350 0.950
0.500 TYP
0.000 0.775 0.000
1.000 TYP
3.000 TYP
3.500 TYP
3.200 2.975
0.600 TYP
Package Style: Module (4mmx4mm)
Supply Voltage (RF off) +8.0 V Supply Voltage (POUT≤31dBm) +5.2 V Control Voltage (VREG)+ 4 . 2 V Input RF Power +10 dBm Mode Voltage (VMODE)+ 3 . 5 V Operating Temperature -30 to +110 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. High Power Mode (VMODE Low) T=25 oC Ambient, VCC=3.4V, VREG=2.8V , VMODE=0V , and POUT=28dBm for all parameters (unless otherwise specified). Operating Frequency Range 824 849 MHz Linear Gain 27 29 dB Second Harmonics -35 dBc Third Harmonics -40 dBc Maximum Linear Output 28 Linear Efficiency 35 40 % Maximum I CC 465 530 mA ACPR @ 885kHz -50 -46 dBc ACPR @ 1.98MHz -58 -55 dBc Input VSWR 2:1 Stability in Band 6:1 No oscillation>-70dBc Stability out of Band 10:1 No damage Noise Power -133 dBm/Hz At 45MHz offset. Low Power Mode (VMODE High) T=25 oC Ambient, VCC=3.4V, VREG=2.8V , VMODE=2.8V, and POUT=18dBm for all parameters (unless otherwise specified). Operating Frequency Range 824 849 MHz Linear Gain 24 26 dB Second Harmonics -35 dBc Third Harmonics -40 dBc Maximum Linear Output 18 Maximum I CC 135 mA P OUT=16dBm ACPR @885kHz -50 -46 dBc ACPR @1.98MHz -60 -56 dBc Input VSWR 2:1 Output VSWR Stability 6:1 No oscillation>-70dBc 10:1 No damage Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).
Parameter Specification Unit ConditionMin. Typ. Max. FM Mode T=25 oC Ambient, VCC=3.4V, VREG=2.8V , VMODE=0V , and POUT=31dBm for all parameters (unless otherwise specified). Operating Frequency Range 824 849 MHz AMPS Maximum Output Power 31 dBm AMPS Efficiency 47 53 % AMPS Gain 24 28 AMPS Second Harmonics -35 -30 dBc AMPS Third Harmonics -40 -30 dBc Power Supply Supply Voltage 3.2 3.4 4.2 V High Gain Idle Current 65 100 mA V MODE=low and VREG=2.8V Low Gain Idle Current 55 70 mA V MODE=high and VREG=2.8V VREG Current 4.7 5.5 mA V MODE=high VMODE Current 250 1000 uA RF Turn On/Off Time 6 uS DC Turn On/Off Time 40 uS Total Current (Power Down) 0.2 5.0 uA V REG Low Voltage 0 0.5 V VREG High Voltage (Recommended) 2.75 2.8 2.95 V VREG High Voltage (Operational) 2.7 3.0 V VMODE Voltage 0 0.5 V High Gain Mode 2.0 2.8 V Low Gain Mode
Pin Function Description Interface Schematic 1V R E G Regulated voltage supply for amplifier bias. In Power Down mode, both VREG and VMODE need to be LOW (<0.5V). 2V M O D E For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency. 3G N D Ground connection. Connect to package base ground. For best perfor- mance, keep traces physically short and connect immediately to ground plane. 4R F I N RF input internally matched to 50Ω. This input is internally AC-coupled. 5V C C 1 First stage collector supply. A low frequency decoupling capacitor (e.g., 4.7µF) may be required. 6V C C 2 Output stage collector supply. A low frequency decoupling capacitor (e.g., 4.7µF) is required. 7G N D Ground connection. Connect to package base ground. For best perfor- mance, keep traces physically short and connect immediately to ground plane. 8R F O U T RF output internally matched to 50 Ω. This output is internally AC-coupled. 9G N D Ground connection. Connect to package base ground. For best perfor- mance, keep traces physically short and connect immediately to ground plane. 10 GND Ground connection. Connect to package base ground. For best perfor- mance, keep traces physically short and connect immediately to ground plane. Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. The pad should have a short thermal path to the ground plane.
Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) 10VREG 4.7 µF 50 Ω µstrip J2 RF OUT 50 Ω µstripJ1 RF IN VCC1 4.7 µF VCC2 22 µF 4.7 µF VMODE Bias CON5 GND GND GND P2-5 VMODE P2-3 VREG CON5 GND GND GND P1-2 VCC1 P1-4 VCC2
3µinch to 8µinch gold over 180µinch nickel. assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 1. PCB Metal Land and Solder Mask Pattern (Top View)