RF5189

RF5189_06 RFMD | Alldatasheet

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RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS 5 6 101112 Input Match Output Match Bias Interstage Match PWR SENBIAS1GND RF IN NC VREG2 BIAS2GND RF OUT RF OUT VCC2 VREG1 VCC1 VCC2 RF5189 3V, 2.45GHz LINEAR POWER AMPLIFIER

• IEEE802.11B WLAN Applications
• 2.5GHz ISM Band Applications
• Wireless LAN Systems
• Commercial and Consumer Systems
• Portable Battery-Powered Equipment
• Spread-Spectrum and MMDS Systems The RF5189 is a linear, medium-power, high-efficiency amplifier IC designed specifically for battery-powered WLAN applications such as PC cards, mini PCI, and compact flash applications. The device is manufactured on an advanced Gallium Arsenide Heterojunction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in 2.5GHz WLAN and other spread-spectrum transmitters. The device is provided in a 12-pin QFN package with a backside ground. The RF5189 is designed to maintain linearity over a wide range of supply voltage and power output. The RF5189 is designed to reduce end-product BOM count by integrat- ing all matching circuitry onto the chip.
• Single Power Supply 3.0V to 5.0V
• +30dBm Saturated Output Power
• 25dB Small Signal Gain
• High Linearity
• 2400MHz to 2500MHz Frequency Range RF5189 3V, 2.45GHz Linear Power Amplifier RF5189 PCBA Fully Assembled Evaluation Board Rev A7 060127 Shaded areas represent pin 1. Dimensions in mm. 0.08 C0.1 C C0.925 0.775 0.102 REF 0.203 REF

2 PLCS

0.15 C 0.15 C Pin 1 ID A 3.00 B 3.00 1.55 1.35 0.45 0.25TYP

0.10 C A BM

1.45 Pin 1 ID

0.50 TYP

0.05 Package Style: QFN, 12-Pin, 3x3 RoHS Compliant & Pb-Free Product

Supply Voltage -0.5 to +6.0 V DC Power Control Voltage (VREG) -0.5 to 3.5 V DC Supply Current 600 mA Input RF Power +10 dBm Operating Ambient Temperature -40 to +85 °C Storage Temperature -40 to +150 °C Moisture sensitivity JEDEC Level 2 Parameter Specification Unit ConditionMin. Typ. Max. Overall-11b Signal T=25° C, VCC=3.0V , VREG=2.7V , Freq=2450MHz Frequency Range 2400 to 2500 MHz Maximum Linear Output Power With 802.11B modulation (11Mbit/s) and meeting 802.11B spectral mask. V CC=3.0V 21 22 dBm VCC=5.0V 24 dBm Linear Efficiency 24 % Small Signal Gain 23 25 27 dB P IN=-7dBm Second Harmonic -35 dBc 802.11B Adjacent Channel Power -38 -32 dBc P OUT=21dBm, V CC=3.0V Alternate Channel Power -56 -52 dBc P OUT=21dBm, V CC=3.0V Isolation 30 dB In “OFF” state, P IN=-5.0dBm Input Return Loss 9.5 15.0 dB 50 Ω reference Output VSWR 2:1 1.5:1 50 Ω reference Power Detect Voltage 1.7 2.1 2.4 V P 0=21dBm Power Down VREG “ON” 2.1 2.7 3.0 V Voltage supplied to control input; device is “ON” VREG “OFF” 0 0.5 V Voltage supplied to control input; device is “OFF” Power Supply Operating Voltage 3.0 to 5.0 V Current Consumption 10 μAV REG=0V 100 160 mA No RF input, V CC=3.0V, and VREG=2.7V 220 270 mA P OUT=21dBm, V CC=3.0V, and VREG=2.7V VREG Current (Total) 5 10 mA V CC=3.0V 10 15 mA V CC=5.0V Caution! ESD sensitive device. Refer to “Handling of PSOP and PSSOP Products” on page 16-15 for special handling information. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Pin Function Description Interface Schematic 1R F I N RF input. Input is matched to 50Ω and DC block is provided internally. 2N C No connect. Recommend connecting to ground. 3B I A S 1 G N D Ground for first stage bias circuit. For best performance, keep traces physically short and connect immediately to ground plane. See pin 4. 4V R E G 1 First stage input bias. This pin requires a regulated supply to maintain nominal bias current. 5V R E G 2 Second stage input bias. This pin requires a regulated supply to main- tain nominal bias current. Usually connected to VREG1. See pin 4. 6B I A S 2 G N D Ground for second stage bias circuit. For best performance, connect to ground with a choke inductor. See pin 4. 7 PWR SEN Provides an output voltage proportional to output RF level. 8R F O U T RF output. Output is matched to 50Ω and DC block is provided inter- nally. 9R F O U T Same as pin 8. See pin 8. 10 VCC2 Second stage output bias. Supply should be connected through a choke inductor sized appropriately to handle the output bias current. See pin 8. 11 VCC2 Same as pin 10. See pin 8. 12 VCC1 First stage output bias. This pin is sensitive to bypass capacitors placed close to it. Place an RF short approximately 200mils from this pin before any other supply connections. See pin 1. Pkg Base GND Ground connection. The backside of the package should be connected to the ground plane through a short path (i.e., vias under the device will be required). INPUT MATCH VCC1 INTERSTAGE MATCH BIAS VREG1 VREG2 BIAS GND1 BIAS GND2 RF OUTOUTPUT MATCH VCC2

The RF5189 is a two-stage device with a nominal gain of 25dB in the 2.4GHz to 2.5GHz ISM band. The RF5189 is designed primarily for IEEE802.11B WLAN applications where the available supply voltage and current are limited. This amplifier will operate to (and below) the lowest expected voltage made available by a typical PCMCIA slot in a laptop PC, and will maintain required linearity at decreased supply voltages. The RF5189 requires only a single positive supply of 3.0V no minal (or greater) to operate to full specifications. Power control is provided through two bias control input pins (VREG1 and VREG2), but in most applications these are tied together and used as a single control input. There is no external matching required on the input and output of the part, thus allowing minimal bill of material (BOM) parts count in end applications. Both the input and the output of the device are DC-blocked. For best results, the PA circuit layout from the evaluation board should be copied as closely as possible, particularly the ground layout and ground vias. Other configurations may also work, but the design process is much easier and quicker if the layout is copied from the RF5189 evaluation board. Gerber files of our designs are available on request. The RF5189 is not a difficult part to implement, but care in circuit layout and component selection is always advisable when designing circuits to operate at 2.5GHz. The choke inductors on VCC2 and BIAS2GND should be chosen so that they are parallel self-resonant at the frequency of operation. In addition, the supply side of the choke inductor on VCC2 should be bypassed with a capacitor that is series self-resonant at the frequency of operation. In practice, VCC1 and the supply side of the choke on VCC2 w ill be tied to the same supply . It is important to isolate VCC1 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a suit- ably-long transmission line which is RF shorted on the other end as described above. Ideally the length of this line will be a quarter wavelength, but it only needs to be long enough so that the effects of other supply bypass capacitors on the VCC1 line are minimized. If board space is a concern, this isolation can also be accomplished with an RF choke inductor or ferrite bead. The RF5189 has primarily been characterized with a voltage on VREG1 and VREG2 of 2.7V DC. However, the RF5189 will operate from a wide range of control voltages. If you prefer to use a control voltage that is significantly different than 2.7VDC, contact RFMD Sales or Applications Engineering for additional data and guidance.

Evaluation Board Schematic 50 Ω μstripJ1 RF IN VREG1 1000 pF VREG2 C13 1000 pF 10 nH C13 1000 pF PDETECT 50 Ω μstrip J2 RF OUT 12 nH C14 1 μF VCC P2-3 VCC1 GND GND CON3 GND GND P1-5 VREG1 P1-3 VREG2 P1-1 PDETECT CON5 P3-1 VCC CON1 GND CON1 5 6 101112 Input Match Output Match Bias Interstage Match

Board Size 1.10" x 1.85" Board Thickness 0.032”, Board Material FR-4

POUT, Gain, ICC Total versus PIN (Typical) @ VCC=3.0V, VREG=2.7V 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 PIN (dBm) Gain (dB), POUT (dBm) 0.0 50.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 ICC Total (mA) Pout(dBm) Gain(dB) ICC_Total(mA) POUT, Gain, ICC Total versus VREG @ VCC=3.0V 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 Vreq(V) Gain(dB), Pout(dBm) 0.0 50.0 100.0 150.0 200.0 250.0 300.0 ICC Total (mA) Pout(dBm) Gain(dB) ICC_Total(mA) Channel Frequency versus Gain (Typical) for VCC=3.0V, 3.3V, and 5.0V, VREG1=VREG2=2.7V and POUT=21dBm 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 Frequency (GHz) Gain (dB) Gain(dB)@Vcc=3.0Volts Gain(dB)@Vcc=3.3Volts Gain(dB)@Vcc=5.0 Volts POUT, PDETECT versus PIN (Typical) @ VCC=3.0, VREG=2.7 over Temp (-40, +25, +85)°C 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 PIN (dBm) POUT (dBm) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 PDETECT (V) Pout(dBm) @ + 25 C Pout(dBm) @ +85 c Pout(dBm) @ -40 C PDETECT (V) @ +25 C PDETECT (V) @ + 85 C PDETECT (V) @ -40 C

ICQ, ICC_Total, POUT versus VREG (Typical) @ VCC=3.0V, PIN=- 5dBm 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0 220.0 240.0 260.0 280.0 300.0 VREG (V) ICQ, ICC_Total (mA) 0.0 5.0 10.0 15.0 20.0 25.0 POUT (dBm) ICQ(mA) ICC_Total(mA) Pout(dBm) IREG, POUT versus VREG (Typical) @ VCC=3.0V, PIN=-5.0dBm 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VREG (V) IREG_Total (mA) 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 POUT (dBm) Ireg(mA) Pout(dBm) Spectral Mask (Typical): VCC=3.0V, VREG1=VREG2=2.7V, POUT=18dBm, PIN=-7.55dBm, and ICC_Total=168mA Spectral Mask (Typical): VCC=3.0V, VREG1=VREG2=2.7V, POUT=21dBm, PIN=-4.0dBm, and ICC_Total=210mA

3μinch to 8μinch gold over 180μinch nickel. assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. Figure 1. PCB Metal Land Pattern (Top View)

can be provided in the master data or requested from the PCB fabrication supplier. that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 2. PCB Solder Mask Pattern (Top View)