RF5188 RFMD | Alldatasheet

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RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS RF IN RF OUT NC NC VMODE GND VREG NC VCC2 VCC2 VCC2 NC NC VCCBIAS VCC1/IM IM 16 15 14 13 8765 Bias RF5188 3V 1950MHZ W-CDMA LINEAR POWER AMPLIFIER MODULE

  • 3V W-CDMA Band 1 Handsets
  • Multi-Mode W-CDMA 3G Handsets
  • 3V TD-SCDMA Handsets
  • Spread-Spectrum Systems The RF5188 is a high-power, high-efficiency linear ampli- fier module specifically designed for 3V handheld sys- tems. The device is manufactured on an advanced third generation GaAs HBT process, and was designed for use as the final RF amplifier in 3V W-CDMA handheld digital cellular equipment, spread-spectrum systems, and other applications in the 1920MHz to 1980MHz band (Band 1). The RF5188 has a digital control line for low power appli- cations to lower quiescent current. The RF5188 is assem- bled in at 16-pin, 3mmx3mm, QFN package.
  • Input/Output Internally Matched@50 Ω
  • 27.5dBm Linear Output Power
  • 42% Peak Linear Efficiency
  • 28dB Linear Gain
  • -42dBc ACLR @ ±5MHz
  • HSDPA Capable RF5188 3V 1950MHz W-CDMA Linear Power Amplifier Module RF5188PCBA-41X Fully Assembled Evaluation Board Rev A4 060310 B 3.00 A 3.00 Pin 1 ID

2 PLCS

0.15 C 0.15 C

0.203 REF

0.102 REF

0.08 C C 0.08 C 0.925 0.775 1.45 0.05 0.28 0.18TYP Pin 1 ID

0.50 TYP

0.40 0.20TYP

0.10 C ABM

1.45 Shaded areas represent pin 1. Dimensions in mm. Package Style: QFN, 16-Pin, 3x3 RoHS Compliant & Pb-Free Product

Supply Voltage (RF off) +8.0 V Supply Voltage (POUT≤31dBm) +5.2 V Control Voltage (VREG)+ 3 . 9 V Input RF Power +10 dBm Mode Voltage (VMODE)+ 3 . 9 V Operating Temperature -30 to +110 °C Storage Temperature -40 to +150 °C Moisture Sensitivity Level (IPC/JEDEC J-STD-20) MSL 2 @ 260 °C Parameter Specification Unit ConditionMin. Typ. Max. High Gain Mode (VMODE Low) T=25 oC Ambient, VCCBIAS=3.4V , VCC=3.4V, VREG=2.8V , VMODE=0V , and POUT=27.5dBm for all parameters (unless otherwise specified). Modulation is 3GPP 3.2 03-00 DPCCH+1DPDCH. Operating Frequency Range 1920 1980 MHz Linear Gain 26 28.5 32 dB Harmonics -10 dBm f=2fo, 3fo Maximum Linear Output 27.5 dBm Linear Efficiency 38 42 47 % Maximum I CC 352 394 435 mA ACLR1 @ ±5MHz -42 -37 dBc ACLR2 @ ±10MHz -53 -48 dBc Input VSWR 1.7:1 Output VSWR Stability Ruggedness 6:1 No oscillation>-70dBc 10:1 No damage Noise Power -150 dBm/Hz -50< POUT<+27.5dBm, RX=925MHz to 960MHz (EGSM) -133 dBm/Hz -50< POUT<+27.5dBm, RX=1805MHz to 1880MHz (DCS) -140 dBm/Hz -50< POUT<+27.5dBm, RX=2110MHz to 2170MHz (W-CDMA), TX/RX Offset=130MHz -143 dBm/Hz -50< POUT<+27.5dBm, RX=2110MHz to 2170MHz (W-CDMA), TX/RX Offset=190MHz -147 dBm/Hz -50< POUT<+27.5dBm, RX=2400MHz to 2480MHz (Bluetooth) -107 dBm/Hz -50< POUT<+27.5dBm, TX=1932.3MHz to 1980MHz, RX=1893.5MHz to 1919.6MHz (PHS) IM Products IM 5MHz -31 dBc IF offset f O+5MHz with CW signal=-40dBc IM 10MHz -41 dBc IF offset f O+10MHz with CW signal=-40dBc Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Parameter Specification Unit ConditionMin. Typ. Max. Low Gain Mode (VMODE High) T=25 oC Ambient, VCCBIAS=3.4V , VCC=1.5V, VREG=2.8V , VMODE=2.8V, and POUT=16dBm for all parameters (unless oth- erwise specified). Modulation is 3GPP 3.2 03-00 DPCCH+1DPDCH. Operating Frequency Range 1920 1980 MHz Linear Gain 22 26 31 dB Maximum Linear Output 16 dBm Linear Efficiency 18.3 21.0 25.3 % ACLR @ ±5MHz -41 -37 dBc ACLR @ ±10MHz -54 -48 dBc Maximum I CC 105 125 145 mA Input VSWR 2:1 Output VSWR Stability Ruggedness 6:1 No oscillation>-65dBc 10:1 No damage IM Products IM 5MHz -31 dBc IF offset f O+5MHz with CW signal=-40dBc IM 10MHz -41 dBc IF offset f O+10MHz with CW signal=-40dBc Power Supply Supply Voltage (VCC1 and VCC2) 3.2 3.4 4.2 V

0.6 V Low power with DC to DC Converter

VCC Bias 1.5 4.2 V High Gain Idle Current (ICC1/ICC2/ICCBIAS) 70 93 mA V MODE=low and VREG=2.8V, VCC=3.4V Low Gain Idle Current (ICC1/ICC2/ICCBIAS) 60 83 mA V MODE=high and VREG=2.8V , VCC=1.5V VREG Current 1 3 mA VMODE Current 250 uA RF Turn On/Off Time 1.2 6 uS DC Turn On/Off Time 2 25 uS Total Current (Power Down) 0.2 0.5 uA V REG Low Voltage (Power Down) 0 0.5 V VREG High Voltage (Recom- mended) 2.75 2.8 2.95 V VREG High Voltage (Operational) 2.7 3.0 V VMODE Voltage 0 0.5 V High Gain Mode VMODE Voltage 2.0 3.0 V Low Gain Mode

Pin Function Description Interface Schematic 1R F I N RF input internally matched to 50Ω. This input is internally AC-coupled. 2G N D Ground connection. 3V M O D E For nominal operation (High Power mode), VMODE is set LOW. When set HIGH, devices are biased lower to improve efficiency at lower out- put levels. 4V R E G Regulated voltage supply for amplifier bias circuit. In power down mode, both V REG and VMODE need to be LOW (<0.5V). 5N C No connection. Do not connect this pin to any external circuit. 6N C No connection. Do not connect this pin to any external circuit. 7N C No connection. Do not connect this pin to any external circuit. 8N C No connection. Do not connect this pin to any external circuit. 9R F O U T RF output. Internally AC-coupled. 10 VCC2 Output stage collector supply. Please see the schematic for required external components. 11 VCC2 Same as pin 10. 12 VCC2 Same as pin 10. 13 NC No connection. Do not connect this pin to any external circuit. 14 IM Interstage matching. Connect to pin 15. 15 VCC1/IM First stage collector supply and interstage matching. A 4.7 μF decou- pling capacitor may be required. Connect to pin 14. 16 VCCBIAS Power supply input for the DC bias circuitry. Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. The pad should have a short thermal path to the ground plane.

Circuit Optimization for Various Output Power Requirements Output Power (dBm) Matching Component Sample Part Number Typical Efficiency (%) 28 12nH LQG15HN12NJ02D (Murata) 41

27.5 N/A 42

26.5 0.5pF GRM1555C1HR50BZ01E (Murata) 42 26 1.0pF GRM1555C1H1R0BZ01E (Murata) 42 25 1.5pF GRM1555C1H1R5BZ01E (Murata) 41 16 15 14 13 8765 Bias 1 nF VREG VMODE 1 nF 1 nF 10 F VCC 1 nF RF IN RF OUT Place this component next to RF5188 with minimal trace length to the PA. VCC BIAS L2 = 8.2 nH and may be needed to provide isolation between VCC1 and VCC2 depending on layout. VCC BIAS can be connected to VCC; however, VCC must be maintained above 1.5 V. Matching Component

Evaluation Board Schematic 16 15 14 13 8765 Bias 1 nF C40 4.7 μF VREG 50 Ωμ stripJ1 RF IN VMODE C20 4.7 μF 50 Ωμ strip J2 RF OUT 1 nF C10 22 μF VCC2 1 nF GND GND GND P1-1 VMODE P1-2 VRE G CON5 GND GND VCCBIAS P2-1 VCC2 P2-3 VCC1 CON5 DNI DNI 0 Ω VCCBIAS VCC1 C30 4.7 μF P2-4

3μinch to 8μinch gold over 180μinch nickel. process development is recommended. Figure 1. PCB Metal Land Pattern (Top View)

clearance can be provided in the master data or requested from the PCB fabrication supplier. that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 2. PCB Solder Mask Pattern (Top View)