RF5117_1 RFMD | Alldatasheet
Document overview
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Technical content
Features
Single 3.3V Power Supply +30dBm Saturated Output Power 26dB Small Signal Gain High Linearity 1800MHz to 2800MHz Fre- quency Range +17dBm PO, 11G, <3% EVM
Applications
IEEE802.11B WLAN Applications IEEE802.11G WLAN Applications 2.5GHz ISM Band Applications Commercial and Consumer Sys- tems Portable Battery-Powered Equip- ment Spread-Spectrum and MMDS Systems RF5117 3V, 1.8GHz to 2.8GHz Linear Power Amplifier RF5117PCBA-41X Fully Assembled Evaluation Board Rev A13 DS071018 RoHS Compliant & Pb-Free Product Package Style: QFN, 16-Pin, 3 x 3
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Absolute Maximum Ratings Parameter Rating Unit Supply Voltage -0.5 to +6.0 V DC Power Control Voltage (VREG) -0.5 to 3.5 V DC Supply Current 600 mA Input RF Power +10 dBm Operating Ambient Temperature -40 to +85 °C Storage Temperature -40 to +150 °C Moisture Sensitivity JEDEC Level 2 Parameter Specification Unit ConditionMin. Typ. Max. Overall T=25° C, VCC=3.0V, V REG=2.7V , Freq=2 450MHz, circuit per evaluation board schematic. Frequency Range 1800 to 2800 MHz Maximum Linear Output Power With 802.11B modulation (11Mbit/s) and meeting 802.11B spectral mask. VCC=3.0V 22 dBm VCC=5.0V 2 7 dBm Linear Efficiency 25 % Error Vector Magnitude (EVM) 2.5 % P O=1 7dBm, EVM increases over 11g, 54MBPS signal input Small Signal Gain 24 26 28.5 dB P IN=-7dBm Reverse Isolation 30 dB Second Harmonic -35 dBc 802.11B Adjacent Channel Power -38 -32 dBc P OUT=21dBm, V CC=3.0V Alternate Channel Power -56 -52 dBc P OUT=21dBm, V CC=3.0V Isolation 35 45 dB In “OFF” state, P IN=-5.0dBm Input Impedance 50 Ω With external matching Input VSWR 2:1 With external matching Power Down VREG “ON” 2.1 2.7 3.0 V Voltage supplied to control input; device is “ON” VREG “OFF” 0 0.5 V Voltage supplied to control input; device is “OFF” Power Supply Operating Voltage 3.0 to 5.0 V Current Consumption 500 mA At max output power 200 220 mA P OUT=21dBm, V CC=3.0V 110 mA Idle current, V CC=3.0V , VREG=2.7V VREG Current (Total) 5 10 mA V CC=3.0V 10 15 mA V CC=5.0V Caution! ESD sensitive device. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical perfor- mance or functional operation of the device under Absolute Maximum Rating condi- tions is not implied. RoHS status based on EUDirective2002/95/EC (at time of this document revision). The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended appli- cation circuitry and specifications at any time without prior notice.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Pin Function Description Interface Schematic 1R F I N RF input. Matching network with DC block required, see evaluation board schematic for details. 2B I A S G N D 1 Ground for first stage bias circuit. Not connected. See pin 5. 3P W R S E N The PWR SEN and PWR REF pins can be used in conjunction with an exter- nal feedback path to provide an RF power control function for the RF5117. The power control function is based on sampling the RF drive to the final stage of the RF5117. 4P W R R E F Same as pin 3. See pin 3. 5V R E G 1 This pin requires a regulated supply to maintain nominal bias current. 6V R E G 2 Same as pin 5. See pin 5. 7B I A S G N D 2 Ground for second stage bias circuit. For best performance connect to ground with a 10nH inductor. See pin 5. 8N C Not connected. 9N C Not connected. 10 RF OUT RF output and bias for the output stage. The power supply for the output transistor needs to be supplied to this pin. This can be done through a quarter-wave length microstrip line that is RF grounded at the other end, or through an RF inductor that supports the required DC currents. 11 RF OUT Same as pin 10. See pin 10. 12 RF OUT Same as pin 10. See pin 10. 13 VCC Interstage match and bias for first stage output. Connect interstage match- ing capacitor to this pad with a short trace. Connect low-frequency bypass capacitors to this pin with a long trace. See evaluation board layout for details. See pin 1. 14 VCC Same as pin 13. See pin 1. 15 NC Not connected. 16 NC Not connected. Pkg Base GND Ground connection. The backside of the package should be connected to the ground plane through a short path, i.e., vias under the device will be required. RF IN VCC Bond Wire Inductance BIAS RF OUT PWR SEN PWR REF BIAS BIAS VREG1 VREG2 BIAS GND1 BIAS GND2 RF OUT BIAS
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Package Drawing 0.70 0.65 0.05 C 0.90 0.85 -C- SEATING PLANE 12° MAX 0.05 0.00 0.50 0.30 0.50 0.60 0.24 TYP PIN 1 ID R.20 1.45 1.15SQ.
0.10 C ABM
0.30 0.18 -B- 3.00 3.00-A-
0.10 C A
2 PLCS
0.10 C B
2 PLCS 1.37 TYP
1.50 TYP
2.75 SQ NOTES: 1. Shaded pin is lead 1. Pin 1 identifier must exist on top surface of package by identification mark or feature on the package body. Exact shape and size is optional. Dimensions in mm.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Theory of Operation and Application Information The RF5117 is a two-stage device with a nominal gain of 26dB in the 2.4GHz to 2.5GHz ISM band. The RF5117 is designed pri- marily for IEEE802.11B/11G WLAN applications where the availabl e supply voltage and current are limited. This amplifier will operate to (and below) the lowest expected voltage made available by a typical PCMCIA slot in a laptop PC, and will maintain required linearity at decreased supply voltages. The RF5117 requires only a single positive supply of 3.0V nominal (or greater) to operate to full specifications. Power control is provided through two bias control input pins (V REG1 and VREG2), but in most applications these are tied together and used as a single control input. There is some external matching on the input and output of the part, thus allowing the part to be used in other applications outside the 2.4GHz to 2.5GHz ISM band (such as MMDS). Both th e input and the output of the device need a series DC-block- ing capacitor. In some cases, a capacitor used as a matching component can also serve as the blocking cap. The circuit used on the evaluation board is optimized for 3.0V nominal applications. For best results, the PA circuit layout from the evaluation board should be copied as closely as possible, particularly the ground layout and ground vias. Other configurations may also work, but the design process is much easier and quicker if the layout is copied from the RF5117 evaluation board. Gerber files of our designs can be provided upon request. The RF5117 is not a difficult part to implement, but care in circuit layout and component selection is always advisable when designing circuits to operate at 2.5GHz. The most critical passive components in the circuit are the input, interstage and out- put matching components (C1, C5, and C11). In these cases, high -Q capacitors suitable for RF applications are used on our evaluation board (a BOM is available on request). High-Q parts ar e not required in every design, but it is very strongly recom- mended that the original design be implemented with the same or similar parts used on our evaluation board. Then, less costly components can be substituted in their place, making it easy to test the impact of cheaper components on performance. Gen- eral RFMD experience has indicated that th e slightly higher cost of better quality passive components is more than offset by the significant improvements in production yields in large-volu me manufacturing. Using less costly components will typically result in a 1 to 2dB degradation in gain. The interstage matching capacitor, C11, along with the combined inductance of the internal bond wire, the short length of cir- cuit board trace, and the parasitic inductan ce of this capacitor, tunes the peak of the small-signal gain response. The trace length between C11 and pins 13 and 14 should be kept as short as possible. In practice, VCC and the supply for the output stage bias will be tied to the same supply. It is important to isolate C11 from other RF and low-frequency bypass capacitors on this supply line. This can be accomplished using a su itably long transmission line which is RF shorted on the other end. Ideally the length of this line will be a quarter wavelength, but it only needs to be lon g enough so that the effects of other supply bypass capacitors on the interstage match are minimized. If board space is a con- cern, this isolation can also be accomplished with an RF choke inductor or ferrite bead. Additionally, a higher-value capacitor than shown on the application schematic can be used if bypass capacitors must be closer. A Smith Chart can be used to pro- vide initial guidance for value selection and parts placement. Be aware of the self-resonant frequency (SRF) of higher-valued capacitors. The SRF must be above the frequency of operation. The output matching capacitor is C5, located 130mils from the IC (this distance should be duplicated as closely as possible). Due to variations in FR-4 characteristics and PCB manufacturer process variations, some benefit will be obtained from small adjustments to these transmission line lengths when the evaluati on board layout is duplicated on another design. Prior to full rate manufacturing, the board layout of early prototypes shou ld include some additional exposed ground areas around C5 to optimize this part of the circuit. A Smith Chart can help determine the desired value and transmission line length, which can be similarly adjusted on the board prior to production.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. The RF5117 can be used with an IEEE802.11g modulation with a few modifications. Pin 2 should not be connected to ground and a 4.7k Ω resistor should be placed on the V REG1 line. This is done on the evaluation board by cutting the V REG1 trace and placing the resistor on the open line. All other components should not be modified and the IEEE802.11g schematic should be followed as closely as possible. Power sensing is implemented with the PWR SEN and PWR REF line s. The outputs of these pins are transistor collectors and need to be pulled up to the supply through a resistor. PWR REF provides an output current proportional to the output stage bias current, and PWR SEN provides an output current proportional to the total (RF and bias) current of the output stage. The pull- up resistors convert these currents to voltages, and the voltage difference between these two pins is proportional to the RF current. See the graph, “VREF-VSENSE versus POUT”, for the response of this signal. This difference signal can be fed to a power control circuit elsewhere in the end product, or it can be processe d at the PA with additional circuitry and used to adjust the VREG voltage(s) to implement automatic level control. Contact RFMD Sales or Applications Engineering for additional data and guidance in using this feature. The RF5117 has primarily been characterized with a voltage on VREG1 and VREG2 of 2.7VDC. However, the RF5117 will operate from a wide range of control voltages. If you prefer to us e a control voltage that is si gnificantly different than 2.7V DC, contact RFMD Sales or Applications Engineering for additional data and guidance.
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Evaluation Board Schematic - IEEE802.11b 2400MHz to 2483MHz 10 pF 390 Ω 390 Ω C15 1 nF PWR SENSE C16 1 nF PS REF 1 nF VREG1 VREG2 C13 1 nF 10 nH 12 nH 2.7 pF JOH 10 pF 10 pF C10 1 nF C11 6.8 pF JOH 1 nF Notes: 1. C7 - 130 mils from chip. 2. Place C11 as close to chip as possible. Part is Backside Grounded. C12 1 nF RF IN 50 Ω μstrip VCC 50 Ω μstrip RF OUT 1.2 nH Murata C17 2.7 pF JOH C14 1 nF 16 15 14 13 5 6 7 8 Bias C23 1 μF CON5 GND P1-4 VREG1 P1-5 VREG2 P1-1 PS REF P1-2 PWR SENSE GND GND P2-3 VCC CON3 P3-1 VCC CON1 CON1 GND 5117400B C22 10 μF TL1 TL1 = 130 mil (50 Ω)
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Evaluation Board Schematic - IEEE802.11g 2400MHz to 2483MHz 10 pF 390 Ω 390 Ω C15 1 nF PWR SENSE C16 1 nF PS REF 1 nF VREG1 VREG2 C13 1 nF 10 nH 12 nH 2.7 pF JOH 10 pF 10 pF C10 1 nF C11 6.8 pF JOH 1 nF Notes: 1. C7 - 130 mils from chip. 2. Pin 2 cut from ground. 3. C11 must be placed as close to chip as possible. 4. The V REG trace is cut and a 4.7 kΩ resistor is placed on the trace. Part is Backside Grounded. C12 1 nF RF IN 50 Ω μstrip VCC 50 Ω μstrip RF OUT 1.2 nH Murata C17 2.7 pF JOH C14 1 nF 16 15 14 13 5 6 7 8 Bias C23 1 μF CON5 GND P1-4 VREG1 P1-5 VREG2 P1-1 PS REF P1-2 PWR SENSE GND GND P2-3 VCC CON3 P3-1 VCC CON1 CON1 GND 4.3 kΩ 5117400B Place C11 as close to chip as possible C22 10 μF TL1 = 130 mil (50 Ω) TL1
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Evaluation Board Layout Board Size 1.5” x 2.0” Board Thickness 0.031”, Board Material FR-4, Multi-Layer
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Spectral Plot: VCC=3.0V, V REG1 =VREG2=2.7V Spectral Plot: V CC=2.7V , VREG1 =VREG2=2.7V POUT=22.05dBm, P IN=-4. 1dBm, ICC~200mA P OUT=19.05dBm, P IN=-6.8dBm, I CC~150mA ICQ, ICC, POUT versus VREG (Typical) VCC = 3.0, PIN = -5.0 dBm 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 160.0 180.0 200.0 VREG1 , VREG2 (VDC) ICC, ICQ (mA) -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 POUT (dBm) Icq Icc Pout IREG, POUT versus VREG (Typical) VCC = 3.0, PIN = -5.0 dBm 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 VREG1 , VREG2 (VDC) IREG (Total) (mA) -25.0 -20.0 -15.0 -10.0 -5.0 0.0 5.0 10.0 15.0 20.0 25.0 POUT (dBm) Icq Pout Offset 18.8 dB Delta 2 [T1] -40.55 dB
11.723076923 MHz
Delta 3 [T1] -56.56 dB -23.900000000 MHz PRN LVL SWP 20 of 20 A Marker 1 [T1] 22.01 dBm
2.441839744 GHz
802.11B, 5117 proto Ref 30 dBm IFOVL *1R M AVG Comment A: 8 MHz int LPF's, Vcc=3.0 Vreg= 2.7, 200 mA Date: 26.SEP.2001 01:10:29 Center 2.442 GHz 5 MHz/ Span 50 MHz -70 -60 -50 -40 -30 -20 -10 HCenter 2.442 G z 5 MHz/ Span 50 MHz Comment A: 8 MHz int LPF's, Vcc=Vreg= 2.7, 150 mA Date: 26.SEP.2001 01:11:53 Delta 2 [T1] -42.31 dB Delta 3 [T1] -58.92 dB -23.900000000 MHz10 30 Offset 18.8 dB -40 -70 -60 -50 -30 -20 -10 S W P2 0 o f2 0 LVL PRN IFOVL AVG *RM Ref 30 dBm Att 40 dB Marker 1 [T1] RBW 100 kHz* VBW 30 kHz* SWT 35 ms 802.11B, 5117 proto
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. VREF-VSENSE versus POUT -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.5 POUT log10 (VREF-VSENSE)
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com. Evaluation Board with 11g Tuning EVM versus POUT (11g Tuned PA) VCC = 3.0V, Gain = 23dB 100 120 140 14 14.5 15 15.5 16 16.5 17 17.5 18 POUT (dBm) ICC (mA) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 EVM% (added by PA) Icc(mA)2.4Vreg Icc(mA)2.5Vreg Icc(mA)2.6Vreg Icc(mA)2.7Vreg EVM%2.4Vreg EVM%2.5Vreg EVM%2.6Vreg EVM%2.7Vreg EVM versus POUT (11g Tuned PA) VCC = 3.3V, Gain = 23dB 0.0 20.0 40.0 60.0 80.0 100.0 120.0 140.0 POUT (dBm) ICC (mA) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 EVM% (added by PA)Icc(mA)2.4Vreg Icc(mA)2.5Vreg Icc(mA)2.6Vreg Icc(mA)2.7Vreg EVM%2.4Vreg EVM%2.5Vreg EVM%2.6Vreg EVM%2.7Vreg ICC and Gain for 11b Waveform in 11g Tuned PA 20.5 21.5 22.5 23.5 24.5 VREG (V) Gain (dB) 150 160 170 180 190 200 210 220 230 240 250 Total ICC (mA) Gain (3V, Po=22.5dBm) Gain (3.3V, Po=23dBm) Icc (3V, Po=22.5dBm) Icc (3.3V, Po=23dBm)