RF3000

RF3000 RFMD | Alldatasheet

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RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS CCA RX VGC 802.11 Preamble/ Header 802.11 Preamble/ Header Control Port RXVGC DAC Q IN ADC TX VGC DAC I OUT DAC Q OUT DAC Modulator Mode Control Tx Length Tx Signal Service Demodulator RX VGC ANT SEL TX VGC I OUT Q OUT M CLK TX PE RX PE TX DATA TX RDY SPI RX RDY RX DATA CCA VREF IN Q IN I IN ADCI IN Data Converter Reference LNA GS DATA CLK RF3000 SPREAD-SPECTRUM BASEBAND MODEM

• IEEE802.11b Wireless LAN Systems
• ISM Band Systems
• Direct Sequence Systems
• Wireless Modems
• Wireless Point-to-Point The RF3000 is a monolithic CMOS baseband processor. It is suitable for use in 11Mbps IEEE802 .11b wireless LAN systems, and contains all functions required to con- vert a spread-spectrum signal to bit stream. The on-chip equalizer provides protection against multi-path in high data rate modes. All functions are configurable via an SPI port. A complete 2.4GHz radio reference design is avail- able from RFMD.
• On-Chip ADCs and DACs, RSSI, AGC
• BPSK/QPSK/CCK
• 250nS Delay Spread Equalizer
• Supports Antenna Diversity
• Reference Design Available RF3000 Spread-Spectrum Baseband Modem RF3000 PCBA Fully Assembled Evaluation Board Rev A4 031216 0.25 0.19 8° MAX 0° MIN 1.27 0.40 6.20 5.80 0.64 0.30 0.20 4.00 3.80 10.00 9.80 1.75 1.35 0.25 0.10 -A- NOTES: 1. Shaded lead is Pin 1. 2. All dimensions are excluding mold flash. 3. Lead coplanarity - 0.10 with respect to datum "A". Package Style: SSOP-28

Supply Voltage +4.0 V DC Input, Output or I/O Voltage Ground-0.5 to VCC+0.5 V DC Voltage 2.7 to 3.6 V VDDD Output 2.7 V DC Max. Storage Temperature -65 to +150 °C Max. Junction Temperature +150 °C Operating Ambient Temperature -40 to +85 °C Parameter Specification Unit ConditionMin. Typ. Max. See Figures 15 and 16. VCC=3.0V to 3.3V+ 10%, TZ=-40°C to +85°C Power Supply Voltage 2.7 3.3 3.6 V VDDA TBD 2.2 TBD V VDDD, Output Only. VREF 1.6 1.7 1.8 V No current draw. Input Voltage 2.5 VDDA+0.2 V Logical “1” (V IH) -0.2 +0.7 V Logical “0” (V IL) Output Voltage TBD VDDA-1.0 TBD V Logical “1” (V OH) TBD 0.2 0.7 V Logical “0” (V OL) Current Consumption 25 TBD mA Transmit Mode (I TX)

50 TBD mA Receive Mode (I RX)

Sleep Mode 500 500 µA Mode 1, Reset Active, No Clocks (I S1) 1.5 1.5 mA Mode 2, Reset Inactive, No Clocks (I S2) Input Leakage Current 10 µAI I Output Leakage Current 10 µAI O Output Loading 20 20 pF TA=-40°C to +85°C. See Note 1. M CLK Duty Cycle 40/60 60/40 % Rise/Fall - 10 nS All outputs. See Notes 2 and 3. TXPE to I TXDATA to I/QOUT 1.0 µS TXPE Inactive Width 1 µS See Notes 2 and 4. TXRDY Active to 1st DATACLK Hi 500 nS Setup TXDATA to DATACLK 10 nS Hold TXDATA to DATACLK Hi 10 nS Reset to TXPE 100 µS Reset to RXPE 100 µS TXDATA Modulation Extension 2 µS See Notes 2 and 5. RXPE Inactive Width 0 nS See Notes 2 and 6. DATACLK Period 90 nS 11Mbps Mode DATACLK Width Hi or Low 22 44 68 nS 11Mbps Mode DATACLK to RX Data 30 nS RXRDY to 1st DATACLK 40 nS See Note 2. RXDATA to 1st DATACLK 40 nS Setup RXDATA to DATACLK 30 nS RESET Width Active 40 nS See Note 2. RXPE to CCA Valid 15 µS See Note 2. RXPE to RSSI Valid 15 µS See Note 8. I/Q IN to RXDATA 2.25 µS Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Notes: 1. AC tests performed with C L=20pF , IOL=2mA, and I OH=-1mA. Input referenc e level all inputs VCC/2. Test VIH=VCC, VIL=0V; VOH=VOL=VCC/2. 2. Not tested, but characterized at initial design and at major process/design changes. 3. Measured from V IL to VIH. 4. TX PE must be inactive before going active to generate a new packet. 5. I OUT/QOUT are modulated after last chip of valid data to provide ramp-down time for RF/IF circuits. 6. A new search will begin a fter last bit of 802.11 packet in 802.11 modes. 7. Centered about 1.7V V REF. 8. Accurate to within ±3dB of final gain setting. Parameter Specification Unit ConditionMin. Typ. Max. I/Q ADC Full Scale Input Voltage 0.7 +10% V P-P See Note 7. Input Bandwidth 11 MHz Input Capacitance 5 pF Input Impedance 50 k Ω I/Q DAC Full Scale Output Voltage 200 mV See Note 7. Sample Rate 11 MHz Resolution 6 bits DNL 0.5 LSB INL 0.5 1.0 LSB Tested for monotonicity. TX VGC DAC Maximum Gain Output Voltage 1.2 V Minimum Gain Output Voltage 2.0 V Resolution 6 bits DNL 0.5 LSB INL 0.5 1.0 LSB Tested for monotonicity. RX VGC DAC Maximum Gain Output Voltage 1.2 V Minimum Gain Output Voltage 2.0 V Resolution 6 bits DNL 0.5 LSB INL 0.5 1.0 LSB Tested for monotonicity. Control Port Timing Characteristics SPI Mode Mode Switching Characteristics. See Figure 3. C CLK Clock Frequency 6 MHz f CLK CS High Time Between Transmissions 1.1 µSt CSH CS Falling to C CLK Edge 22 nS t CSS C CLK Low Time 68 nS t CLKL C CLK High Time 68 nS t CLKH CD IN to C CLK Setup Time 42 nS t DSU C CLK Rising to Data Hold Time 16 nS t DHLD C CLK Falling to CD OUT Stable 47 nS t PD

Pin Function Description Interface Schematic 1 TXPE Input from the external network processor. The rising edge of TX PE places the transmitter into an active state. The falling edge of TX PE indicates the end of transmission. 2R X P E When active (value '1'), the receiver is powered up and CCA circuitry is active. 3M C L K Master clock. This should be a 44MHz for IEEE802.11b and is used to generate other internally used clocks. 4T X R D Y Indicates that the chip is ready to accept data from the MAC for Tx. 5R X R D Y Indicates that the chip is ready to deliver data to the MAC from Rx. 6V D D D Output from 2.2V internal voltage regulator for digital sections of RF3000. This pin should not be connected to anything. 7G N D D Ground signal for digital power. 8 CCA Clear channel assessment per IEEE802.11b standard. “1” indicates “clear”. 9L N A G S LNA gain select. “1” indicates “high gain”. 10 TXDATA TX data stream input. 11 DATACLK Data clock for TX and RX data. 12 RXDATA RX data stream output. 13 CSb In SPI mode this pin serves as serial port chip select. 14 CCLK Serial port clock. This clock is used for SPI mode. 15 CDIN In SPI mode this pin serves as CDIN input. 16 CDOUT In SPI mode this pin serves as CDOUT output. 17 RXVGC Analog receive variable gain control output: 1.2V to 2.0V. 18 NC Not connected. 19 IIN Analog I input. 20 QIN Analog Q input. 21 VDDA DC power for analog sections 3.3V. 22 GNDA Ground signal for analog power. 23 IOUT Analog I output: 1.6V to 1.8V. 24 QOUT Analog Q output: 1.6V to 1.8V. 25 TXVGC Analog voltage for transmitter variable gain control: 1.2V to 2.0V. 26 ANTSEL Antenna selection signal for diversity receiver. 27 RESET Pin='1' chip reset. Pin='0' standard operation. 28 VREF Reference voltage for internal data converters. Connect to RF2948 V REF or set to 1.7VDC.

Figure 5. RF3000 Block Diagram

The control port is used by the Media Access Controller (MAC) to set up and modify the multiple operation modes of the RF3000. The port is set to SPI mode, with the RF3000 acting as Slave. Note that if no setup information is programmed into the RF3000's registers, it will default to a BPSK 1Mbps IEEE802.11b DSSS mode. If an IEEE802.11b mode is selected in Register 1, other waveform registers are ignored and the appropriate, standards compliant features are All Registers, as defined in the Register Definition section of this datasheet, can be read in real time through this control port. Selected registers, as indicated in the Register section are read-only. The control port of the RF3000 contains a mode to automatically increment the register pointer, allowing reading or writ- ing of adjacent bytes without the need to stop and restart control port access. SPI Mode Description SPI mode pin definitions. SPI Method of Operation Write: To Write into a register of the RF3000, the accessing SPI master needs to simply bring CS low, then Address the RF3000 (01000002) and provide a '0' for the Read/Write-bit. The user should note that all data transfers to/from the RF3000 are msb first. This should be followed by the Auto-increment-bit and the Memory address pointer (MAP), this is an 7-bit value to indicate the initial address for the write process. Register data is to immediately follow the MAP . If the Auto-Increment-bit is set RF3000 will continue to write data 1 byte at a time into the address pointed to by the MAP , and increment the MAP after each byte. When the SPI Master is finished filling registers, it must raise CS to indicate the cycle end. Read: Reading the contents of the RF3000 internal registers, the procedure is actually a write process followed by the read. The SPI Master must bring CS low, to prepare the RF3000 to look for its address. The SPI Master now addresses the RF3000, by placing the RF3000 base address (0100000 2) on the data bus and append a '0' for the Read/Write-bit. The SPI Master must now set the Auto-increment -bit and initialize the 7-bit MAP to the value of the register to be read. The user should raise CS, to end the write portion of the cycle. To complete the Write/Read cycle the SPI Master now needs to lower CS again, and readdress the RF3000 providing a '1' for the Read/Write-bit. Once this is completed the RF3000 will begin outputting the register contents. As long as the CS remains low, and the auto-increment bit is set, the RF3000 will auto-increment the MAP . When the RF3000 reaches Address 31, the MAP will be reset to Register 0 and the process continues. Pin Name Description CS Serial port chip select. A value of '0' is port enabled. C CLK Control port-bit clock input from serial port master. CD IN Serial data input to the RF3000. Data is clocked in on the rising edge of C CLK. CD OUT Serial data output from the RF3000. Data is clocked out on the falling edge of C CLK.

RF3000 Method of Operation The transmitter power enable (TX PE) input enables the transmitter process. (Note: Transmit has priority over receive.) When TX PE is high, the LNA GS signal will be driven low. The TX RDY output indicates the readiness of the RF3000 to receive data for transmit. Transmitted data is passed into the RF3000 through the TXDATA input and clocked by the DATA CLK output. The receiver power enable (RX PE) input enables the receiver, and the receive data ready (RX RDY) signal indicates that received data is upcoming. The RF3000 generates the received data clocks, and outputs the received data, through the RX DATA output. The receiver port also provides a clear channel assessment (CCA) to the MAC. The table below summarizes the operation of the chip. The user should note that RX PE must be High to perform CCA. IEEE802.11b Transmit Modes IEEE802.11b DSSS Transmit Modes The RF3000 supports PSK and CCK DSSS modes defined in IEEE802.11b specification. The RF3000 also supports the optional short preamble and header format as defined in IEEE802.11b. The following section describes IEEE802.1 1b DSSS data transmission. The user must first pr epare the applicable con- trol port registers to determine the mode of operation and the transmission length. The mode of operation must be writ- ten into Register 1, followed by setting the transmission length (in microseconds). The length is to be written into Registers 17 (bit 0 only), 18 and 19. Mode byte values for IEEE802.11b modes are summarized below Once the control port values are written, the RF3000 is ready to transmit data. Optionally, the TX length value can be written during the 128µS of preamble. When the user is ready to transmit, TX PE is driven High. This signals the RF3000 to assemble and transmit the 802.11 preamble and header, as described below. The preamble and header for 1Mbps mode is always transmitted as 1Mbps BPSK. However for 2Mbps, 5.5Mbps and 11Mbps modes, IEEE802 .11b allows a short preamble, which has th e preamble, transmitted as 1Mbps BPSK and the header transmitted as 2Mbps QPSK. The usage of the optional short preamble is selected when the transmission mode is written to the control port. TX PE RX PE Operation 0 0 Standby mode. 0 1 RX is powered up. CCA circuity is active. 1 0 TX is powered up. Begi n TX. CCA is inactive. 1 1 RESERVED IEEE802.11 DSSS Mode Mode Byte Value 1Mbps DBPSK 0x00 16 2Mbps DQPSK Long preamble 0x20 16 2Mbps DQPSK Short preamble 0x30 16 5.5Mbps CCK Long preamble 0x40 16 5.5Mbps CCK Short preamble 0x50 16 11Mbps CCK Long preamble 0x60 16 11Mbps CCK Short preamble 0x70 16 Preamble Header Data 128 1’s SFD (16-bits) Service (8-bits) Signal (8-bits) Length (16-bits) CRC (16-bits) Data (x-bits)

The RF3000 receiver has an interface similar to the transmit port, and provides link support data through the control port. for a valid Barker code PN sequence. exist inside the RF3000 to compensate for manufacturing tolerances in total system gain of an IEEE802.11b radio. AGC algorithm is completely controlled by detection of saturation of the A/D converters. Figure 9. Diversity and AGC Algorithm

The RF3000 begins the algorithm by setting the RXVGC an d LNAGS pins to a predetermined maximum gain condition. packet and cannot be altered until the next packet. data, the demodulator will make fine tuning adjustments to RSSI based on the value of RXVGC. may be noise) initially kicks off the AGC. The AGC then chooses the gain setting to accommodate this level of signal. ting to give the baseband processor an optimum input amplitude for robust demodulation. Figure 10. AGC Decision Structure

High Gain Calibration Procedure Calibration of an IEEE802.11b radio can be accomplished by sending a repetitive pattern to the radio at a known input power, and adjusting the register settings until all packets are correctly received without errors or missing packets. A sim- ple procedure is contained outlined as follows. 1. Write the six LSB's of register 21 to the value 011000 (24 decimal). This will decrease the total system gain. 2. Apply an 1Mbps IEEE802.11b signa l to the input of the radio of a known input power (-75dBm). 3. Decrease the six LSB's of register 21 by one LSB until all packets are received correctly without dropping any pack- ets. 4. Since the input power of the reference signal was set to -75dBm (to eliminate effects of thermal noise), calculate the final register 21 setting by subtracting a known predetermined value from the value found in step 3 of the calibration procedure. Low Gain Calibration Procedure Similar techniques can be applied to calibrate the Low gain settings of the RF3000. As an initial value, the register set- ting in register 20 should be equal to the value of register 21. Register 20 is provided to allow manufacturing calibration to account for reverse isolation variances in the T/R switch if used as an additional pad. Post-AGC When the Barker code is acquired, the RF3000 assigns the ACQ-bit in the mode register to a 1 and proceeds to extract the header information. When the start frame delimiter is identified, the RF3000 will assign a 1 to the SFD-bit in the mode register. The RF3000 w ill now decode the transmissio n mode and data length from the header, and check the header via the 16-bit CRC. The RF3000 will then clock-out 32 bits of header information. This will be the 8-bit RX signal field, followed by the 8-bit RX service field, and then the 16-bit RX length field. The MAC can also read these values through the serial port registers 0x04 through 0x07. The header data will be followed by 16 bit times of no clock transitions. Immediately before providing data, the RF3000 will drive RX RDY High. The received data will be stable on the rising edge of DATA CLK . In the event the header CRC is incorrect, the RF 3000 will bring RX RDY high for the duration of the packet, but no DATA CLK or RX DATA transitions will occur.

The following sections describe each of the blocks, as indicated in the block diagram, that comprise the RF3000. Modulator PSK Modes The RF3000 uses a proprietary architecture that allows the modulation of PSK signals by simply reprogramming the part via the control port. The transmitted data stream is first spread and the resulting data stream is modulated. CCK Mode IEEE802.11b Preamble/Header Creation and Assembly The RF3000 provides circuitry to generate and assemble a preamble and header as specified in the IEEE802.11b spec- ification. The short preamble option for 2Mbps, 5.5Mbps and 11Mbps , as specified in IEEE802.11b, is selectable in the mode control register. The RF3000 will transmit these fields along with a protective CRC-16 for error detection. For other protocols, the preamble/header circuitry is disabled, and packet structures should be generated externally. Demodulator PSK Modes The RF3000 uses a proprietary architectu re that allows the demodulation of PSK signals by simply reprogramming the part via the control port. The received signal is first de-spread and the PSK signal is recovered. CCK Mode In order to perform CCK demodulation, circuitry is provided to pass the output of the A/D converters to a fast Walsh transform (FWT). The output of the FWT is then passed to decision circuitry to determine the received signal. IEEE802.11b Preamble/Header Detection and Extraction Circuitry is provided to search the incoming data for start frame delimiter (SFD) and to obtain length field information as well as modulation type. In 802.11 modes, this circuitry is always active since the preamble and header tells the PHY which modulation type th e data packet is using. The RF3000 will also check the preamble/hea der field for errors by checking the CRC-16 field for errors. Data Converters The RF3000 contains all A/D converters and D/A converters required to implement a transceiver. A/D Converters I/Q A/Ds - These are 4-bit analog-to-digital converters used to sample the data according to the mode of the RF3000. D/A Converters Four (4) digital-to-analog converters are present for transmitter VGC, receiver VGC, I Out, and Q Out. RSSI, CCA and AGC Scramblers Scramblers for whitening the spectrum are provided, as specified in IEEE802.11b. SCRAMBLER NOTE: The data sc rambler defined by IEEE802.11b has a prob ability of 1/128, to lock up scrambling when random data is followed by a repetitive pattern. The patterns identified are: all 0's; all 1’s; repetitive 01's; repeated 0011's; and, repeated 000111's. Once the pattern ceases the scrambler will resume its normal operation.

Switching and detection at beginning of Receive. Equalizer Proprietary architecture, active only in 5.5Mbps and 11Mbps CCK modes. For multipath cancellation, the RF3000 defines the path with the largest magnitude as the main path and all others as secondary paths. The RF3000 equalizer can cancel the two most significant secondary paths. these can either be two (2) post-cursor, echo paths, or they can be one (1) post-cursor and one (1) pre-cursor paths. Pre-cursor delay can be up to one-quarter symbol period. Post-cursor delay can be up to one (1) symbol period. The magnitude of cancelled multipaths up to -3dBc, normalized to the main path.

Control Port Register Definitions for RF3000 Register 0x00 - Reserved This register is reserved. Register 0x01 - Modem Control and RX Status * - Read Only This register is used to setup primary operation of the modem. NOTE: The four (4) LSB’s are read-only and reflect the receiver status. Mode (3-0) - TX Mode Default 802.11 1Mbps DSSS, RX mode detected automatically. NOTE: In 802.11 modes, the received data rate will be accepted from the received header and therefore will be selected automatically. Short Preamble - READ ONL Y 0 - Long Preamble Received 1 - Short Preamble Received ACQ - Receiver acquisition status - READ ONL Y 0 - Not locked 1 - acquired SFD - 802.11 SFD status - Read Only 0 - Not found 1 - SFD detected CRC - 802.11 RX CRC - Read Only 0 - CRC valid 1 - CRC error R7 R6 R5 R4 R3 R2 R1 R0 Mode 3 Mode 2 Mode 1 Mode 0 Short Preamble * ACQ * SFD * CRC * Mode 3 Mode 2 Mode 1 Mode 0 Mode ID Notes 0000 8 0 2 . 1 1 1 M b p s D S S S Default Mode

0001 R e s e r v e d R e s e r v e d

0010 8 0 2 . 1 1 2 M b p s D S S S L o n g p r e a m b l e 0011 8 0 2 . 1 1 2 M b p s D S S S S h o r t p r e a m b l e 0100 8 0 2 . 1 1 5 . 5 M b p s C C K L o n g p r e a m b l e 0101 8 0 2 . 1 1 5 . 5 M b p s C C K S h o r t p r e a m b l e 0110 8 0 2 . 1 1 1 1 M b p s C C K L o n g p r e a m b l e 0111 8 0 2 . 1 1 1 1 M b p s C C K S h o r t p r e a m b l e

1000 BPSK Reserved

1001 Q P S K R e s e r v e d

1010 R e s e r v e d R e s e r v e d

1011 R e s e r v e d R e s e r v e d

Register 0x02 - CCA Control CCA1, CCA0 - 802.11 CCA Mode: RSSI_t - 6-bit RSSI threshold value for CCA. Register 0x03 - Diversity and RSSI Value * - Read Only NOTE: The six (6) LSB’s are read-only and reflect the receiver status. Diversity - RX diversity enable bit. Default - 0 0 - No diversity, ANT SEL pin is forced to Cpantsel. 1 - Diversity active, RF3000 automatically selects ANT SEL pin. Cpantsel - Antenna selection bit in non-diversity mode. Default - 0 0 - ANT SEL forced to 0. 1 - ANT SEL forced to 1. RSSI5-0 - Output of the RSSI A/D - Read Only Register 0x04 - RX Signal Field (Read only) In DSSS modes, this value is the received byte of the received signal field. In FHSS, only the four (4) LSB’s are used. *** - IEEE802.11b proposed modulation rates not currently supported. Register 0x05 - RX Length Field MSB’s (Read only) The upper byte of the length field received. In DSSS mode, this value is the length in microseconds of the received data packet. CCA1 CCA0 RSSI_t5 RSSI_t4 RSSI_t3 RSSI_t2 RSSI_t1 RSSI_t0 CCA1 CCA0 CCA Mode 0 0 RSSI Threshold Sensitive 0 1 Acquisition Sensitive 1X B o t h Diversity Cpantsel RSSI5 * RSSI4 * RSSI3 * RSSI2 * RSSI1 * RSSI0 * RX_Sig7 RX_Sig6 RX_Sig5 RX_Sig4 RX_Sig3 RX_Sig2 RX_Sig1 RX_Sig0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Received Mode 00001010 1 M b p s D S S S 00010100 2 M b p s D S S S 00110111 5 . 5 M b p s D S S S 01101110 1 1 M b p s D S S S

00000000 R e s e r v e d

00000001 1 . 5 M b p s F S K * * *

00000010 R e s e r v e d

00000011 2 . 5 M b p s F S K * * * 00000100 3 M b p s F S K * * * 00000101 3 . 5 M b p s F S K * * * 00000110 4 M b p s F S K * * * 00000111 4 . 5 M b p s F S K * * * RX_LN15 RX_LN14 RX_LN13 RX_LN12 RX_LN11 RX_LN10 RX_LN9 RX_LN8

Register 0x06 - RX Length Field LSB’s (Read only) The lower byte of the length field received. Register 0x07 - RX Service Field (Read only) This register is used per IEEE802.11b specification. RX_SER7 is length field extension in high data rate proposal 802.11b. RX_SER3 is modulation selection bit for high rate transmission. 0 - CCK RX_SER2 signifies Synth Clock to Signal Clock per 802.11 specification. Register 0x08 - Reserved Register 0x09 - Reserved Register 0x0A - Reserved Register 0x0B - Reserved Register 0x0C - Reserved Register 0x0D - Reserved Register 0x0E - Reserved Register 0x0F - Reserved Register 0x10 - Reserved Register 0x11 - TX Variable Gain and TX Length Field Extension TXVGC5-TXVGC0 - Gain setting for transmission. 000000 - Min gain 111111 - Max gain SCRAMBLER - This bit enables and disables the IEEE802.11b data scrambler. TX_LN16 - TX length extension bit as defined in IEEE 802.11b specification. Register 0x12 - TX Length Field MSB’s Register 0x13 - TX Length Field LSB’s Registers 0x12 and 0x13 indicate the number of microseconds that the RF3000 is to transmit after receiving a request to start transmission. R X _ L N 7R X _ L N 6R X _ L N 5R X _ L N 4R X _ L N 3R X _ L N 2R X _ L N 1R X _ L N 0 RX_SER7 RX_SER6 RX_SER5 RX_SER4 RX_SER3 RX_SER2 RX_SER1 RX_SER0 TXVGC5 TXVGC4 TXVGC3 TXVGC2 TXVGC1 TXVGC0 SCRAMBLER TX_LN16 Bit Value Scrambler Mode

0 Enabled

1 Disabled

TX_LN15 TX_LN14 TX_LN13 TX_LN12 TX_LN11 TX_LN10 TX_LN9 TX_LN8 TX_LN7 TX_LN6 TX_LN5 TX_LN4 TX_LN3 TX_LN2 TX_LN1 TX_LN0

Register 0x14 - Low Gain Calibration Bit 5 .. Bit 0:Low Gain Calibration, Range -32 to +16 Register 0x15 - High Gain Calibration Bit 7: A value of ‘1’ enables the channel 14 filter Bit 6: 6dB pad of DS modes Bit 5 .. Bit 0:High Gain Calibration, Range -8 to +31 Register 0x16 - Reserved Register 0x17 - Reserved Register 0x18 - Reserved Register 0x19 - Reserved Register 0x1A - Reserved Register 0x1B - Reserved Register 0x1C - Options Register 1 Bit 7 .. Bit 5:Signed Magnitude Offset for all steps of course AGC. Saturation threshold is 4+ value where V=3< Value <3. Bit 4: A value of ‘1’ allows the AGC algo rithm to retrigger with ADC saturation. Bit 3: A value of ‘1’ enables the alternate TX/RX data bus interface. Bit 2: Reserved, set to ‘0’. Register 0x1D - Options Register 2 Bit 7: LNAGs Delay-When set to ‘1’, this delays the next AGC decision step an extra 1 µS (total of 2µS) if a transition of the LNAGs pin from 1 to 0 occurs. Bit 6 .. Bit 3:Reserved, set to ‘0’. Bit 2: Sets threshold for AGC re-trigger. ‘0’ sets re-trigger threshold to high count. ‘1’ sets re-trigger threshold to low count. Bit 1: Reserved, set to ‘0’. Bit 0: Reserved, set to ‘0’. Register 0x1E - Reserved Register 0x1F - Reserved Reserved Reserved Low_Gain5 Low_Gain4 Low_Gain3 Low_Gain2 Low_Gain1 Low_Gain0 B i t 7 B i t 6B i t 5B i t 4B i t 3B i t 2B i t 1B i t 0 Channel 14 Filter DSSS PAD High_Gain5 High_Gain4 High_Gain3 High_Gain2 High_Gain1 High_Gain0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SAT_THRESH [2] SAT_THRESH [1] SAT_THRESH [0] ALT AGC Enabled Alternative Data Port Interface RESERVED ’0’ RESERVED ‘0’ RESERVED ‘0’ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LNAGS DELAY RESERVED ‘0’ RESERVED ‘0’ RESERVED ‘0’ RESERVED ‘0’ AGC Re-trigger Threshold RESERVED ‘0’ RESERVED ‘0’

28 VREF

27 RESET

26 ANTSEL

25 TXVGC

24 QOUT

23 IOUT

22 GNDA

21 VDDA

20 QIN

19 IIN

17 RXVGC

16 CDOUT

15 CDIN14CCLK

Evaluation Board Schematic (Download Bill of Materials from www.rfmd.com.) CCA TXRDY RXRDY RXPE TXPE MCLK RXDATA CS CCLK CDOUT CDIN LNA CNTL TXDATA DATACLK

5.0 VCC

WE:P READY 0.01 uF 4.7 uF 330 kΩ 4.7 uF

3.3 VCC

0 Ω GNDA GNDD P3 Power GNDA GNDD

5.0 VCC VREF

3000400, Rev. B 1514 1T X P E RXPE MCLK TXRDY RXRDY VDDD GNDD CCA LNA CNTL TXDATA DATACLK RXDATA CSN AD0 CCLK VREF RESET ANTSEL TXVGC QOUT IOUT GNDA VDDA I IN RSSI RSVGC CDOUT SDA CDIN AD1 Q IN RF3000 0.47 µF VDDD GNDD CCA LNA CNTL TXDATA DATACLK RXDATA CS CCLK TXPE RXPE MCLK TXRDY RXRDY 0.47 µF 10 nF IOUT GNDA 3.3VCC Q IN I IN RSSI RXVGC CDOUT CDIN VREF RESET ANTSEL TXVGC QOUT 4.7 kΩ GNDD E10 0.1 µF 10 kΩ 0 Ω

Board Size 2.12” x 3.57” Board Thickness 0.062”, Board Material FR-4