RF2905

RF2905 RFMD | Alldatasheet

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Functional Block Diagram RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA T el (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS 17 18 Linear RSSI Gain Control 31 3034 Prescaler 128/129 or Phase Detector & Charge Pump 41 40 39 38 Lock Detector 42 43 Ref Select 37 1413 DATA OUT RSSI DIV CTRL MOD CTRL OSC SEL MUTE IF2 IN IF1 OUT IF2 BP+ VREF IF IF2 BP- IF1 BP- IF1 BP+ IF1 IN- IF1 IN+ MIX OUT- MIX OUT+ MIX IN LNA OUT RX IN TX OUT LVL ADJ RESNTR+ MOD IN VREF P LOCK DET LOOP FLT OSC B1 OSC B2 OSC E

45 PRESCL OUT

25 FM OUT

433/868/915MHZ FM/FSK/ASK/OOK TRANSCEIVER

• Wireless Meter Reading  Keyless Entry Systems  433/868/915MHz ISM Band Systems  Wireless Data Transceiver  Wireless Security Systems  Battery Powered Portable Devices The RF2905 is a monolithic integrated circuit intended for use as a low cost FM transceiver. The device is provided in 7mmx7mm, 48-lead plastic LQFP packaging and is designed to provide a fully functional FM transceiver. The chip is intended for linear (AM, FM) or digital (ASK, FSK, OOK) applications in the North American 915MHz ISM band and European 433MHz and 868MHz ISM bands. The integrated VCO, dual modulus/dual divide (128/129 or 64/65) prescaler, and reference oscillator require only the addition of an external crystal to provide a complete phase-locked oscillator.  Fully Monolithic Integrated Transceiver  2.7V to 5.0V Supply Voltage  Narrow Band and Wide Band FM/FSK  300MHz to 1000MHz Frequency Range  10dB Cascaded Noise Figure  10mW Output Power at 433MHz RF2905 433/868/915MHz FM/FSK/ASK/OOK Transceiver RF2905 PCBA-L Fully Assembled Evaluation Board (433MHz) RF2905 PCBA-M Fully Assembled Evaluation Board (868MHz) RF2905 PCBA-H Fully Assembled Evaluation Board (915MHz) Rev B11 010516 Dimensions in mm. 7.00 +0 . 1 0s q . 9.00 +0 . 2 0s q . 0.22 +0 . 0 5 7° MAX 0° MIN 0.60 0.15 0.10+ 0.127 1.40 +0 . 0 5 0.50 0.35 0.25 Package Style: LQFP-48, 7x7

Supply Voltage -0.5 to +5.5 V DC Control Voltages -0.5 to +5.0 V DC Input RF Level +10 dBm Output Load VSWR 50:1 Operating Ambient Temperature -40 to +85 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. Overall T=25 °C, VCC =3.6V, Freq=915MHz RF Frequency Range 300 to 1000 MHz VCO and PLL Section VCO Frequency Range 300 to 1000 MHz Prescaler divide ratio 64/65 or 128/129 Prescaler Output Impedance 50 Ω PLL Phase Noise -75 dBc/Hz Freq=915MHz, 10kHz Offset, 5kHz Loop Bandwidth -100 dBc/Hz Freq=915MHz, 100kHz Offset, 5kHz loop Bandwidth Reference Frequency TBD 17 MHz Crystal RS 50 100 Ω Charge Pump Current -40 +40 µA Transmit Section Max Modulation Frequency 2 MHz Min Modulation Frequency Set by loop filter bandwidth Maximum Power Level +7 +10 dBm Freq=433MHz 0 +3 8 dBm Freq=915MHz Power Control Range 12 dB Power Control Sensitivity 10 dB/V Max FM Deviation 200 kHz Instantaneous frequency deviation is inversely proportional with the modulation voltage Antenna Port Impedance 50 Ω TX ENABL=“1”. RX ENABL=“0” Antenna Port VSWR 1.5:1 TX Mode Modulation Input Impedance 4 k Ω Harmonics -23 dBc Spurious dBc Compliant to Part 15.249 and I-ETS 300 220 Overall Receive Section Frequency Range 300 to 1000 MHz Cascaded Voltage Gain 35 dB Freq=433MHz 23 dB Freq=915MHz Cascaded Noise Figure 10 dB Cascaded Input IP3 -31 dBm Freq=433MHz -26 dBm Freq=915MHz RX Sensitivity -95 -101 dBm IF BW=180kHz, Freq=915MHz, S/N=8dB LO Leakage -70 dBm RSSI DC Output Range 0.5 to 2.5 V R LOAD =51k Ω RSSI Sensitivity 25 mV/dB RSSI Dynamic Range 70 80 dB Caution!ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Parameter Specification Unit ConditionMin. Typ. Max. LNA Voltage Gain 23 dB 433MHz 16 dB 915MHz Noise Figure 4.8 dB 433MHz 5.5 dB 915MHz Input IP3 -27 dBm 433MHz -20 dBm 915MHz Input P1dB -37 dBm 433MHz -30 dBm 915MHz Antenna Port Impedance 50 Ω RX ENABL=“1”. TX ENABL=“0” Antenna Port VSWR 1.5:1 RX Mode Output Impedance Open Collector Ω 433MHz Open Collector Ω 915MHz Mixer Single-ended configuration Conversion Voltage Gain 8 dB 433MHz 7 dB 915MHz Noise Figure (SSB) 10 dB 433MHz 17 dB 915MHz Input IP3 -21 dBm 433MHz -17 dBm 915MHz Input P1dB -31 dBm 433MHz -28 dBm 915MHz Maximum Output Voltage V PP Balanced First IF Section IF Frequency Range 0.1 10.7 25 MHz Voltage Gain 34 dB IF=10.7MHz, Z L=330 Ω Noise Figure 13 dB IF1 Input Impedance 330 Ω IF1 Output Impedance 330 Ω Second IF Section IF Frequency Range 0.1 10.7 25 MHz Voltage Gain 60 dB IF=10.7MHz IF2 Input Impedance 330 Ω IF2 Output Impedance 1 k Ω At IF2 OUT- pin Demod Input Impedance 10 k Ω FM Output Impedance 500 Ω Data Output Impedance >1 ΜΩ FM Output Bandwidth 500 kHz 3dB Bandwidth, Dependent upon IF band- width and Discriminator. Data Output Bandwidth 500 kHz 3dB Bandwidth, Z LOAD =1M Ω || 3pF; Depen- dent upon IF bandwidth and Discriminator. Data Output Level 0.3 V CC -0.3 V Z LOAD =1M Ω || 3pF; Output voltage is pro- portional with the instantaneous frequency deviation. FM Output DC Level 2.6 V Z LOAD >10kΩ FM Output AC Level 200 mV PP ZLOAD >10kΩ

Parameter Specification Unit ConditionMin. Typ. Max. Power Down Control Logical Controls “ON” 2.0 V Voltage supplied to the input Logical Controls “OFF” 1.0 V Voltage supplied to the input Control Input Impedance 25k Ω Turn On Time 4 ms Reference Crystal=7.075MHz Turn Off Time 4 ms Dependent upon reference crystal. Higher RX to TX and TX to RX Time 4 ms frequencies reduce turn on/off times Power Supply Voltage 3.6 V Specifications 2.7 to 5.0 V Operating limits Current Consumption 22 25 34.5 mA TX Mode, LVL ADJ=3.6V 8 10 13.5 mA TX Mode, LVL ADJ=0V 7 9 12 mA RX Mode 1 µA Power Down Mode which sets: PLL ENABL, TX ENABL, RX ENABL, LVL ADJ, OSC SEL, and MUTE=0V 5.3 8 10 mA PLL Only Mode

Pin Function Description Interface Schematic 1 RX ENABL Enable pin for the receiver circuits. RX ENABL>2.0V powers up all receiver functions. RX ENABL<1.0V turns off all receiver functions except the PLL functions and the RF mixer. 2 TX ENABL Enables the transmitter circuits. TX ENABL>2.0V powers up all trans- mitter functions. TX ENABL<1.0V turns off all transmitter functions except the PLL functions. 3T X O U T RF output pin for the transmitter electronics. TX OUT output impedance is a low impedance when the transmitter is enabled. TX OUT is a high impedance when the transmitter is disabled. 4G N D 2 Ground connection for the 40dB IF limiting amplifier and Tx PA func- tions. Keep traces physically short and connect immediately to ground plane for best performance. 5R X I N RF input pin for the receiver electronics. RX IN input impedance is a low impedance when the transmitter is enabled. RX IN is a high imped- ance when the receiver is disabled. 6G N D 1 Ground connection for RF receiver functions. Keep traces physically short and connect immediately to ground plane for best performance. 7L N A O U T Output pin for the receiver RF low noise amplifier. This pin is an open collector output and requires an external pull up coil to provide bias and tune the LNA output. 8G N D 3 Same as pin 4. 9 MIX IN RF input to the RF Mixer. An LC matching network between LNA OUT and MIX IN can be used to connect the LNA output to the RF mixer input in applications where an image filter is not needed or desired.

10 GND5 GND5 is the ground connection shared by the input stage of the trans-

mit power amplifier and the receiver RF mixer. 11 MIX OUT+ Complementary (with respect to pin 12) IF output from the RF mixer. Interfaces directly to 10.7MHz ceramic IF filters as shown in the appli- cation schematic. A pull-up inductor and series matching capacitor should be used to present a 330Ω termination impedance to the ceramic filter. Alternately, an IF tank can be used to tailor the IF fre- quency and bandwidth to meet the needs of a given application. 12 MIX OUT- IF output from the RF mixer. For a balanced mixer output, pull-up induc- tors from pin 11 and 12 to V CC and a capacitor between the pins should be used. The sum of the total pull-up inductance should be used to res- onate the capacitor between pins 11 and 12. DC blocking capacitors of 10nF can then be used to connect the balanced output to IF1 IN+ (pin 13) and IF1 IN- (pin 14). See pin 11. 50 kΩ RX ENABL 40 kΩ 20 kΩ TX ENABL TX OUT VCC RX IN 500 LNA OUTVCC GND5 MIX IN MIX OUT-MIX OUT+ 15 pF 15 pF GND5 GND5

Pin Function Description Interface Schematic 13 IF1 IN+ Balanced IF input to the 40dB limiting amplifier strip. A 10nF DC block- ing capacitor is required on this input. 14 IF1 IN- Functionally the same as pin 13 except inverting node amplifier input. In single-ended applications, this input should be bypassed directly to ground through a 10nF capacitor. See pin 13. 15 IF1 BP+ DC feedback node for the 40dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. See pin 13. 16 IF1 BP- Same as pin 15. See pin 13. 17 IF1 OUT IF output from the 40dB limiting amplifier. The IF1 OUT output presents a nominal 330Ω output resistance and interfaces directly to 10.7MHz ceramic filters. 18 IF2 IN Balanced IF input to the 60dB limiting amplifier strip. A 10nF DC block- ing capacitor is required on this input. The IF2 IN input presents a nom- inal 330Ω input resistance and interfaces directly to 10.7MHz ceramic filters.19 GND6 Ground connection for 60dB IF limiting amplifier. Keep traces physically short and connect immediately to ground plane for best performance. 20 VREF IF DC voltage reference for the IF limiting amplifiers. A 10nF capacitor from this pin to ground is required. 21 IF2 BP+ DC feedback node for the 60dB limiting amplifier strip. A 10nF bypass capacitor from this pin to ground is required. See pin 18. 22 IF2 BP- Same as pin 21. See pin 18. 23 MUTE This pin is used to mute the data output (DATA OUT). MUTE>2.0V turns the DATA OUT signal on. MUTE<1.0V turns the DATA OUT sig- nal off. The MUTE signal should be logic low in the Sleep Mode.

24 RSSI A DC voltage proportional to the received signal strength is output from

this pin. The output voltage range is 0.5V to 2.5V, into 51kΩ load, and increases with increasing signal strength. 25 FM OUT Linear output from the FM demodulator. This pin is used in analog applications when signal fidelity is important. This output is inverted for low side injection of the LO and normal for high side injection. 26 DATA OUT Demodulated data output from the demodulator. Output levels on this are TTL/CMOS compatible. The magnitude of the load impedance is intended to be 1MΩ or greater. When using a RF2905 transmitter and receiver back to back a data inversion will occur, when the LO is low side injected. A high side injection will add an inversion of the Rx data. IF1 IN-IF1 IN+ 330 330 60 kΩ 60 kΩ IF1 BP+ IF1 BP- IF1 OUT IF2 IN 330 330 60 kΩ 60 kΩ IF2 BP+ IF2 BP- 25 kΩ 75 kΩ MUTE VCC RSSI FM OUT DATA OUT

Pin Function Description Interface Schematic 27 DEMOD IN This pin is the input to the FM demodulator. This pin is NOT AC cou- pled. Therefore, a DC blocking capacitor is required on this pin to avoid shorting the demodulator input with the LC tank. A ceramic discrimina- tor or DC blocked LC tank resonant at the IF should be connected to this pin. 28 IF2 OUT Balanced IF output from the 60dB limiting amplifier strip. This pin is intended to be connected to pin 27 through a 4pF (suggested) capaci- tor and an FM discriminator circuit.

29 VCC6 This pin is used is supply DC bias to the second IF amplifier, Demodu-

lator and Data Slicer. An IF bypass capacitor should be connected directly to this pin and returned to ground. A 10nF capacitor is recom- mended for 10.7MHz IF applications.

30 RESNTR+ This port is used to supply DC voltage to the VCO as well as to tune the

center frequency of the VCO. Equal value inductors should be con- nected to this pin and pin 31 although a small imbalance can be used to tune in the proper frequency range. 31 RESNTR- See RESNTR+ description. See pin 30. 32 VCC2 This pin is used is supply DC bias to the VCO, prescaler, and PLL. An RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applica- tions.

33 GND4 GND4 is the ground shared on chip by the VCO, prescaler, and PLL

electronics.

34 MOD IN FM analog or digital modulation can be imparted to the VCO through

this pin. The VCO varies in accordance to the voltage level presented to this pin. To set the deviation to a desired level, a voltage divider refer- enced to Vcc is the recommended. This deviation is also dependent upon the overall capacitance of the external resonant circuit. See pin 30. 35 DIV CTRL This pin is used to select the desired prescaler divisor. A logic high (DIVCTRL>2.0V) selects the 64/65 divisor. A logic low (DIVCTRL<1.0V) selects the 128/129 divisor. 36 MOD CTRL This pin is used to select the prescaler modulus. A logic high (MOD CTRL>2.0V) selects 64 or 128 for the prescaler divisor. A logic low (MOD CTRL<1.0V) selects 65 or 129 for the prescaler divisor. D u et od e s i g nt i m i n gc o n s t r a i n t s ,t h ep r e s c a l e ri nt h ed i v i d eb y6 5o r 129 modes has a limited frequency range for accurate operation. These two modes are not recommended for use from 400MHz to 460MHz. 37 OSC SEL A logic high (OSC SEL>2.0V) applied to this pin powers on reference oscillator 2 and powers down reference oscillator 1. A logic low (OSC SEL<1.0V) applied to this pin powers on reference oscillator 1 and powers down reference oscillator 2.

38 OSC B2 This pin is connected directly to the reference oscillator 2 transistor

base. The intended reference oscillator configuration is a modified Col- pitts. DEMOD IN 10 kΩ VCC IF2 OUT RESNTR-ESNTR+ 4k Ω MOD IN DIV CTL MOD CTL OSC E OSC B1 OSC B2

Pin Function Description Interface Schematic

39 OSC E This pin is connected directly to the emitter of the reference oscillator

transistors. See pin 38.

40 OSC B1 This pin is connected directly to the reference oscillator 1 transistor

base. The intended reference oscillator configuration is a modified Col- pitts. See pin 38. 41 LOOP FLT Output of the charge pump, and input to the VCO control. An RC net- work from this pin to ground is used to establish the PLL bandwidth. 42 VREF P Bypass pin for the prescaler reference voltage. A 33nF capacitor to ground is needed to suppress reference spurs in the device. This value may be different for different PCB arrangements. 43 LOCK DET This pin provides an analog output indicating the lock status of the PLL. The amplitude of this signal is typically 200mV PP around a DC level of VCC -0.1V.

44 VCC1 This pin is used to supply DC bias to the LNA, Mixer, first IF Amp, and

Bandgap reference. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recom- mended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applications.

45 PRESCL

Dual-modulus/Dual-divide prescaler output. The output can be inter- faced to an external PLL IC for additional flexibility in frequency pro- gramming.

46 VCC3 This pin is used to supply DC bias and collector current to the transmit-

ter PA. A RF bypass capacitor should be connected directly to this pin and returned to ground. A 22pF capacitor is recommended for 915MHz applications. A 68pF capacitor is recommended for 433MHz applica- tions. 47 LVL ADJ This pin is used to vary the transmitter output power. An output level adjustment range greater than 12dB is provided through analog volt- age control of this pin. DC current of the transmitter power amp ia also reduced with output power. This pin MUST be low when the transmitter is disabled. 48 PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high (PLLENABL>2.0V) powers up the VCO and PLL electronics. A logic low (PLLENABL<1.0V) powers down the PLL and VCO. LOOP FLT VCC LOCK DET 20 kΩ VCC PRESCL OUT 400 4k Ω LVL ADJ 40 kΩ 50 kΩ PLL ENABL

RF2905 Theory of Operation and Application Information The RF2905 is a part of a family of low-power RF transceiver IC’s that was developed for wireless data communication devices operating in the European 433/ 868MHz ISM bands or 915MHz US ISM band.This IC has been implemented in a 15GHz silicon bipolar pro- cess technology that allows low-power transceiver operation in a variety of commercial wireless products. In its basic form, the RF2905 can implement a two-way half duplex FSK transceiver with the addition of some crystals, filters, and passive components. There are two reference crystals that allow for the transmit carrier and the receiver LO to be independently generated with a common PLL and VCO. The receiver IF section is optimized to interface with low cost 10.7MHz ceramic filters but has a -3 dB bandwidth of 25MHz and can still be used (with lower gain) at higher fre- quency with the other type of filters. The PA output and LNA input are available on separate pins and are designed to be connected together through a DC blocking capacitor. In the Transmit mode, the PA will have a 50Ω impedance and the LNA will be a high impedance. In Receive mode, the LNA will have a 50Ω interface and the PA will have a high impedance. This eliminates the need for a TX/RX switch and allows a s i n g l eR Ff i l t e rt ob eu s e di nt r a n s m i ta n dr e c e i v e modes. Separate access to the PA and LNA allow the RF2905 to interface with external components such as higher power PA’s, lower NF LNA’s, upconverters, and downconverters for a variety of implementations. FM/FSK SYSTEMS The MOD IN pin drives an internal varactor for modu- l a t i n gt h eV C O .T h i sp i nc a nb ed r i v e nw i t hav o l t a g e level needed to generate the desired deviation. This voltage can be carried on a DC bias to select the desired slope (deviation/volt) for FM systems. Or, a resistor divider network referenced to Vcc or ground can divide down logic level signals to the appropriate level for a desired deviation in FSK systems. On the receiver demod, two outputs are available, an analog FM output and a digital FSK output. The FM output is a buffered signal coming off of the quadrature demodulator. The digital output is generated by a data slicer that is DC coupled differentially to the demodula- tor. An on-chip 1.6MHz RC filter is provided at the demodulator output to filter the undesired 2xIF product. This balanced data slicer has a speed advantage over a conventional adaptive data slicer where a large capacitor is used to provide DC reference for bit deci- sion. Since the balanced data slicer does not have to charge a large capacitor, the RF2905 exhibits a very fast response time. For best operation of the on-chip data slicer, FM deviation needs to exceed the carrier frequency error anticipated between the receiver and transmitter with margin. The data slicer itself is a transconductance amp and the DATA OUT pin is capable of driving rail to rail out- put only into a very high impedance and small capaci- tance. The amount of capacitance will determine the bandwidth of the DATA OUT. At a 3pF load, the band- width is in excess of 500kHz. The rail to rail output of the data slicer is also limited by the frequency deviation and bandwidth of the IF filters. With the 180kHz band- width filters on the eval boards, the rail to rail output is limited to less than 140kHz. Choosing the right IF bandwidth and deviation vs. data rate (mod index) is important in evaluating the applicability of the RF2905 for a given data rate. While this type of data slicer is best for wideband devi- ation, it can also work for narrowband if care is taken to minimize frequency differences. By loading down the DATA OUT pin, the output will be limited to a small data signal on a DC carrier. With this signal, an external data slicer can be used to achieve higher data rates or improve performance in narrow deviations. Alterna- tively, an AFC loop can be added to correct for fre- quency errors with a few external components. For FM or FSK modulation, an internal varactor is used to directly modulate the VCO with the baseband data. The primary consideration when directly modulating the VCO is the data rate verses PLL loop bandwidth. The PLL will track out the modulation to the extent of its loop bandwidth which distorts the modulating data. Therefore, the lower frequency components of the modulating data should be 5 to 10 times the loop band- width to minimize the distortion. The lower frequency components are generated by long strings of 1’s or 0’s in the data stream. By limiting the number of consecu- tive, same bits, the lower frequency component can be set. In addition, the data stream should be balanced to minimize distortion. Using a coding pattern such as Manchester is highly recommended to optimize system performance. The PLL loop bandwidth is important in several other system parameters. For example, switching from trans- mit to receive requires the VCO to retune to another frequency. The switching speed is proportional to the loop bandwidth, the higher the loop bandwidth, the

distortion of the modulation data. changes due to load pulling. (relative to the data rate) DC reference to a data slicer. B o t ht h eR XI Na n dT XO U Th a v eaD Cb i a so nt h e m . be needed to separate the DC of RX IN and TX OUT. route these signals keeping them physically short. recommended layout pattern for the VCO components. possible with the bias inductor being further away. desired, a high impedance filter is recommended. Figure 1. Recommended VCO Layout

shows a schematic implementation of a LC tank. parallel resistor is used with a ceramic discriminator). Where D is a factor to account for the loop damping. frequency change during the transient. To lock faster, we need to minimize C.

1. To this end, use the divide by 128 rather than the
2. Design the loop filter for the minimum phase margin

this allows C to be kept at a minimum.

1. Design the loop filter for the highest loop cut fre-

Several issues arise in the selection of the crystals. should be evaluated for each application. Figure 2. LC Type Discriminator Circuit

13 16 1514 17 18 19 20 21 22 23 24

Detector & Charge Pump 41 40 39 38 Lock Detector 4243 Ref Select 37 1413 DATA OUT RSSI DIV CTRL MOD CTRL OSC SEL MUTE 2120 221615 LVL ADJ LOCK DET+ 4.7 nH 4.7 nH VCC 2.7 k Ω3.3 nF 47 nF Filter 22 pF 10 nH 10 pF VCC 8.2µ H 22 pF VCC Filter Filter FM Disc. 51 kΩ 10 pF TX DATA 3.9 kΩ 5p F 22 pF10 nF 100 pF 100 pF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 5p F 100 pF 100 pF 100 pF 0.1 uF 10 Ω 11 pF 10 Ω 10 nF 10 Ω 10 nF D1 : SMV1233-011 22 pF 10 Ω VCC 10 nF PLL ENABL RX ENABL TX ENABL 22 pF VCC 10 nF PLL LOOP BANDWIDTH ~5 kHz 10 Ω46 4.7 uF 22 pF VCC 10 nF 10 Ω nF pF

Detector & Charge Pump 41 40 39 38 Lock Detector 4243 Ref Select 37 1413 DATA OUT RSSI DIV CTRL MOD CTRL OSC SEL MUTE 2120 221615 LVL ADJ LOCK DET+ 6.8 nH 6.8 nH VCC 2.7 kΩ3.3 nF 47 nF Filter 22 pF 10 nH 10 pF VCC 8.2 uH 22 pF VCC Filter Filter FM Disc. 51 kΩ 10 pF TX DATA 3.9 kΩ 3p F 22 pF10 nF 100 pF 100 pF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 5p F 100 pF 100 pF 100 pF 0.1 uF 10 Ω 11 pF 10 Ω 10 nF 10 Ω 10 nF D1 : SMV1233-011 22 pF 10 Ω VCC 10 nF PLL ENABL RX ENABL TX ENABL 22 pF VCC 10 nF PLL LOOP BANDWIDTH ~5 kHz 10 Ω 4.7 uF 22 pF VCC 10 nF 10 Ω nF pF

Detector & Charge Pump 41 40 39 38 Lock Detector 4243 Ref Select 37 1413 DATA OUT RSSI DIV CTRL MOD CTRL OSC SEL MUTE 2120 221615 LVL ADJ LOCK DET+ 2.7 kΩ3.3 nF 47 nF Filter 22 pF 47 nH 33 pF VCC 8.2 uH 22 pF VCC Filter Filter FM Disc. 51 kΩ 10 pF TX DATA 3.9 kΩ 3p F 22 pF10 nF 100 pF 100 pF 10 nF 10 nF 10 nF 10 nF 10 nF 10 nF 5p F 100 pF 100 pF 100 pF 0.1 uF 10 Ω 11 pF 10 Ω 10 nF 10 Ω 10 nF D1 : SMV1233-011 22 pF 10 Ω VCC 10 nF PLL ENABL RX ENABL TX ENABL 22 pF VCC 10 nF PLL LOOP BANDWIDTH ~5 kHz 10 Ω 4.7 uF 22 pF VCC 10 nF 10 Ω nF pF

Evaluation Board Schematic (Download Bill of Materialsfrom www.rfmd.com.) 48 45 4647 44 43 42 41 40 39 38 37 13 16 1514 17 18 19 20 21 22 23 24 VCC MOD CTRL P3-1 P3-3 GND PLL ENABL TX ENABLP1-1 P1-3 GND OSC SEL GND P4-2 P4-3 RX ENABL P4-4 P4-5 DIV CTRL MUTE N/C LVL ADJP2-1 P2-3 GND

3 LOCK DETP5-1

L1* C5* L2 8.2 uH 22 pF 10 pF 10 nF 10 Ω 10 nF SFECV10.7 MS3S-A-TC BW=180kHz C10 10 nF C11 10 nF 10 nF SFECV10.7 MS3S-A-TC BW=180kHz C13 10 nF C14 10 nF C12 10 nF MUTE 51 kΩ C15 1n F R22 N/C SLICER IN FM OUT DATAOUT C 1 61 0n F C 1 74p F R13 1.5 k Ω CDF107B-A0.001 DISC 0 Ω C21 22 pF 10 Ω D1 L4* L5*C18* 10 Ω C22 10 nF C20 10 nF C19 22 pF X1*X2* OSC SEL MOD CTRL DIV CTRL MOD IN R17 3.9 kΩ C26 3.3 nF C27 47nF C1 100 pF 100 pF L7*L6* C36* C39*C35* RF RX ENABL TX ENABL PLL ENABL LVL ADJ C31 22 pF C30 10 nF R12 10 Ω C34 4.7 µF C32 10 nF C33 22 pF R15 0 Ω R14 0 Ω 2.2 µH C37 120 pF MIXOUT C38 0.1 µF R23 0 Ω 2N3904 R16 TBD R10 50 kΩ R21 50 kΩ 1 C28 10 nF C40 33 nF R11 1M Ω C29 1nF R18 TBD LOCK DET Test Only Not Populated LMC7211 SLICER IN Circuit not populated. Optional Lock Detector or OOK Data Slicer SMV1233-011Linear RSSI Gain Control Prescaler 128/129 or Phase Detector & Charge Pump Lock Detector Ref Select C24 100pF VCC VCC VCC 10 Ω 8.2 kΩ VCC R9* L (433MHz) M (868MHz) H (915MHz) Board C35 (pF) 8.2 8.2 L6 (nH) Jumper Jumper L7 (nH) C18 (pF) N/C N/C C39 (pF) L1 (nH) C5 (pF) 4.7 4.7 L4,L5(nH) 2.4 2.7 2.7 R9 (kΩ ) 6.78 13.577344 7.15909 X1 (MHz) 6.612 13.410156 7.07549 X2 (MHz) 2905400-, 401-, 402- C41 3-10 pF C42 3-10 pF C25 100 pF C23 100 pF

Board Size 3.05” x 3.05” Board Thickness 0.031”, Board Material FR-4, Multi-Layer (Same board layout is used for the -L, -M, and -H versions.)

1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 LNA S11 Swp Max 1.2GHz Swp Min 0.3GHz RXoffTXoff RXonTXoff 0.3GHz 0.3GHz 1.0 1.0-1.0 10.0 10.0 -10.0 5.0 5.0 -5.0 2.0 2.0 -2.0 3.0 3.0 -3.0 4.0 4.0 -4.0 0.2 0.2 -0.2 0.4 0.4 -0.4 0.6 0.6 -0.6 0.8 0.8 -0.8 RF OUT S22 Swp Max 1.2GHz Swp Min 0.3GHz TXonRXoff 0.3GHz

Freq. = 915 MHz, VCC = 3.6V, RLoad = 51 kΩΩΩΩ 0.0 0.5 1.0 1.5 2.0 2.5 Received Power (dBm) RSSI Output (Volts) Modulation Deviation Freq. = 915 MHz, VCC = 2.7 V, LVL ADJ = 2.7 V 0.0 100.0 200.0 300.0 400.0 500.0 600.0 MOD IN (Volts) Deviation From Carrier (kHz) Modulation Deviation Freq. = 915 MHz, VCC = 3.3 V, LVL ADJ = 3.3 V 0.0 100.0 200.0 300.0 400.0 500.0 600.0 MOD IN (Volts) Deviation From Carrier (kHz) Modulation Deviation Freq. = 915 MHz, VCC = 5.0 V, LVL ADJ = 5.0 V 0.0 200.0 400.0 600.0 800.0 1000.0 1200.0 MOD IN (Volts) Deviation From Carrier (kHz)

TX Power Output and ICC versus Level Adjust at 433 MHz, 3.6 V VCC -15.0 -10.0 -5.0 0.0 5.0 10.0 LVL ADJ (V) RF PO (dBm) 5.0 10.0 15.0 20.0 25.0 30.0 ICC (mA) P out (dB) Icc (mA) TX Power Output and ICC versus Level Adjust at 868 MHz, 3.6 V VCC -15.0 -10.0 -5.0 0.0 5.0 10.0 LVL ADJ (V) RF PO (dBm) 5.0 10.0 15.0 20.0 25.0 30.0 ICC (mA) P out (dB) Icc (mA) TX Power Output and ICC versus Level Adjust at 905 MHz, 3.6 V VCC -15.0 -10.0 -5.0 0.0 5.0 10.0 LVL ADJ (V) RF PO (dBM) 5.0 10.0 15.0 20.0 25.0 30.0 ICC (mA) Po u t( d B ) Icc (mA) RX Mode Current versus VCC Freq = 905 MHz 6.00 7.00 8.00 9.00 10.00 11.00 12.00 VCC (V) ICC (mA) Icc (mA) TX Power Output and ICC versus VCC at 905 MHz, LVL ADJ = VCC 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 VCC, LVL ADJ (V) RF PO (dBm) 10.00 15.00 20.00 25.00 30.00 35.00 40.00 ICC (mA) Power(dBm) Icc(mA)