RF2402

RF2402 RFMD | Alldatasheet

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Functional Block Diagram RF Micro Devices, Inc.

7625 Thorndike Road

Greensboro, NC 27409, USA T el (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS /Gfc SiGe HBT Si CMOS VDD2 VDD1 VPD I SIG I REF Q REF Q SIG RF OUT GND2 GND GND GND1 PHASE LO IN POWER CONTROL Σ +45° -45° RF2402 UHF QUADRATURE MODULATOR  Digital and Spread-Spectrum Systems  GMSK, QPSK, DQPSK, QAM Modulation  GSM and D-AMPS Cellular Systems  AM, SSB, DSB Modulation  Image-Reject Upconverters The RF2402 is a monolithic integrated universal modula- tion system capable of generating modulated AM, PM, or compound carriers in the UHF frequency range. The IC contains all of the required components to implement the modulation function including differential amplifiers for the baseband inputs, a 90° hybrid phase splitter, limiting LO amplifiers, two balanced mixers, a combining amplifier, and an output RF amplifier which will drive a 50Ω load. Component matching, which can only be accomplished with monolithic construction, is used to full advantage to obtain excellent amplitude balance and high phase accu- racy. The unit features low power consumption, single power supply operation, and adjustment free operation with no external parts required to operate the part as specified.  Single 3V to 5V Power Supply  Low Power and Small Size  CMOS Compatible Power Down Control  Excellent Amplitude and Phase Balance  Low Broadband Noise Floor  600MHz to 1000MHz Operation RF2402 UHF Quadrature Modulator RF2402 PCBA Fully Assembled Evaluation Board Rev B1 010329 .157 .150 .050 .016 8 °MAX 0°MIN .065 .043 .244 .228 .010 .007 .344 .337 .010 .004 .050 .018 .0141 Package Style: SOP-14

Supply Voltage (VDD ) -0.5 to +7.5 V DC Power Down Voltage -0.5 to V DD +0.4 V DC Input LO and RF Levels +6 dBm Operating Ambient Temperature -40 to +85 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. Carrier Input T=25°C, VCC =5V DC , I&Q inputs=2VPP Frequency Range 600 to 1000 MHz Power Level -3 to +6 dBm Input VSWR 1.2:1 With external 50 Ω termination. Input Impedance 200-j200 Ω At 900MHz, without external 50Ω termina- tion. Modulation Input Frequency Range DC to 100 MHz Reference Voltage (VREF ) 2.0 to 3.0 V Modulation (I&Q) V REF ±2 V I & Q signals for 0dBm output power. Maximum Modulation (I&Q) V REF ±2.5 V In-phase and quadrature signals. Input Resistance 3000 Ω DC Offset 50 150 mV I SIG -IREF and QSIG -QREF for DC balance Amplitude Error (I/Q) 0.2 dB Quadrature Phase Error ±3 ° From 800MHz to 1000MHz. RF Output VDD =5V , LO P ower=0dBm, LO Freq=900MHz, SSB Output Power 0 dBm Output Impedance 50 Ω Output VSWR 1.5:1 Broadband Noise Floor -155 dBm/Hz Sideband Suppression 25 dB Carrier Suppression 40 dB Modulation DC offset externally adjusted for optimum suppression. Suppression is typi- cally better than 25dB without adjustment. Power Down Turn On/Off Time <100 ns PD Input Resistance >1 M Ω Power Down “ON” V CC V Threshold voltage Power Down “OFF” 0 V Threshold voltage Power Supply Voltage 5 V Specifications 3 to 5.5 V Operating Limits Current 28 39 mA Operating 0.5 2 mA Power Down Caution!ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Pin Function Description Interface Schematic 1V D D 2 Power supply for the RF Output amplifier. An external RF bypass capacitor is needed. The trace length between the pin and the bypass capacitor should be minimized. The ground side of the capacitor should connect immediately to the ground plane. 2V D D 1 Power supply for all other circuits. An external RF bypass capacitor is needed. 3P D Power Down control. When this pin is 0V all circuits are turned off, and when +5V all circuits are operating. This is a high impedance input, internally connected to the gates of a few FETs. To minimize current consumption in power down mode, this pin should be as close to 0V as possible. In order to maximize output power this pin should be as close to +5V as possible during normal operation. 4I S I G Baseband input to the I mixer. This pin is DC coupled. Maximum output power is obtained when the input signal has a peak to peak amplitude of 5V. The DC level supplied to this pin should be 2.5±0.5V. The SIG and REF inputs are inputs of a differential amplifier. Therefore the REF and SIG inputs are interchangeable. If swapping the I SIG and I REF pins, the Q SIG and Q REF also need to be swapped to maintain the correct phase. It is also possible to drive the SIG and REF inputs in a balanced mode. This will increase the gain. 5I R E F Reference voltage for the I mixer. This voltage should be the same as the DC voltage supplied to the I SIG pin. To obtain a carrier suppres- sion of better than 40dB it may be tuned ±0.15V (relative to the I SIG DC voltage). Without tuning, it will typically be better than 25dB.6Q R E F Reference voltage for the Q mixer. This voltage should be the same as the DC voltage supplied to the Q SIG pin. To obtain a carrier suppres- sion of better than 40dB it may be tuned ±0.15V (relative to the Q SIG DC voltage). Without tuning, it will typically be better than 25dB. The SIG and REF inputs are inputs of a differential amplifier. Therefore the REF and SIG inputs are interchangeable. If swapping the I SIG and I REF pins, Q SIG and Q REF also need to be swapped to maintain cor- rect phase. It is also possible to drive the SIG and REF inputs in a bal- anced mode. This will increase the gain. 7Q S I G Baseband input to the Q mixer. This pin is DC coupled. Maximum out- put power is obtained when the input signal has a peak to peak ampli- tude of 5V. The DC level supplied to this pin should be 2.5±0.5V. 8L O I N The input of the phase shifting network. This high impedance input can b em a t c h e dw i t ha ne x t e r n a l5 6Ω termination resistor. This pin is inter- nally connected to ground through a 4kΩ resistor. Putting a DC voltage on this pin is not recommended. However, connecting this pin to ground, e.g. through a shunt inductor, is allowed. 9 PHASE This pin adjusts the phase of the I/Q signals. However, the control is very sensitive and hard to control. Control voltage change for a few degrees adjustment is in the order of 10mV. Device to device and tem- perature variation are not characterized. Therefore it is not recom- mended to use this pin; leave it not connected. Do NOT connect it to ground. For compensating large errors in the I/Q signals supplied to the device or in control loops, this pin may prove useful. I SIG I REF Q REF Q SIG LO IN PHASE

Pin Function Description Interface Schematic 10 GND1 Ground connection of the LO phase shift network. This pin should be connected directly to the ground plane. 11 GND Ground connection for other circuits. Keep traces short and connect to ground plane immediately. 12 GND Same as pin 11. 13 GND2 Ground connection for the RF output stage. A good ground connection is especially important at this pin to avoid interference with other cir- cuits. 14 RF OUT 50Ω output. This pin carries a DC voltage, and an external blocking capacitor is recommended. RF OUT POWER CONTROL Σ 33 pF RF OUTPUT 33 pF 100 nF 100 nF 100 Ω 100 Ω 56 Ω 33 pF LO INPUT 100 Ω100 Ω 100 nF VDD POWER DOWN I INPUT Z IN=100 VREF I INPUT Z IN=100 CMOS 50 Ωµ strip 50 Ωµ strip +45° -45°

Evaluation Board Schematic (Download Bill of Materialsfrom www.rfmd.com.) POWER CONTROL Σ 100 pF 33 pF 100 nF Ω 100 pF 33 pF P1-3 P1-1 I SIG Q SIG RF OUT LO IN P1-1 P1-3 REF GND VDD1

2402400 Rev E

50 Ωµ strip 50 Ωµ strip 50 Ωµ strip 50 Ωµ strip +45° -45°

2.020” x 2.020”