RF2192_06 RFMD | Alldatasheet

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RF Micro Devices, Inc.

7628 Thorndike Road

Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com Optimum Technology Matching® Applied Si BJT GaAs MESFETGaAs HBT Si Bi-CMOS SiGe HBT Si CMOS InGaP/HBT GaN HEMT SiGe Bi-CMOS GND VCC1 VCC1 VCC BIAS 2F0 161 131415 GND GND RF IN 4VREG1 VMODE VREG2 BIAS GND GND 98765 RF OUT RF OUT RF OUT RF2192 3V 900MHz LINEAR POWER AMPLIFIER

  • 3V CDMA/AMPS Cellular Handsets
  • 3V JCDMA Cellular Handsets
  • 3V CDMA2000 Cellular Handsets
  • 3V TDMA/GAIT Cellular Handsets
  • 3V CDMA 450MHz Band Handsets
  • Portable Battery-Powered Equipment The RF2192 is a high-power, high-efficiency linear ampli- fier IC targeting 3V handheld systems. The device is manufactured on an advanc ed Gallium Arsenide Hetero- junction Bipolar Transistor (HBT) process, and has been designed for use as the final RF amplifier in dual-mode 3V CDMA/AMPS and CDMA2000 handheld digital cellu- lar equipment, spread-spectrum systems, and other applications in the 800MHz to 960MHz band. The RF2192 has a low power mode to extend battery life under low output power conditions. The device is pack- aged in a 16-pin, 4mmx4mm QFN.
  • Single 3V Supply
  • 29dBm Linear Output Power
  • 37% Linear Efficiency
  • Low Power Mode
  • 45 mA idle current
  • 47% Peak Efficiency 31dBm Output RF2192 3V 900MHz Linear Power Amplifier RF2192PCBA-41X Fully Assembled Evaluation Board Rev A8 060918 12° MAX 0.05 0.00 0.75 0.65 1.00 0.90 C 0.05 Dimensions in mm. Shaded pin is lead 1. A 4.00 2.00 1.50 SQ. 4.00 2.00 1.60

2 PLCS

0.10 C A

0.10 C ABM

3.20 0.75 0.50

0.10 C B

2 PLCS-B-

0.80 TYP 0.45 0.28 3.75 3.75 Package Style: QFN, 16-Pin, 4x4 RoHS Compliant & Pb-Free Product

Supply Voltage (RF off) +8.0 V DC Supply Voltage (POUT≤31dBm) +5.2 V DC Mode Voltage (VMODE)+ 4 . 2 V DC Control Voltage (VREG)+ 3 . 0 V DC Input RF Power +10 dBm Operating Case Temperature -30 to +110 °C Storage Temperature -40 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. Usable Frequency Range 400 960 MHz High Power State- US-CDMA (VMODE Low) Case T=25°C, V CC=3.4V , VREG= 2.85V , VMODE=0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) Frequency Range 824 849 MHz Linear Gain 27 30 dB Second Harmonic -33 dBc Third Harmonic <-60 dBc Maximum Linear Output Power (CDMA Modulation) 29 dBm Total Linear Efficiency 37 % P OUT=29dBm Adjacent Channel Power Rejec- tion -48 -44 dBc ACPR@885kHz -58 -56 dBc ACPR@1980kHz Input VSWR 2:1 Output VSWR 10:1 No damage. 6:1 No oscillations. >-70dBc Noise Power -133 dBm/Hz At 45MHz offset Low Power State- US-CDMA (VMODE High) Case T=25°C, V CC=3.4V , VREG=2.85V, VMODE=1.8V to 3V, Freq=824MHz to 849MHz (unless otherwise specified) Frequency Range 824 849 MHz Linear Gain 19 22 dB Second Harmonic -33 dBc Third Harmonic <-60 dBc Maximum Linear Output Power (CDMA Modulation) 16 20 dBm Max I CC 150 mA P OUT=+16dBm (all currents included) Adjacent Channel Power Rejec- tion -48 -46 dBc ACPR@885kHz <-60 -58 dBc ACPR@1980kHz Input VSWR 2:1 Output VSWR 10:1 No damage. 6:1 No oscillations. >-70dBc Caution! ESD sensitive device. RF Micro Devices believes the furnished information is correct and accurate at the time of this printing. RoHS marking based on EUDirective2002/95/EC (at time of this printing). However, RF Micro Devices reserves the right to make changes to its products without notice. RF Micro Devices does not assume responsibility for the use of the described product(s).

Parameter Specification Unit ConditionMin. Typ. Max. High Power State CDMA 2000 1x (VMODE LOW) Case T=25 oC, VCC=3.4V, VREG=2.85V. VMODE=0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) Frequency Range 824 849 MHz Linear Gain 29 dB Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) 26.5 dBm 2.5dB Backoff included in IS98D CCDF 1% 5.4dB Peak Average Ratio at CCDF 1% Adjacent Channel Power Rejec- tion -47 dBc ACPR@885kHz <-60 dBc ACPR@1.98MHz Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) 29 dBm 4.5dB Peak Average Ratio at CCDF 1% Adjacent Channel Power Rejec- tion -47 dBc ACPR@885kHz <-60 dBc ACPR@1.98MHz Low Power State CDMA 2000 1x (VMODE HIGH) Case T=25 oC, VCC=3.4V, VREG=2.85V. VMODE=1.8V to 3V, Freq=824MHz to 849MHz Frequency Range 824 849 MHz Linear Gain 22 dB Pilot+DCCH 9600 Maximum Linear Output Power (CDMA 2000 Modulation) 16 20 dBm 5.4dB Peak to Average Ratio at CCDF 1% Adjacent Channel Power Rejec- tion -48 dBc ACPR@885kHz <-85 dBc ACPR@1.98MHz Efficiency 15 % P OUT=20dBm Pilot+FCH 9600+SCHO 9600 Maximum Linear Output Power (CDMA 2000 Modulation) 16 20 dBm 4.5dB Peak to Average Ratio at CCDF 1% Adjacent Channel Power Rejec- tion <-50 dBc ACPR@885kHz <-65 dBc ACPR@1.98MHz FM Mode Case T=25°C, V CC=3.4V , VREG=2.85V, VMODE=0V to 0.5V, Freq=824MHz to 849MHz (unless otherwise specified) Frequency Range 824 849 MHz Gain 30 dB Second Harmonic -33 dBc Third Harmonic <-60 dBc Max CW Output Power 31 32 dBm Total Efficiency (AMPS mode) 47 % P OUT=31dBm (room temperature) Input VSWR 2:1 Output VSWR 10:1 No damage. 6:1 No oscillations. >-70dBc Note: DCCH: Dedicated Control Channel FCH: Fundamental Channel CCDF: Complementary Cumulative Distribution Function

Parameter Specification Unit ConditionMin. Typ. Max. High Power State- CDMA450 (VMODE Low) Case T=25 oC, VCC=3.4V, VREG=2.85V, VMODE=0V to 0.5V, Freq=452MHz to 458MHz (unless otherwise specified) Frequency Range 452 458 MHz Linear Gain 31 dB Second Harmonic 30 dBc Third Harmonic -60 dBc Maximum Linear Output Power (CDMA Modulation) 29 dBm Total Linear Efficiency 35 % P OUT=29dBm Adjacent Channel Power Rejec- tion -49 dBc ACPR @ 885kHz -56 dBc ACPR @ 1980kHz Input VSWR 2:1 Output VSWR 10:1 No damage. 6:1 No oscillations. > -70dBc Low Power State- CDMA450 (VMODE High) Case T=25 oC, VCC=3.4V, VREG=2.85V, VMODE=2.85V , Freq=452MHz to 458MHz (unless otherwise specified) Frequency Range 452 458 MHz Linear Gain 23 dB Maximum Linear Output Power (CDMA Modulation) 16 dBm Max I CC 160 mA P OUT=+16dBm (all currents included) Adjacent Channel Power Rejec- tion -52 dBc ACPR @ 885kHz -70 dBc ACPR @ 1980kHz Input VSWR 2:1 Output VSWR 10:1 No damage. 6:1 No oscillations. > -70dBc DC Supply Supply Voltage 3.0 3.4 4.2 V The maximum power out for V CC=3.0V is 28dBm. Quiescent Current 160 mA V MODE=Low 45 70 mA V MODE=High VREG Current 10 mA VMODE Current 1 mA Turn On/Off Time <40 μs Time between V REG turned on and PA reaching full power. Turn on/off time can be reduced by lowering the bypass capacitor value on the V REG line. Total Current (Power Down) 10 μAV REG=Low VREG “Low” Voltage 0 0.5 V VREG “High” Voltage 2.75 2.85 2.95 V VMODE “Low” Voltage 0 0.5 V VMODE “High” Voltage 1.8 2.85 3.0 V

Note: This schematic is a preliminary schematic. This 450MHz band CDMA tune is done by modifying the existing 800MHz band CDMA evaluation board. Pin Function Description Interface Schematic 1G N D Ground connection. 2G N D Ground connection. 3G N D Ground connection. 4R F I N RF input. An external 100pF series capacitor is required as a DC block. In addition, shunt inductor and series capacitor are required to provide 2:1VSWR. 5V R E G 1 Power Down control for first stage. Regulated voltage supply for ampli- fier bias. In Power Down mode, both V REG and VMODE need to be LOW (<0.5V). 6V M O D E For nominal operation (High Power Mode), VMODE is set LOW. When set HIGH, the driver and final stage are dynamically scaled to reduce the device size and as a result to reduce the idle current. 7V R E G 2 Power Down control for the second stage. Regulated voltage supply for amplifier bias. In Power Down mode, both V REG and VMODE need to be LOW (<0.5V). 8B I A S G N D Bias circuitry ground. See application schematic. 9G N D Ground connection. 10 RF OUT RF output and power supply for final stage. This is the unmatched col- lector output of the second stage. A DC block is required following the matching components. The biasing may be provided via a parallel L-C set for resonance at the operating frequency of 824MHz to 849MHz. It is important to select an inductor with very low DC resistance with a 1A current rating. Alternatively, shunt microstrip techniques are also appli- cable and provide very low DC resistance. Low frequency bypassing is required for stability. 11 RF OUT Same as pin 10. See pin 10. 12 RF OUT Same as pin 10. 13 2FO Harmonic trap. This pin connects to the RF output but is used for pro- viding a low impedance to the second harmonic of the operating fre- quency. An inductor or transmission line resonating with an on chip capacitor at 2fo is required at this pin. 14 VCC BIAS Power supply for bias circuitry. A 100pF high frequency bypass capaci- tor is recommended. 15 VCC1 Power supply for first stage. 16 VCC1 Same as Pin 15. Pkg Base GND Ground connection. The backside of the package should be soldered to a top side ground pad which is connected to the ground plane with mul- tiple vias. The pad should have a short thermal path to the ground plane. GND1 RF IN VCC1 From Bias Stages 100 pF RF OUT From Bias Stages

Evaluation Board Schematic US-CDMA (Download Bill of Materials from www.rfmd.com.) C25 4.7 μF C30 100 pF 100 pF C27 100 pF 0 Ω C13 100 pF C1 C14 100 pF L1* 100 pF C28 10 nF 4.7 uF C17 2.4 pF 0 Ω TL1 TL2 C26 4.7 μF * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). **C1 and C14 are High Q capacitors (i.e., Johanson C-series). 161 131415 98765 39 nH 0 Ω 5.6 nH RF IN VCC 1 nH RF OUT VREG VMODE TL5 C24 12 pF TL3 Transmission Line Length CDMA (US) TL1 15 mils TL2 350 mils TL3 105 mils TL5 85 mils CDMA (US) 100 9.1 20 9.1 Board C30 (pF) C1 (pF) L1 (nH) C14 (pF) 510 Ω 100 pF

4.7 μF 470 pF 100 pF 100 pF 100 pF 0 Ω 100 pF C1 C100 C3 100 pF L1* 100 pF 10 nF 4.7 uF 7.5 pF 0 Ω TL1 TL2 4.7 μF * L1 is a High Q inductor (i.e., Coilcraft 0805HQ-series). C1, C100, C14, and C140 are High Q capacitors (i.e., Johanson C-series). 161 131415 98765 39 nH 0 Ω 12 nH P1-1 6.8 nH P2-1 P2-2 TL5 27 pF TL4 Transmission Line Length TL1 15 mils TL2 125 mils TL6 220 mils TL4 L=40 mils 100 pF RF IN 510 Ω 6.8 nH 1.2 nH TL6 C140 C14** RF OUT CDMA (450 MHz) 15 13 15 20 Board C100 (pF) C140 (pF) C1 (pF) L1 (nH) C14 (pF) TL5 L=75 mils

Evaluation Board Layout - US-CDMA 2.0” x 2.0” Board Thickness 0.031”, Board Material FR-4, Multi-Layer, Ground Plane at 0.015”

3μinch to 8μinch gold over 180μinch nickel. assembly processes. The PCB land pattern has been developed to accommodate lead and package tolerances. Figure 1. PCB Metal Land Pattern (Top View)

can be provided in the master data or requested from the PCB fabrication supplier. that the quantity of vias be increased by a 4:1 ratio to achieve similar results. Figure 2. PCB Solder Mask (Top View)