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Technical content
Features
Fractional-N Synthesizer Very Fine Frequency Resolution 1.5Hz for 26MHz Reference LO Frequency Range 940MHz to 1000MHz Low Phase Noise VCO Integrated LO Buffers Two Wideband RF Mixers Mixer Frequency Range 30MHz to 2500MHz Mixer Input IP3 +12dBm Mixer Bias Adjustable for Low Power Operation 2.1V to 2.3V Power Supply Low Current Consumption 45mA typ. at 2.2V 3-Wire Serial Interface
Applications
Band Shifters Super-Heterodyne Radios Diversity Receivers Wireless Telemetry DS120320 Package: QFN, 32-Pin, 5mm x 5mm RF2054Low Power PLL and VCO with Inte- grated Mixers
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support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Absolute Maximum Ratings Parameter Rating Unit Supply Voltage (VDD) -0.5 to +3.6 V Input Voltage (VIN), any Pin -0.3 to V DD +0.3 V RF/IF Mixer Input Power +15 dBm Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. ESD Requirements Human Body Model General 2000 V RF Pins 1000 V Machine Model General 200 V RF Pins 100 V Operating Conditions Supply Voltage (VDD)2 . 1 2 . 2 2 . 3 V Temperature (TOP) -20 +75 °C Logic Inputs/Outputs VDD = Supply to DIG_VDD pin Input Low Voltage -0.3 +0.5 V Input High Voltage 1.5 V DD V Input Low Current -10 +10 uA Input = 0V Input High Current -10 +10 uA Input = V DD Output Low Voltage 0 0.2 * V DD V Output High Voltage 0.8 * V DD VDD V Load Resistance 10 k Load Capacitance 20 pF Static VDD = +2.2V, MIX_IDD = 001 Supply Current (IDD) O n e M i x e r E n a b l e d 4 24 54 8 m A F U L L D = 0 Both Mixers Enabled 57 mA FULLD = 1 Standby 3 mA Reference oscillator and bandgap only. Power Down Current 140 A ENBL = 0 and REF_STBY = 0 Mixer Mixer output driving 4:1 balun, MIX_IDD = 001 Gain (DUT Only) -6 -3.5 -2 dB Not including balun losses. Gain -6.5 dB Including balun losses, 1GHz to 2GHz conver- sion. Noise Figure 11 dB IIP3 +12 dBm Pin1dB +1 dBm RF and IF Port Frequency Range 30 2500 MHz Mixer Input Return Loss 10 dB 100 differential Caution! ESD sensitive device. Exceeding any one or a combination of the Absolute Maximum Rating conditions may cause permanent damage to the device. Extended application of Absolute Maximum Rating conditions to the device may reduce device reliability. Specified typical perfor- mance or functional operation of the device under Absolute Maximum Rating condi- tions is not implied. The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices, Inc. ("RFMD") for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RFMD. RFMD reserves the right to change component circuitry, recommended appli- cation circuitry and specifications at any time without prior notice. RFMD Green: RoHS compliant per EU Directive 2002/95/EC, halogen free per IEC 61249-2-21, < 1000ppm each of antimony trioxide in polymeric materials and red phosphorus as a flame retardant, and <2% antimony in solder.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Parameter Specification Unit ConditionMin. Typ. Max. Voltage Controlled Oscillator 3.3nH (*2) VCO Inductor VCO Frequency Range 900 1150 MHz Open Loop Phase-Noise at 1MHz Offset 960MHz LO Frequency -134 dBc/Hz VCO Tuning Gain 960MHz LO Frequency 15 MHz/V Reference Oscillator External Reference Frequency 10 21 26 MHz Reference Divider Ratio 1 7 External Reference Input Level 500 800 1200 mV P-P AC-coupled Local Oscillator 3.3nH (*2) VCO Inductor Synthesizer Output Frequency 940 1000 MHz Phase Detector Frequency 26 MHz Closed Loop Phase-Noise at 960MHz LO 21MHz phase detector frequency 10kHz Offset -90 dBc/Hz 100kHz Offset -100 dBc/Hz 1MHz Offset -130 dBc/Hz
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Detailed Functional Block Diagram Pin Out Serial Data Interface, Control and Biasing Analog Regulator Digital Regulator Mux LO Divider 1 /1, /2, or /4 LO Divider 2 /1, /2, or /4 LO Buffer 1 LO Buffer 2 Mixer 1 Mixer 2 Voltage Controlled Oscillator Reference Divider /1 to /7 Reference Oscillator Circuitry - + Vref N Divider Phase / Freq Detector Frac-N Sequence Generator Charge Pump Synthesizer Vtune ANA_VDD DIG_VDD ANA_DEC LFILT1 LFILT2 LFILT3 REXT XTALIPP XTALIPN ENX ENBL MODE RESETB SDATA SCLK RFOP1N RFOP1P RFIP1N RFIP1P RFIP2P RFIP2N RFOP2P RFOP2N SERIAL BUS CONTROL ANA_VDD OP1 4:1 ANA_VDD OP2 4:1 1:1 IP2 1:1 IP1 INDN INDP REFERENCE CLOCK ENBL INDP INDN REXT ANA_DEC LFILT1 LFILT2 8LFILT3 2527 2630 29 2831 NC NC RFOP2N RFOP2P RESETB ENX SCLK
32 SDATA
ANA_VDD NC NC DIG_VDD RFOP1P
17 RFOP1N
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Note 1: The signal should be connected to this pin such that DC current cannot flow into or out of the chip, either by using AC coupling capacitors or by use of a transformer (see evaluation board schematic). Note 2: DC current needs to flow from ANA_VDD into this pin, either through an RF inductor , or transformer (see evaluation board schematic). Note 3: Alternatively an external reference can be AC-coupled to pin 11 XTALIPN, and pin 10 XTALIPP decoupled to ground. This may make PCB routing simpler. Pin Names and Descriptions Pin Name Description 1E N B L Ensure that the ENBL high voltage level is not greater than VDD. An RC low-pass filter could be used to reduce digital noise. 2I N D P VCO 3 differential inductor. Connect to ground for DC bias. 3I N D N VCO 3 differential inductor. Connect to ground for DC bias. 4R E X T External bandgap bias resistor. Connect a 51k resistor from this pin to ground to set the bandgap reference bias current. This could be a sensitive low frequency noise injection point. 5A N A _ D E C Analog supply decoupling capacitor. Connect to analog supply and decouple as close to the pin as possible. 6L F I L T 1 Phase detector output. Low-frequency noise-sensitive node. 7L F I L T 2 Loop filter op-amp output. Low-frequency noise-sensitive node. 8L F I L T 3 VCO control input. Low-frequency noise-sensitive node. 9M O D E Mode select pin. An RC low-pass filter can be used to reduce digital noise. 10 XTALIPP Reference oscillator input. Should be AC-coupled if an external reference is used. See note 3. 11 XTALIPN Reference oscillator input. Should be AC-coupled to ground if an external reference is used. See note 3. 12 GND Connect to ground. 13 RFIP1P Differential input 1. See note 1. 14 RFIP1N Differential input 1. See note 1. 15 NC 16 NC 17 RFOP1N Differential output 1. See note 2. 18 RFOP1P Differential output 1. See note 2. 19 DIG_VDD Digital supply. Should be decoupled as close to the pin as possible. 20 NC 21 NC 22 ANA_VDD Analog supply. Should be decoupled as close to the pin as possible. 23 RFIP2N Differential input 2. See note 1. 24 RFIP2P Differential input 2. See note 1. 25 NC 26 NC
27 RFOP2N
Differential output 2. See note 2. 28 RFOP2P Differential output 2. See note 2. 29 RESETB Chip reset (active low). Connect to DIG_VDD if external reset is not required. 30 ENX Serial interface select (active low). An RC low-pass filter could be used to reduce digital noise. 31 SCLK Serial interface clock. An RC low-pass filter could be used to reduce digital noise. 32 SDATA Serial interface data. An RC low-pass filter could be used to reduce digital noise. EP Exposed pad Connect to ground. This is the ground reference for the circuit. All decoupling should be connected here through low impedance paths.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Typical Performance Characteristics: PLL and VCO VDD = +2.2V, TA = +25°C unless stated, as measured on RF2054 evaluation board. See schematic page 36. -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 Phase Noise (dBc/Hz) Offset Frequency (kHz) Synthesizer Phase Noise versus Frequency 21MHz Reference and +2.2V Supply 940MHz 960MHz 980MHz 1000MHz -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 Phase Noise (dBc/Hz) Offset Frequency (kHz) Synthesizer Phase Noise versus Temperature LO = 960MHz, 21MHz Reference and +2.2V Supply -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 Phase Noise (dBc/Hz) Offset Frequency (kHz) VCO Phase Noise versus Frequency +2.2V Supply 940MHz 960MHz 980MHz 1000MHz -160.0 -140.0 -120.0 -100.0 -80.0 -60.0 -40.0 -20.0 Phase Noise (dBc/Hz) Offset Frequency (kHz) VCO Phase Noise versus Temperature VCO Frequency 960MHz, +2.2V Supply -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C 0.0 25.0 50.0 75.0 100.0 125.0 800 900 1000 1100 1200 1300 Coarse Tuning Word (CT_CAL) VCO Frequency (MHz) VCO Coarse Tuning versus Frequency 3.3nH VCO Inductors and +2.2V Supply -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C 940 945 950 955 960 965 970 VCO Frequency (MHz) Tuning Voltage (Volts) VCO Frequency versus Tuning Voltage and Temperature For the Same Coarse Tune Setting, +2.2V Supply -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Typical Performance Characteristics: RF Mixer 1, Downconversion VDD = +2.2V, TA = +25°C, unless stated, as measured on RF2054 evaluation board. See schematic page 36. 40.0 41.0 42.0 43.0 44.0 45.0 46.0 47.0 48.0 Current (mA) Supply Voltage Total Supply Current versus Temp and Voltage Mixer 1 Enabled, LO Frequency = 960MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 Conversion Gain (dB) Supply Voltage Mixer 1 Conversion Gain versus Temp and Voltage RF Input = 2000MHz, IF Output = 1040MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 1970 1980 1990 2000 2010 2020 2030 Pin 1dB (dBm) Input IP3 (dBm) RF Input Frequency (MHz) Mixer 1 Linearity versus Voltage Downconversion, IF Output = 1040MHz IIP3, +2.1V IIP3, +2.2V IIP3, +2.3V Pin 1dB, +2.1V Pin 1dB, +2.2V Pin 1dB, +2.3V 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 Input IP3 (dBm) Supply Voltage Mixer 1 Input IP3 versus Temp and Voltage RF Input = 2000MHz, IF Output = 1040MHz -20° C 0° C +25° C +50° C +75° C -60.0 -58.0 -56.0 -54.0 -52.0 -50.0 -48.0 -46.0 -44.0 -42.0 -40.0 LO Leakage (dBm) Supply Voltage Mixer 1 LO Leakage versus Temp and Voltage LO Frequency 960MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 Noise Figure (dB) Supply Voltage Mixer 1 Noise Figure versus Temp and Voltage RF Input = 2000MHz, IF Output = 1040MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Typical Performance Characteristics: RF Mixer 2, Upconversion VDD = +2.2V, TA = +25°C unless stated, as measured on RF2054 evaluation board. See schematic page 36. 40.0 41.0 42.0 43.0 44.0 45.0 46.0 47.0 48.0 Current (mA) Supply Voltage Total Supply Current versus Temp and Voltage Mixer 2 Enabled, LO Frequency = 960MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 Input IP3 (dBm) Supply Voltage Mixer 2 Input IP3 versus Temp and Voltage IF input = 1040MHz, RF Output = 2000MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 Conversion Gain (dB) Supply Voltage Mixer 2 Conversion Gain versus Temp and Voltage IF Input = 1040MHz, RF Output = 2000MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 -2.0 0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 1970 1980 1990 2000 2010 2020 2030 Pin 1dB (dBm) Input IP3 (dBm) RF Input Frequency (MHz) Mixer 2 Linearity versus Voltage Upconversion, IF Input = 1040MHz IIP3, +2.1V IIP3, +2.2V IIP3, +2.3V Pin 1dB, +2.1V Pin 1dB, +2.2V Pin 1dB, +2.3V 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 Noise Figure (dB) Supply Voltage Mixer 2 Noise Figure versus Temp and Voltage IF Input = 1040MHz, RF Output = 2000MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -60.0 -58.0 -56.0 -54.0 -52.0 -50.0 -48.0 -46.0 -44.0 -42.0 -40.0 LO Leakage (dBm) Supply Voltage Mixer 2 LO Leakage versus Temp and Voltage LO Frequency 960MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Typical Performance Characteristics: RF Mixers VDD = +2.2V, TA = +25°C unless stated, as measured on RF2054 evaluation board. See schematic page 36. 50.0 51.0 52.0 53.0 54.0 55.0 56.0 57.0 58.0 59.0 60.0 Current (mA) Supply Voltage Total Supply Current versus Temp and Voltage Full Duplex Mode, LO Frequency = 960MHz -20/g131C 0/g131C +25/g131C +50/g131C +75/g131C -10.0 -9.0 -8.0 -7.0 -6.0 -5.0 -4.0 -3.0 -2.0 880 900 920 940 960 980 1000 Conversion Gain (dB) LO Frequency (MHz) Typical Mixer Conversion Gain +25°C and +2.2V Supply, RF = IF + LO Mixer 1, RF in = 2000MHz Mixer 2, IF in = 1050MHz -60.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 880 900 920 940 960 980 1000 LO Leakage (dBm) LO Frequency (MHz) Typical LO Leakage at Mixer Output +25°C and +2.2V Supply Mixer 1 Mixer 2
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Detailed Description The RF2054 is a frequency converter chip that includes a fracti onal-N phase locked loop, a low noise VCO core, an LO signal multiplexer, two LO buffer circuits, and two RF mixers. Sy nthesizer programming, device configuration, and control are achieved through a mixture of hardware and software controls . All on-chip registers are programmed through a simple three- wire serial interface. VCO The VCO core in the RF2054 consists of one VCO which covers a frequency range dependant on the value of the external inductor used. The RF2054 has been characterized with 3.3nH inductors, so the VCO covers from 940MHz to 1000MHz. Note that the VCO inductor is differential so the value given is the inductance on each device pin, and the total differential induc - tance will be twice this value. VCO3 must be selected using the PLL1x0:P1_VCOSEL and PLL2x0:P2_VCOSEL control word and setting 10 for VCO3. The VCO has 128 overlapping bands to achieve an acceptable VCO gain (MHz/V) and hence a good phase noise performance across the whole tuning range. The chip automatic ally selects the correct VCO band (VCO coarse tuning) to generate the desired fre- quency based on the values programmed into the PLL1 and P LL2 register banks. For information on how to program the desired LO frequency into the PLL1 and PLL2 banks, refer to the next section. The automatic VCO band selection is triggered every time the ENBL pin is taken high. Once the band has been selected, the PLL will lock onto the correct frequency. During the band selection process, fixed capacitance elements are prog ressively connected to the VCO resonant circuit until the VCO is oscillating at approximately the correct frequency. The output of this band selection is made available in the RB1:CT_CAL read-back register. A value of 127 or 0 in this register indica tes that the selection was unsuccessful; this is usually due to the wrong VCO being selected so the user is trying to program a frequency that is outside of th e VCO operating range. A value between one and 126 indicates a successful calibration, the actu al value being dependent on the desired frequency, as well as process variation. The band selection takes approximately 25 s with a 21MHz clock. The band select process will center the VCO tuning voltage at about 1.0V, compensating for manufact uring tolerances and process variation, as well as environ- mental factors, including temperature. For applications where th e synthesizer is always on and the LO frequency is fixed, the synthesizer will maintain lock over the whole temperature range of -20°C to +75°C. However, it is recommended to re-initiate an automatic band selection for every 30 degrees of temperature change in order to maintain optimal synthesizer perfor- mance. This assumes an active loop filter. If start-up time is a critical parameter and the user is always programming the same frequency for the PLL, the calibration result may be read back from the RB1:CT_CAL register and written to PLL1x2:P1_CT_DEF or PLL2x2:P2_CT_DEF registers (depending on the desired PLL re gister bank). The calibration function must then be disabled by setting the PLL1x0:P1_CT_EN and/or PLL2x0:P2_CT_EN control words to 0. For further information, please refer to the RF205x Calibration User Guide. The LO divide ratio is set by the PLL1x0:P1_LODIV and PLL2x0:P2_LODIV control words. The LO is routed to mixer1, mixer2, or both, depending on the state of the MODE pin and the value of CFG1:FULLD.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. VCO External Inductor Selection The RF2054 VCO resonator circuit can be simplified to the schematic shown below: The following equation can be used to calculate the VCO frequency range: where C is the total differential capacitance C1, 2.5pF to 5.5pF, and L is the total differential inductance: L = L3 + L4 + 1nH = 7.6nH For L3 and L4 of 3.3nH, this equation gives total VCO frequency range of about 800MHz to 1150MHz. Some margin must be left at the top and bottom of the VCO frequency range to allow for process, assembly and environmental variations. A CT_CAL margin of 25 bits is recommended at both the top and bottom, about 0.6pF of capacitance. The VCO resonator will have the highest Q and lowest phase noise at the lower end of the coarse tuning curve. For applications where the LO frequency is fixed, or only tunes over a few MHz, it is recommended to design for CT_CAL of about 40 using C1 = 4.7pF. C1 Variable (coarse tune) capacitance plus varactor and stray capacitance. L1 and L2 Bondwire inductance of 0.5nH on each pin. L3 and L4 External inductors that form a differential inductor and provide a DC ground path to bias VCO. L5 Inductance of ground via (not part of differential inductor). 0.5nH 0.5nH 2.5pF to 5.5pF RF2054 VCO CORE Pin 2 INDP Pin 3 INDN 3.3nH 3.3nH Fo 1 2 LC
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Fractional-N PLL The RF2054 contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the VCO. The PLL includes automatic calibration systems to counteract the effects of pr ocess and environmental variatio ns, ensuring repeatable lock time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 26MHz. The reference path features a divider, but typically for best phase noise this is bypassed. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remaining three bits CLK DIV <15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled. Two PLL programming banks are provided, the first bank is prec eded by the label PLL1, and the second bank is preceded by the label PLL2. For the RF2054, these banks are used to program mixer 1 and mixer 2 respectively, and are selected automat- ically as the mixer is selected (using the MODE pin). The PLL will lock the VCO to the frequency FVCO according to: FVCO = NEFF*FOSC/R where NEFF is the programmed fractional-N divider value, F OSC is the reference input frequency, and R is the programmed R divider value (1 to 7). The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows: First determine the desired, effective N divider value, NEFF: NEFF = FVCO*R/FOSC N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224 = 16777216. Example: VCO3 operating at 960MHz, 21MHz reference frequency, the desired effective divider value is: NEFF = FVCO *R / FOSC = 960 *1 / 21 = 45.714285714285. The N value is set to 45, equal to the integer part of N EFF, and the NUM value is set to the fractional portion of N EFF multiplied by 224: NUM = 0.714285714285 * 224 = 11983726. Converting N and NUM into binary results in the following: N = 0001 0110 1 NUM = 1011 0110 1101 1011 0110 1110 So the registers would be programmed: P1_N (or P2_N) = 0001 0110 1 P1_NUM_MSB (or P2_NUM_MSB) = 1011 0110 1101 1011 P1_NUM_LSB (or P2_NUM_LSB) = 0110 1110 The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL Lock Detect The lock detect function is a window detector, indicating an out of lock condition when the VCO tuning voltage is outside of a certain voltage range. When out of lock then the LOCK bit will be high, bit 1 in the read back register RB1. It is possible th at when an out of lock is indicated the PLL is still locked, but the tuning voltage has drifted outside of the window. There are two windows for the lock detector set by LD_LEV, bit 14 in register CFG1. The following are the typical tuning voltage ranges for the lock detect circuit measured with +2.2V supply voltage to the RF2054: LD_LEV = 0: 0.55V to 1.55V (narrow window) LD_LEV = 1: 0.35V to 1.75V (wide window) Phase Detector and Charge Pump The chip provides a current output to drive an external loop fi lter. An on-chip operational amplifier can be used to design an active loop filter or a passive design can be implemented. Th e maximum charge pump output current is set by the value con- tained in the P1_CP_DEF/P2_CP_DEF field and CP_LO_I. In the default state (P1_CP_DEF/P2_CP_DEF = 31 and CP_LO_I = 0) the charge pump current (ICPset) is 120A. If CP_LO_I is set to 1 this current is reduced to 30A. The charge pump current can be altered by changing the value of P1_CP_DEF/P2_CP_DEF. The charge pump current is defined as: ICP= ICPset*CP_DEF / 31 If automatic loop bandwidth correction is enabled the charge pump current is set by the calibration algorithm based upon the VCO gain. For more information on the VCO gain calibration, whic h is disabled by default, please refer to the RF205x Calibra- tion User Guide. The phase detector will operate with a maximum input frequency of 26MHz. Loop Filter The PLL may be designed to use an active or a passive loop filt er as required. The internal configuration of the chip is shown below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF205x Programming Tool software can assist with loop filter designs. Because the op-amp is used in an in verting configuration in active mode, when the passive loop filter mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP = 1, for passive mode, CFG1:PDP = 0. LFILT1 LFILT2 LFILT3 To VCO Tuning LF_ACT=TRUE+1.1V
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. The charge pump output voltage compliance range is typically +0. 7V to +1.5V. For applications using a passive loop filter VCO coarse tuning must be performed regularly enough to ensure that the VCO tuning voltage falls within this compliance range at all temperatures. The active loop filter maintains the charge pu mp output voltage in the center of the compliance range, and the op-amp provides a wider VCO tuning voltage range, typical 0V to +2.1V. Reference Input The RF2054 requires an external reference source. The external source (such as a TCXO) should be AC-coupled into one of the XO inputs, and the other input should be AC-coupled to ground. The bias circuits in the reference path (XO) take approximately 200sec to settle, and so for applications requiring rapid pulsed operation of the PLL (such as a TDMA system, or Rx/Tx half-dup lex system) it is necessary to keep the XO running between bursts. However, when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY register is provided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even when ENBL is asserted low. Thus the XO will be stable and a clock is immediately available when ENBL is asserted high, allow- ing the chip to assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period before it can provide a stable clock. It is recommended to program REFSTBY high at least 200 users before asserting ENBL high. Wideband Mixer The RF2054 includes two wideband, double-balanced Gilbert cell mixers. Each mixer has an input port and an output port that can be used for either IF or RF , i.e. for up conversion or down conversion. The mixer current can be programmed to between 5mA and 25mA in 5mA steps depending on linearity requirem ents, using the MIX1_IDD<3:0> word for mixer 1 and the MIX2_IDD<3:0> word for mixer 2, both of which are in the CFG2 register. The majority of the mixer current is sourced through the output pins via either a centre-tapped balun or an RF chok e in the external matching circuitry to the supply. The RF2054 has been characterized for lowest current operation, so MIX1 _IDD and MIX2_IDD set to 001. Mixer 1 of the RF2054 has been characterized for down conversion from approximately 2 GHz input to 1040MHz IF output. Mixer 2 of the RF2054 has been characterized for upconversion from IF input of 1040MHz to approximately 2GHz output. The RF mixer input and output ports are differential and require simple matching circuits optimized to the specific application frequencies. A conversion gain of approximately -3dB is achieved with 100 differential input impedance, and the outputs driving 200 differential load impedance. Increasing the mixer output load increases the conversion gain. The mixer has a broadband common gate input. The input impeda nce is dominated by the resistance set by the mixer 1/gm term, which is inversely proportional to the mixer curre nt setting. The resistance will be approximately 135 at the mixer low current setting (001). There is also some shunt capacitance at the mixer input. The mixer output is high impedance, consisting of a resistance of approximately 2k in parallel with some capacitance. The mixer output does not need to be matched as such, just to see a resistive load. A higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the im pedance of the output capacitance is less significant. For the RF2054 mixer 1 IF output a 33nH inductor is used (1040MHz) and for the mixer 2 RF output a 8.2nH inductor is used (2GHz). For more information about the mixer port impedances and matc hing, please refer to the RF205x Family Application Note on Matching Circuits and Baluns.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. The mixer layout and pin placement has been optimized for high mixer-to-mixer isolation of over 60dB. The mixers can be set up to operate in half-duplex mode (1 mixer active) or full dupl ex mode (both mixers active). The mode selection is done via hardware control of the MODE pin and by setting the FULLD bit in the CFG1 register as shown in the table below. When in full- duplex mode, one can either use PLL register bank 1 or 2, the LO signal is routed to both mixers. Mode Pin FULLD Bit Active PLL Register Bank Active Mixer Low 0 1 1 High 0 2 2 Low 1 1 Both High 1 2 Both
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. General Programming Information Serial Interface All on-chip registers in the RF2054 are programmed using a 3-wire serial bus which supports both write and read operations. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETB pins in addition to programming via the serial bus. Serial Data Timing Characteristics Parameter Description Time t1 Reset delay >5ns t2 Programming setup time >5ns t3 Programming hold time >5ns t4 ENX setup time >5ns t5 ENX hold time >5ns t6 Data setup time >5ns t7 Data hold time >5ns t8 ENBL setup time >0ns t9 ENBL hold time >0ns MCU ENX SCLK SDATA ENBL RESETB MODE 3‐wire bus Hardware Controls RF2054 RESETB ENX SCLK SDATA ENBL X Reset chip Initial programming of device Programming updates Serial bus X XX X X X X t8t6 t7 t9
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Write Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall- ing edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will drive SDATA for the entire telegram. RF2054 will read the data bit on the rising edge of SCLK. The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mod e transfer of 24 bits. Data is latched into RF2054 on the last rising edge of SCLK (after ENX is asserted high). For more information, please refer to the timing diagram on page 16. The maximum clock speed for a register write is 19.2MHz. A register write therefore takes approximately 1.3 s. The data is latched on the rising edge of the clock. The datagram consists of a single start bit followed by a ‘0’ (to indicate a write opera- tion). This is then followed by a seven bit address and a sixteen bit data word. Note that since the serial bus does not require the presence of the reference clock, it is necessary to insert an additional rising clock edge before the ENX line is set low to ensure the address/data are read correctly. Read Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele- gram, and then control will be ha nded over to RF2054 for the data portion. RF2054 will read the data bits of the address on the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2054. One and a half clocks are reserved for turn-around, and then the data bits are presented by RF2054. The data is set up on the rising edge of SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2054 will release control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2054 transitions from high impedance to low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address bit has been read), so the controller chip should be presenting a high impedance by that time. For more information, please refer to the timing diagram on page 16. The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4s. The address is latched on the rising edge of the clock an d the data output on the falling edge. The datagram consists of a single start bit fo l- A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENX SCLK SDATA XA 6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENX SCLK SDATA XA 6 A5
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit data word representing the register content is presented to the receiver. Note that since the serial bus does not require the presence of the reference clock, it is necessary to insert an additional rising clock edge before the ENX line is set low to ensure the address is read correctly. Hardware Control Three hardware control pins are provided: ENBL, MODE, and RESETB. ENBL Pin The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in the VCO section on page 10. As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre- quency. The band selection is initiated when the ENBL pin is ta ken high. Every time the frequency of the synthesizer is re-pro- grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune). RESETB Pin The RESETB pin is a hardware reset control that will reset all digital circuits to their start-up state when asserted low. The device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the positive supply. MODE Pin The MODE pin controls which mixer(s) an d PLL programming register bank is acti ve. See the PLL and Mixer description sec- tions for details. ENBL Pin REFSTBY Bit XO and Bias Block Analogue Bloc k Digital Block Low 0 Off Off On Low 1 On Off On H i g h0 O nO nO n H i g h1 O nO nO n Parameter Description Time t1 MODE setup time >5ns t2 MODE hold time >5ns ENBL MODE
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Programming the RF2054 The figure below shows an overview of the device programming. Note: The set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below. Additional information on device use and programming can be found on the RF205X family page of the RFMD web site (http://www.rfmd.com/rf205x). The following documents may be particularly helpful:
- RF205x Frequency Synthesizer User Guide
- RF205x Calibration User Guide Device off Set-up device operation Set operating frequencies Set calibration mode ENABLE device Apply power Reset device Apply power to the device. Ensure the device is set into a known and correct state. To use the device it will be necessary to program the registers with the desired contents to achieve the required operating characteristics. See following sections for details. When programming is complete the device can be enabled.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Start-up When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high at least 200s before ENBL is taken high. This is to allow the XO bias circuits to settle. The various calibration routines will also take some time depending on whether they are enabled or not. Coar se tuning calibration takes about 50 s and VCO tuning gain compensation takes about 100s. Additionally, time for the PLL to settle will be required. Al l of these timings will be dependant upon application specific factors such as loop filter bandwidth, reference clock frequency, and so on. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration rout ines, minimizing all calibration times, and setting the PLL loo p bandwidth as wide as possible. The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting the RESETB pin low for at least 100ns. Setting Up Device Operation The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is achieved as follows. Three registers need to be written, taking 3.9s at the maximum clock speed. If the device is used with an active filter in sim- plex operation it will not be necessary to program CFG1 reducing the programming time to 2.6s. Set-up device operation Disable active loop filter? Default Yes LF_ACT Set to 0 Program MIX1_IDD and MIX2_IDD Set-up complete Program XO_CT, XO_CR_S and CLK_DIV Internal capacitors used to set Xtal load Mixer linearity Full duplex operation? Default Yes FULLD Set to 1 When setting up the device it is necessary to decide if an active or passive loop filter will be used in the phase locked loop. The LF_ACT bit is located in the CFG1 register and is active by default. Set the phase detector polarity bit in CFG1since the active filter inverts the loop filter voltage. The user must then activate the full duplex mode of operation if fast frequency switching is required or it is necessary to have both mixers operating simultaneously. This bit is also located in the CFG1 register and is inactive by default. The mixer linearity setting is then selected. The default value is 4 with 1 being the lowest setting and 5 the highest. The MIX1_IDD and MIX2_IDD bits are located in the CFG2 register. The internal crystal loading capacitors are also programmed to present the correct load to the crystal. The capacitance internal to the chip can be varied from 8-16pF in 0.25pF steps (default=10pF). The reference divider must also be set to determine the phase detector frequency (default=1). These bits are located in the CFG4 register.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Setting Up VCO Coarse Tuning and Loop Filter Calibration If the user wishes to disable the VCO coarse tune calibration or enable the loop filter calibration then the following program- ming operation will need to take place. Two registers need to be written taking 2.6s at maximum clock speed if the course tuning is deactivated or the loop filter cal- ibration activated. Since it is necessary to program these registers when setting the operating frequency (see next section) this operation usually carries no overhead. The coarse tune calibration takes approximately 26s when using a 21MHz reference clock (it will take proportionally longer if a slower clock is used, and vice versa). This follows a VCO warm-up period also dependent on the reference clock, typically 10s to 15s. Disable VCO coarse tune? Default Yes P1_CT_EN, P2_CT_EN Set to 00 Set calibration mode Operating mode set Enable loop filter cal? Default Yes Loop filter calibration When setting up the device it is necessary to decide whether to deactivate the devices' internal VCO calibration or provide the calibration information directly. These bits are located in the PLL1x0 and PLL2x0 registers and are active by default. It is also necessary to decide whether to activate the loop filter calibration mode, only necessary when operating the device over very wide band of frequencies. These bits are also located in the PLL1x0 and PLL2x0 registers. The default setting assumes an active loop filter is used.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Setting The Operating Frequency Setting the operating frequency of the device requires a number of registers to be programmed. A total of five registers must be programmed to set the device operating frequency for each path within the device. This will take 6.5s for each path at maximum clock speed. To change the frequency of the VCO it will be necessary to repeat these operations. However, it may not be necessary to repro- gram the LODIV bits reducing the register writes to three per path. For an example on how to determine the integer and fractional pa rts of the synthesizer PLL division ratio please refer to the detailed description of the PLL. Set operating frequencies Program P1_VCOSEL, P2_VCOSEL, P1_LODIV, P2_LODIV, and FLL Fact Program P1_N, P2_N Program P1_NUM_MSB, P2_NUM_MSB Program P1_NUM_LSB, P2_NUM_LSB, P1_CT_DEF, P2_CT_DEF Frequency programmed When programming the operating frequency it is necessary to select the appropriate VCO and LODIV values. The P1_VCOSEL and P1_LODIV bits are located in the PLL1x0 register and the corresponding P2 bits in the PLL2x0 register. P1_VCOSEL and P2_VCOSEL should always be set to 10 for VCO3. FLL_Fact (CFG3) should be set to 00 if N<28. The integer part of the PLL division ratio is programmed into the PLL1x3 and PLL2x3 registers according to the required synthesizer path. The MSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL1x1 and PLL2x1 registers. The LSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL1x2 and PLL2x2 registers together with the CT_CAL bits if fast frequency switching is required. (Depending on required frequency resolution and coarse tune settings this may not be required.)
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Programming Registers Register Map Diagram Reg. Name R/W Add Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG1 R/W 00 LD_EN LD_LEV TVCO PDP LF_ACT CPL CT_POL Res EXT_VCO FULLD CP_LO_I CFG2 R/W 01 MIX1_IDD MIX1_VB MIX2_IDD MIX2_VB Res KV_RNG NBR_CT_AVG NBR_KV_AVG CFG3 R/W 02 TKV1 TKV2 Res FLL_FACT CT_CPOLREFSTBY CFG4 R/W 03 CLK_DIV_BYPASS XO_CT XO_I2 XO_I1 XO_CR_S TCT CFG5 R/W 04 LO1_I LO2_I T_PH_ALGN CFG6 R/W 05 SU_WAIT Res PLL1x0 R/W 08 P1_VCOSEL P1_CT_E N P1_KV_E N P1_LODI V Res P1_CP_DEF PLL1x1 R/W 09 P1_NUM_MSB PLL1x2 R/W 0A P1_NUM_LSB P1_CT_DEF Res PLL1x3 R/W 0B P1_N Res P1_VCOI PLL1x4 R/W 0C P1_DN P1_CT_GAIN P1_KV_GAIN Res PLL1x5 R/W 0D P1_N_PHS_ADJ Res P1_CT_V PLL2x0 R/W 10 P2_VCOSEL P2_CT_E N P2_KV__ EN P2_LODI V Res P2_CP_DEF PLL2x1 R/W 11 P2_NUM_MSB PLL2x2 R/W 12 P2_NUM_LSB P2_CT_DEF Res PLL2x3 R/W 13 P2_N Res P2_VCOI PLL2x4 R/W 14 P2_DN P2_CT_GAIN P2_KV_GAIN Res PLL2x5 R/W 15 P2_N_PHS_ADJ Res P2_CT_V GPO R/W 18 Res P1_GPO Res P1_ GPO P1_ GPO Res P2_GP Res P2_GPO P2_ GPO Res CHIPREV R 19 PARTNO REVNO RB1 R 1C LOCK CT_CAL CP_CAL Res RB2 R 1D V0_CAL V1_CAL RB3 R 1E RSM_STATE Res TEST R 1F TEN TMUX CPU CPD FNZ LDO _BY P TSEL Res DACTEST Res
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. CFG1 (OOh) - Operational Configuration Parameters CFG2 (O1h) - Mixer Bias and PLL Calibration # Bit Name Default Function
15 LD_EN 1 9 Enable lock detector circuitry
14 LD_LEV 0 Modify lock range for lock detector
13 TVCO(4:0) 0 VCO warm-up time = (TVCO*32)/F REF
8 PDP 1 Phase detector polarity: 0 = positive, 1 = negative
7 LF_ACT 1 C Active loop filter enable, 1 = Active 0 = Passive
6 CPL(1:0) 1 Charge pump leakage current: 00 = no leakage, 01 = low leakage, 10 = mid leakage, 11 =
4 CT_POL 0 Polarity of VCO coarse-tune word: 0 = positive, 1 = negative
2 EXT_VCO 0 0 = Normal operation 1 = external VCO
1 FULLD 0 0 = Half duplex, mixer is enabled according to MODE pin, 1 = Full duplex, both mixers
0 CP_LO_I 0 0 = High charge pump curr ent, 1 = low charge pump current
# Bit Name Default Function 15 MIX1_IDD 1 8 Mixer 1 current setting: 000 = 0mA to 101 = 25mA in 5mA steps. 110 and 111 unused. RF2054 characterized with setting 001 for lowest current.14 0 13 0 12 MIX1_VB 0 Mixer 1 voltage bias. 11 1 C 10 MIX2_IDD 1 Mixer 2 current setting: 000 = 0mA to 101 = 25mA in 5mA steps. 110 and 111 unused. RF2054 characterized with setting 001 for lowest current.90
7 MIX2_VB 0 5 Mixer 2 voltage bias
4 KV_RNG 1 Sets accuracy of voltage measurement during KV calibration: 0 = 8bits, 1 = 9bits
3 NBR_CT_AVG 1 8 Number of averages during CT cal
1 NBR_KV_AVG 0 Number of averages during KV cal
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. CFG3 (O2h) - PLL Calibration CFG4 (O3h) - Crystal Oscillator and Reference Divider # Bit Name Default Function
15 TKV1 0 0 Settling time for first measurement in LO KV compensation
11 TKV2 0 4 Settling time for second measurement in LO KV compensation
3 FLL_FACT 0 4 Default setting 01. Needs to be set to 00 for N<28. 1C T _ C P O L 0
0 REFSTBY 0 Reference oscillator standby mode 0=XO is off in standby mode, 1=XO is on in standby mode
# Bit Name Default Function
15 CLK_DIV 0 1 Reference divi der, divide by 2 (010) to 7 (111) when reference divider is enabled
12 CLK_DIV_BYPASS 1 Reference divider enable d = 0, divider bypass (divide by 1) = 1
11 XO_CT 1 8 Crystal oscillator coarse tune (a pproximately 0.5pF steps from 8pF to 16pF) 10 0
7 XO_I2 0 0 Crystal oscillator current setting
6X O _ I 1 0 5 XO_CR_S 0 Crystal oscillator additional fixed capacitance (approximately 0.25pF)
4 TCT 0 Duration of coarse tune acquisition
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. CFG5 (O4h) - LO Bias CFG6 (O5h) - Start-up Timer # Bit Name Default Function
15 LO1_I 0 0 Local oscillator Path1 current setting
11 LO2_I 0 0 Local oscillator Path2 current setting
7 T_PH_ALGN 0 0 Phase alignment timer
# Bit Name Default Function 15 SU_WAIT 0 0 Crystal oscillator settling timer. 14 0 13 0 12 0 11 0 1 10 0 70 0 30 0
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL1x0 (08h) - VCO, LO Divider and Calibration Select PLL1x1 (09h) - MSB of Fractional Divider Ratio # Bit Name Default Function 15 P1_VCOSEL 0 7 Always set to 10 = VCO3. 14 1
13 P1_CT_EN 1 Path 1 VCO coarse tune: 00 = disabled, 11 = enabled
11 P1_KV_EN 0 1 Path 1 VCO tuning gain calibration: 00 = disabled, 11 = enabled
9 P1_LODIV 0 Path 1 local oscillator divi der: 00 = divide by 1, 01 = divide by 2, 10 = divide by 4, 11 = reserved81 70 1
5 P1_CP_DEF 0 Charge pump current setting
If P1_KV_EN = 11 this value sets charge pump current during KV compensation only41 31 F # Bit Name Default Function
15 P1_NUM_MSB 0 6 Path 1 VCO divider numerator value, most significant 16 bits
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL1x2 (0Ah) - LSB of Fractional Divider Ratio and CT Default PLL1x3 (0Bh) - Integer Divider Ratio and VCO Current # Bit Name Default Function
15 P1_NUM_LSB 0 2 Path 1 VCO divider numerator value, least significant 8 bits
7 P1_CT_DEF 0 7 Path 1 VCO coarse tuning value, used when P1_CT_EN = 00
# Bit Name Default Function
15 P1_N 0 2 Path 1 VCO divider integer value
2 P1_VCOI 0 Path 1 VCO bias setting: 000 = minimum value, 111 = maximum value. RF2054 character- ized with 000.11
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL1x4 (0Ch) - Calibration Settings PLL1x5 (0Dh) - More Calibration Settings # Bit Name Default Function
15 P1_DN 0 1 Path 1 frequency step size used in VCO tuning gain calibration
6 P1_CT_GAIN 1 Path 1 coarse tuning calibration gain
3 P1_KV_GAIN 0 4 Path 1 VCO tuning gain calibration gain
# Bit Name Default Function
15 P1_N_PHS_ADJ 0 0 Path 1 frequency step size used in VCO tuning gain calibration
4 P1_CT_V 1 Path 1 course tuning voltage setting when performing course tuning calibration. Default value is 16. 30 0
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL2x0 (10h) - VCO, LO Divider and Calibration Select PLL2x1 (11h) - MSB of Fractional Divider Ratio # Bit Name Default Function 15 P2_VCOSEL 0 7 Always set to 10 = VCO3. 14 1
13 P2_CT_EN 1 Path 2 VCO coarse tune: 00 = disabled, 11 = enabled
11 P2_KV_EN 0 1 Path 2 VCO tuning gain calibration: 00 = disabled, 11 = enabled
9 P2_LODIV 0 Path 2 local oscillator divi der: 00 = divide by 1, 01 = divide by 2, 10 = divide by 4, 11 = reserved81 5 P2_CP_DEF 0 Charge pump current setting. If P2_KV_EN = 11 this value sets charge pump current during KV compensation only41 31 F # Bit Name Default Function
15 P2_NUM_MSB 0 6 Path 2 VCO divider numerator value, most significant 16 bits
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL2x2 (12h) - LSB of Fractional Divider Ratio and CT Default PLL2x3 (13h) - Integer Divider Ratio and VCO Current # Bit Name Default Function 15 P2_NUM_LSB 0 2 Path 2 VCO divider numerator value, least significant 8 bits. 14 0 13 1 12 0 11 0 7 10 1
7 P2_CT_DEF 0 7 Path 2 VCO coarse tuning value, used when P2_CT_EN = 00
# Bit Name Default Function
15 P2_N 0 2 Path 2 VCO divider integer value
2 P2_VCOI 0 Path 2 VCO bias setting: 000 = minimum value, 111 = maximum value. RF2054 character- ized with 000.11
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. PLL2x4 (14h) - Calibration Settings PLL2x5 (15h) - More Calibration Settings # Bit Name Default Function
15 P2_DN 0 1 Path 2 frequency step size used in VCO tuning gain calibration
6 P2_CT_GAIN 1 Path 2 coarse tuning calibration gain
3 P2_KV_GAIN 0 4 Path 2 VCO tuning gain calibration gain
# Bit Name Default Function
15 P2_N_PHS_ADJ 0 0 Path 2 synthesizer phase adjustment
4 P2_CT_V 1 Path 2 course tuning voltage setting when performing course tuning calibration. Default value is 16. 30 0
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. GPO (18h) - Internal Control Output Settings CHIPREV (19h) - Chip Revision Information # Bit Name Default Function 15 0 0
14 P1_GPO1 0 Setting of GPO1 when path 1 is active, used internally only
12 P1_GPO3 0 Setting of GPO3 when path 1 is active, used internally only
11 P1_GPO4 0 0 Setting of GPO4 when path 1 is active, used internally only
6 P2_GPO1 0 Setting of GPO1 when path 2 is active, used internally only
4 P2_GPO3 0 Setting of GPO3 when path 2 is active, used internally only
3 P2_GPO4 0 0 Setting of GPO4 when path 2 is active, used internally only
# Bit Name Default Function 1 5 P A R T N O 00R F M D P a r t n u m b e r f o r d e v i c e 14 0 13 0 12 0 11 0 0 10 0
7 R E V N O XXP a r t r e v i s i o n n u m b e r
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. RB1 (1Ch) - PLL Lock and Calibration Results Read-back RB2 (1Dh) - Calibration Results Read-Back # Bit Name Default Function
15 LOCK X X PLL lock detector, 0 = PLL locked, 1 = PLL unlocked
14 CT_CAL X CT setting (either result of course tune calibration, or CT_DEF, depending on state of CT_EN). Also depends on the MODE of the device13 X 12 X
11 X X
7 CP_CAL X X CP setting (either result of KV cal, or CP_DEF, depending on state of KV_EN). Also depends on the MODE of the device6X 3X X # Bit Name Default Function
15 VO_CAL X X The VCO voltage measured at the start of a VCO gain calibration
7 V1_CAL X X The VCO voltage measured at the end of a VCO gain calibration
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. RB3 (1Eh) - PLL state Read-Back TEST (1Fh) - Test Modes # Bit Name Default Function
15 RSM_STATE X X State of the radio state machine
# Bit Name Default Function
15 TEN 0 0 Enables test mode
14 TMUX 0 Sets test multiplexer state
11 CPU 0 0 Set charge pump to pump up, 0 = normal operation 1 = pump down
10 CPD 0 Set charge pump to pump down, 0 = normal operation 1 = pump down
9 FNZ 0 0 = normal operation, 1 = fr actional divider modulator disabled
8 LDO_BYP 0 On chip low drop out regulator bypassed
7 TSEL 0 0
4D A C T E S T 0 D A C t e s t 30 0
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Evaluation Board Schematic 51KR1 33pF 33pF 33pF 33pF VDDA VDDD 1nF C710uF C11 22pF 470pF 330pF C10 12K 820RR2 VDDA VDDA 82pF C20 82pF C21 82pF C23 82pF C24 82pF C26 82pF C27 82pF C28 82pF C29 82pF C30 RF_OP2 RF_IP2 RF_OP1 RF_IP1 Socket for USB interface TXD1 DTR#2 RTS#3 UIO4 RXD5 RI#6 GND7 DSR#8 DCD#9 CTS#10 CB411 CB212 SLD 13 USB 14 VCC 15 PU2 16 PU1 17 CB3 18 3V3 19 RST# 20 VCC 21 CB1 22 CB0 23 GND 24 VDDA 10uF C12 REF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 HDR_2X12 VDDA VDDD DNI DNI 33pF C13 33pF C14 33pF C15 1nF C16 VDD VDD 330pF C17 820RR6 82pF DNI R88.2nH RF_OP2_P RF_OP2_N RF_IP2_P RF_IP2_N 33nH DNI R11 RF_OP1_N RF_OP1_P RF_OP1 RF_IP2 RF_OP2 RF_IP1_N RF_IP1_P REF 10nF C19 10nF C18 TC1-1-13M TC4-19+ TC1-1-13M TC4-25+ DNI C31 DNI C33 R17 R15 50 OHM (0.5mm) 50 OHM (0.5mm) 50 OHM (0.5mm) 50 OHM (0.5mm) RF_IP1 10nF C34 33pF C36 33pF C35 LFILT3 LFILT3 LFILT1 LFILT1 LFILT2 LFILT2 Loop Filter XTALIPP10 ENBL1 INDP2 INDN3 REXT4 ANA_DEC5 LFILT16 LFILT27 LFILT38 MODE9 XTALIPN11 NC 15 GND 12 RFIP1P13 RFIP1N14 NC 16 ANA_VDD 22 RFOP1N 17 RFOP1P 18 DIG_VDD 19 NC 20 NC 21 RESETB29 RFIP2N 23 RFIP2P 24 NC25 NC26 RFOP2N27 RFOP2P28 SDATA32 ENX30 SCLK31 GND 33 RF2054 TP1 TP2 22K R21 3.3nHL3 3.3nHL4 VDDD 2GHz IP 1GHz OP 1GHz IP 2GHz OP Note: Disconnect J1 on UM232R (VIO)
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Evaluation Board Layout (RF2056) Board Size 2.5” x 2.5” Board Thickness 0.040”, Board Material FR-4
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Note: The RF2054 was evaluated and characterized on a standard RF2056 evaluation board, but with component changes as defined in the schematic on page 36.
support, contact RFMD at (+1) 336-678-5570 or customerservice@rfmd.com. Package Drawing QFN, 32-Pin, 5mm x 5mm Support and Applications Information Application notes and support material can be downloaded from the product web page: www.rfmd.com/rf205x.
Ordering Information
Part Number Package Quantity RF2054 32-Pin QFN 25-Piece sample bag RF2054SB 32-Pin QFN 5-Piece sample bag RF2054SR 32-Pin QFN 100-Piece reel RF2054TR7 32-Pin QFN 750-Piece reel RF2054TR13 32-Pin QFN 2500-Piece reel 0.08 C 0.1 C -C- 0.85±0.10 Detail ‘D’ Rotated CW Shaded area indicates pin 1. Dimensions in mm. 0.00 0.05 SEATING PLANE -A- -B- 5.00 5.000 3.70±0.10 0.1 CM A B 0.25 Typ. 0.1 CM A B0.23±0.05 32x 0.1 C 0.85±0.10 SEE DETAIL ‘D’ See Detail ‘D’ 0.35±0.05 32x 0.50 Typ.