RF2052

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Document overview

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Technical content

Features

 30MHz to 2.5GHz Frequency Range  Fractional-N Synthesizer  Very Fine Frequency Resolution 1.5Hz for 26MHz Reference  Low Phase Noise VCO  On-Chip Crystal-Sustaining Circuit With Programmable Loading Capacitors  High-Linearity RF Mixer  Integrated LO Buffer  Mixer Input IP3 +18dBm  Mixer Bias Adjustable for Low Power Operation  2.7V to 3.6V Power Supply  Low Current Consumption 55mA to 75mA at 3V  3-Wire Serial Interface

Applications

 CATV Head-Ends  Digital TV Up/Down Converters  Digital TV Repeaters  Multi-Dwelling Units  Cellular Repeaters  Frequency Band Shifters  UHF/VHF Radios  Software Defined Radios  Satellite Communications  Super-Heterodyne Radios  BPSK Modulator DS140110 Package: QFN, 32-Pin, 5mmx5mm

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Detailed Functional Block Diagram Pin Out Serial Data Interface, Control and Biasing Analog Regulator Digital Regulator LO Divider /1, /2, or /4 LO Buffer Mixer VCO 1 VCO 2 VCO 3 Voltage Controlled Oscillators Reference Divider /1 to /7 Reference Oscillator Circuitry and Crystal Tuning - + Vref N Divider Phase / Freq Detector Frac-N Sequence Generator Charge Pump Synthesizer Vtune ANA_VDD DIG_VDD ANA_DEC LFILT1 LFILT2 LFILT3 INDN INDP REXT XTALIPP XTALIPN ENX ENBL MODE RESETB SDATA SCLK RFOPN RFOPP RFIPN RFIPP SERIAL BUS CONTROL ANA_VDD OP 4:1 1:1 IP ENBL INDP INDN REXT ANA_DEC LFILT1 LFILT2 8LFILT3 2527 2630 29 2831 NC NC RFOPN RFOPP RESETB ENX SCLK

32 SDATA

ANA_VDD NC NC DIG_VDD NC 17 NC 9 1110 141312 15 MODE XTALIPP XTALIPN GND NC NC NC NC EP

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Note 1: The signal should be connected to this pin such that DC current cannot flow into or out of the chip, either by using AC coupling capacitors or by use of a transformer (see evaluation board schematic). Note 2: DC current needs to flow from ANA_VDD into this pin, either through an RF inductor , or transformer (see evaluation board schematic). Note 3: Alternatively an external reference can be AC-coupled to pin 11 XTALIPN, and pin 10 XTALIPP decoupled to ground. This may make PCB routing simpler. Pin Function Description 1E N B L Ensure that the ENBL high voltage level is not greater than VDD. An RC low-pass filter could be used to reduce digital noise. 2I N D P VCO 3 differential inductor. Normally a micro-strip inductor is used to set the VCO 3 frequency range 1200MHz to 1600MHz. 3I N D N VCO 3 differential inductor. Normally a micro-strip inductor is used to set the VCO 3 frequency range 1200MHz to 1600MHz. 4R E X T External bandgap bias resistor. Connect a 51k resistor from this pin to ground to set the bandgap reference bias current. This could be a sensitive low frequency noise injection point. 5A N A _ D E C Analog supply decoupling capacitor. Connect to analog supply and decouple as close to the pin as possible. 6L F I L T 1 Phase detector output. Low-frequency noise-sensitive node. 7L F I L T 2 Loop filter op-amp output. Low-frequency noise-sensitive node. 8L F I L T 3 VCO control input. Low-frequency noise-sensitive node. 9M O D E Mode select pin. An RC low-pass filter can be used to reduce digital noise. 10 XTALIPP Reference crystal / reference oscillator input. Should be AC-coupled if an external reference is used. See note 3. 11 XTALIPN Reference crystal / reference oscillator input. Should be AC-coupled to ground if an external reference is used. See note 3. 12 GND Connect to ground. 13 NC 14 NC 15 NC 16 NC 17 NC 18 NC

19 DIG_VDD

Digital supply. Should be decoupled as close to the pin as possible. 20 NC 21 NC 22 ANA_VDD Analog supply. Should be decoupled as close to the pin as possible. 23 RFIPN Differential input. See note 1. 24 RFIPP Differential input. See note 1. 25 NC 26 NC

27 RFOPN

Differential output. See note 2. 28 RFOPP Differential output. See note 2. 29 RESETB Chip reset (active low). Connect to DIG_VDD if external reset is not required. 30 ENX Serial interface select (active low). An RC low-pass filter could be used to reduce digital noise. 31 SCLK Serial interface clock. An RC low-pass filter could be used to reduce digital noise. 32 SDATA Serial interface data. An RC low-pass filter could be used to reduce digital noise. EP Exposed pad Connect to ground. This is the ground reference for the circuit. All decoupling should be connected here through low impedance paths.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Absolute Maximum Ratings Parameter Rating Unit Supply Voltage (VDD) -0.5 to +3.6 V Input Voltage (VIN), any Pin -0.3 to V DD+0.3 V RF/IF Mixer Input Power +15 dBm Operating Temperature Range -40 to +85 °C Storage Temperature Range -65 to +150 °C Parameter Specification Unit ConditionMin. Typ. Max. ESD Requirements Human Body Model General 2000 V RF Pins 1000 V Machine Model General 200 V RF Pins 100 V Operating Conditions Supply Voltage (VDD) 2.7 3.0 3.6 V Temperature (TOP) -40 +85 °C Logic Inputs/Outputs VDD=Supply to DIG_VDD pin Input Low Voltage -0.3 +0.5 V Input High Voltage V DD / 1.5 V DD V Input Low Current -10 +10 uA Input=0V Input High Current -10 +10 uA Input=V DD Output Low Voltage 0 0.2*V DD V Output High Voltage 0.8*V DD VDD V Load Resistance 10 k  Load Capacitance 20 pF Static Programmable Supply Current (IDD) Low Current Setting 55 mA High Linearity Setting 75 mA Standby 3 mA Reference oscillator and bandgap only. Power Down Current 140 AE N B L = 0 a n d R E F _ S T B Y = 0 Mixer Mixer output driving 4:1 balun. Gain -2 dB Not including balun losses. Noise Figure Low Current Setting 9.5 dB High Linearity Setting 12 dB

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Parameter Specification Unit ConditionMin. Typ. Max. Mixer, cont. IIP3 Low Current Setting +10 dBm High Linearity Setting +18 dBm Pin1dB Low Current Setting +2 dBm High Linearity Setting +12 dBm RF and IF Port Frequency Range 30 2500 MHz Mixer Input Return Loss 10 dB 100  differential Voltage Controlled Oscillator Open Loop Phase Noise at 1MHz Offset 2GHz LO Frequency -130 dBc/Hz 1GHz LO Frequency -135 dBc/Hz 500MHz LO Frequency -140 dBc/Hz Reference Oscillator Xtal Frequency 10 52 MHz External Reference Frequency 10 104 MHz Reference Divider Ratio 1 7 External Reference Input Level 500 800 1500 mV P-P AC-coupled Local Oscillator Synthesizer Output Frequency 300 2400 MHz Dependant on VCO 3 external inductor. After LO dividers. Phase Detector Frequency 52 MHz Closed Loop Phase-Noise at 10 kHz Offset 26MHz phase detector frequency 2GHz LO Frequency -90 dBc/Hz 1GHz LO Frequency -95 dBc/Hz 500MHz LO Frequency -102 dBc/Hz

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Typical Performance Characteristics: Synthesizer and VCO - VDD=3V , TA=25°C, as measured on RF2052 evaluation board, for application schematic see page 34. Phase Detector Frequency=26MHz, Loop Bandwidth=60kHz. VCO3 With Passive Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 1200MHz 600MHz 300MHz VCO2 With Passive Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 1600MHz 800MHz 400MHz VCO1 With Passive Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 2000MHz 1000MHz 500MHz VCO2 With Active Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 1600MHz 800MHz 400MHz VCO3 With Active Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 1200MHz 600MHz 300MHz VCO1 With Active Loop Filter -160 -140 -120 -100 -80 -60 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 2000MHz 1000MHz 500MHz

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Typical Performance Characteristics: Synthesizer and VCO - VDD=3V , TA=25°C unless stated, as measured on RF2052 evaluation board, for application schematic see page 34. VCO2 Open Loop Phase Noise -160 -140 -120 -100 -80 -60 -40 -20 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 2000MHz 1800MHz 1600MHz VCO3 Open Loop Phase Noise -160 -140 -120 -100 -80 -60 -40 -20 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 1600MHz 1400MHz 1200MHz VCO1 Open Loop Phase Noise -160 -140 -120 -100 -80 -60 -40 -20 1 10 100 1000 10000 Offset Frequency (kHz) Phase Noise (dBc/Hz) 2400MHz 2200MHz 2000MHz VCO1 F VCO versus V T for the same coarse tune setting 2045 2050 2055 2060 2065 2070 2075 2080 2085 2090 2095 VT (V) FVCO (MHz) -40 VCO2 Tuning Gain versus Frequency 1500 1600 1700 1800 1900 2000 2100 FVCO (MHz) Tuning Gain (MHz/V) VCO1 Tuning Gain versus Frequency 1900 2000 2100 2200 2300 2400 2500 FVCO (MHz) Tuning Gain (MHz/V)

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Typical Performance Characteristics: RF Mixer - VDD=3V , TA=25°C unless stated, as measured on RF2052 evaluation board, for application schematic see page 34. Mixer Conversion Gain, IF Output=100MHz -10 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Conversion Gain (dB) -40°C +27°C +85°C Operating Current versus Temperature and Supply Voltage 001 010 011 100 101 Mixer Bias Current Setting (MIX2_IDD) Supply Current (mA) -40°C, +2.7V -40°C, +3.0V -40°C, +3.6V +27°C, +2.7V +27°C, +3.0V +27°C, +3.6V +85°C, +2.7V +85°C, +3.0V +85°C, +3.6V Gain versus Temperature and Supply Voltage (excluding losses in PCB and Baluns) -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 - 4 0 - 2 0 0 2 04 06 08 0 1 0 0 Temperature (°C) Gain (dB) 2.7V 3.0V 3.6V Mixer Typical RF and LO Leakage at IF Output -70 -60 -50 -40 -30 -20 -10 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Level at Mixer Output (dBm) IF Output at 100MHz RF Leakage LO Leakage (High Side) Mixer Typical IF and LO Leakage at RF Input -80 -70 -60 -50 -40 -30 -20 -10 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Level at Mixer Input (dBm) 100MHz IF Leakage to RF Port LO Leakage (High Side) to RF Mixer Typical LO Leakage at IF Output IF Output=100MHz -70 -60 -50 -40 -30 -20 -10 0 500 1000 1500 2000 2500 RF Input Frequency (MHz) LO Leakage (dBm) -40 Deg C +27 Deg C +85 Deg C

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Typical Performance Characteristics: RF Mixer - VDD=3V , TA=25°C unless stated, as measured on RF2052 evaluation board, for application schematic see page 34. Mixer Noise Figure versus Bias Current IF Output=100MHz 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Noise Figure (dB) MIX2_IDD = 001 MIX2_IDD = 010 MIX2_IDD = 011 MIX2_IDD = 100 MIX2_IDD = 101 Mixer Input Power for 1dB Compression versus Temperature and Bias Current Setting IF Output=100MHz 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Pin 1dB (dBm) -40 Deg C, 001 +27 Deg C, 001 +85 Deg C, 001 -40 Deg C, 011 +27 Deg C, 011 +85 Deg C, 011 -40 Deg C, 101 +27 Deg C, 101 +85 Deg C, 101 Mixer Input IP3 versus Bias Current Setting 001 010 011 100 101 Bias Current Setting (MIX2_IDD) Input IP3 (dBm) 500MHz RF to 100MHz IF 900MHz RF to 100MHz IF 2000MHz RF to 500MHz IF Mixer Noise Figure versus Temperature IF Output=100MHz and MIX2_IDD=100 250 500 750 1000 1250 1500 1750 RF Input Frequency (MHz) Noise Figure (dB) -40°C +27°C +85°C IIP3 versus Temperature and Supply Voltage (Max Linearity) 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 -40 -20 0 20 40 60 80 100 Temperature (°C) IIP3 (dBm) 2.7V 3.0V 3.6V NF versus Temperature and Supply Voltage (Low Noise Mode MIX2_IDD=001) 8.0 8.5 9.0 9.5 10.0 10.5 11.0 -40 -20 0 20 40 60 80 100 Temperature (°C) NF(dB) 2.7V 3.0V 3.6V

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Detailed Description The RF2052 is a wideband RF frequency converter chip which includes a fractional-N phase-locked loop, a crystal oscillator cir- cuit, a low noise VCO core, an LO buffer, and an RF mixer. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls . All on-chip registers are programmed through a simple three- wire serial interface. VCO The VCO core in the RF2052 consists of three VCOs which, in conjunction with the integrated 2/4 LO divider, cover the LO range from 300MHz to 2400MHz. VCO 1, 2, and 3 are selected using the PLL2x0:P2_VCOSEL co ntrol word. Each VCO has 128 overlapping bands to achieve an acceptable VCO gain (20MHz/V nom) and hence a good phase noise performance across the whole tuning range. The chip automatically selects the correct VCO band (“VCO coarse tuning ”) to generate the desired LO frequency based on the values programmed into the PLL2 registers bank. For information on how to program the desired LO frequency refer to page 11. The automatic VCO band selection is triggered every time the ENBL pin is taken high. Once the band has been selected the PLL will lock onto the correct frequency. During the band selection process fixed capacitance elements are progressively connected to the VCO resonant circuit until the VCO is oscillating at approximately the correct frequency. The output of this band selection is made available in the RB1:CT_CAL read-back register. A value of 127 or 0 in this register indicates that the selection was unsuccessful, this is usually due to the wrong VCO being selected so the user is trying to program a frequency that is outside of the VCO operating range. A value between 1 and 126 indicates a successful calibration, the actual value being dependent on the desired frequency as well as process variation for a particular device. The band selection takes approximately 1500 cycles of the phase detector clock (about 50us with a 26MHz clock). The band select process will center the VCO tuning voltage at about 1.2V, compensating for manufacturing tolerances and process variation as well as environmental factors including tem- perature. For applications where the synthesizer is always on and the LO frequenc y is fixed, the synthesizer will maintain lock over a +/-60°C temperature range. However it is recommended to re-initiate an automatic band selection for every 30 degrees change in temperature in order to maintain optimal synthesizer performance. This assumes an active loop filter . If start-up time is a critical parameter, and the user is always programming the same frequency for the PLL, the calibration result may be read back from the RB1:CT_CAL register, and written to the PLL2x2:P2_CT_DEF register. The calibration function must then be disabled by setting the PLL2x0:P2_CT_EN control word to 0. For further information please refer to the RF205x Calibration User Guide. When operating using VCO1 for frequencies above 2.2GHz, it is recommended to change the coarse tuning voltage setting, PLL2x5:P2_CT_V, from the default value of 16 down to 12. The LO divide ratio is set by the PLL2x0:P2_LODIV control words. The current in the VCO core can be progra mmed using the PLL2x3:P2_VCOI control word. This allows optimization of VCO per- formance for a particular frequency. For applications where the required LO frequency is above 2GHz it is recommended that the LO buffer current be increased by setting CFG5:LO2_I to 1100 (hex value C). VCO Tank Inductor VCO Frequency Range DIV 2 DIV 4

1 Internal 1800MHz to 2400MHz 900MHz to 1200MHz 450MHz to 600MHz

2 Internal 1500MHz to 2100MHz 750MHz to 1050MHz 375MHz to 525MHz

3 External 1200MHz to 1600MHz* 600MHz to 800MHz 300MHz to 400MHz

*The frequency of VCO3 is set by external inductors and can be varied by the user.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Fractional-N PLL The IC contains a charge-pump based fractional-N phase locked loop (PLL) for controlling the three VCOs. The PLL includes automatic calibration systems to counteract the effects of pr ocess and environmental variations, ensuring repeatable lock- time and noise performance. The PLL is intended to use a reference frequency signal of 10MHz to 104MHz. A reference divider (divide by 1 to divide by 7) is supplied and should be programmed to limit the frequency at the phase detector to a max- imum of 52MHz. The reference divider bypass is controlled by bit CLK DIV_BYP, set low to enable the reference divider and set high for divider bypass (divide by 1). The remaining three bits CLK DIV<15:13> set the reference divider value, divide by 2 (010) to 7 (111) when the reference divider is enabled. Two PLL programming banks are provided, the first bank is preceded by the label PLL1 and the second bank is preceded by the label PLL2. For the RF2052 the default programming bank is PLL2, selected by setting the MODE pin high. The PLL will lock the VCO to the frequency FVCO according to: FVCO=NEFF*FOSC/R where NEFF is the programmed fractional N divider value, F OSC is the reference input frequency, and R is the programmed R divider value (1 to 7). The N divider is a fractional divider, containing a dual-modulus prescaler and a digitally spur-compensated fractional sequence generator to allow fine frequency steps. The N divider is programmed using the N and NUM bits as follows: First determine the desired, effective N divider value, NEFF: NEFF=FVCO*R/FOSC N(9:0) should be set to the integer part of NEFF. NUM should be set to the fractional part of NEFF multiplied by 224=16777216. Example: VCO1 operating at 2220MHz, 23.92MHz reference frequency, the desired effective divider value is: NEFF=FVCO *R / FOSC=2220 *1 / 23.92=92.80936454849. The N value is set to 92, equal to the integer part of N EFF, and the NUM value is set to the fractional portion of N EFF multiplied by 224: NUM=0.80936454895 * 2 24=13,578,884. Converting N and NUM into binary results in the following: N= 0 0101 1100 NUM=1100 1111 0011 0010 1000 0100 So the registers would be programmed: P2_N = 0 0101 1100 P2_NUM_MSB=1100 1111 0011 0010 P2_NUM_LSB=1000 0100 The maximum NEFF is 511, and the minimum NEFF is 15, when in fractional mode. The minimum step size is FOSC/R*2 24. Thus for a 23.92MHz reference, the frequency step size would be 1. 4Hz. The minimum reference frequency that could be used to program a frequency of 2400MHz (using VCO1) is 2400/511, 4.697MHz (approx).

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Phase Detector and Charge Pump The chip provides a current output to drive an external loop filter. An on-chip operational amplifier can be used to design an active loop filter or a passive design can be implemented. The maximum charge pump output current is set by the value con- tained in the P2_CP_DEF field and CP_LO_I. In the default state (P2_CP_DEF=31 and CP_LO_I=0) the charge pump current (ICPset) is 120uA. If CP_LO_I is set to 1 this current is reduced to 30uA. The charge pump current can be altered by changing the value of P2_CP_DEF. The charge pump current is defined as: ICP= ICPset*CP_DEF / 31 If automatic loop bandwidth correction is enabled the charge pu mp current is set by the calibration algorithm based upon the VCO gain. For more information on the VCO gain calibration, whic h is disabled by default, please refer to the RF205x Calibra- tion User Guide. The phase detector will operate with a maximum input frequency of 52MHz. Note that for high phase detector frequencies, the divider ratio decreases. For N<28 the FLL_FACT register needs to be changed to 00 from the default value of 01. This is to ensure correct VCO band selection. Loop Filter The PLL may be designed to use an active or a passive loop filter as required. The internal configuration of the chip is shown below. If the CFG1:LF_ACT bit is asserted high, the op-amp will be enabled. If the CFG1:LF_ACT bit is asserted low, the internal op-amp is disabled and a high impedance is presented to the LFILT1 pin. The RF 205x Programming Tool software can assist with loop filter designs. Because the op-amp is used in an inverting configuration in active mode, when the passive loop filter mode is selected the phase-detector polarity should be inverted. For active mode, CFG1:PDP=1, for passive mode, CFG1:PDP=0. The charge pump output voltage compliance range is typically +0.7V to +1.5V. For applications using a passive loop filter VCO coarse tuning must be performed regularly enough to ensure that the VCO tuning voltage falls within this compliance range at all temperatures. The active loop filter maintains the charge pu mp output voltage in the center of the compliance range, and the op-amp provides a wider VCO tuning voltage range, typical 0V to +2.4V. LFILT1 LFILT2 LFILT3 To VCO Tuning LF_ACT=TRUE+1.1V

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Crystal Oscillator The PLL may be used with an external reference source, or its own crystal oscillator. If an external source (such as a TCXO) is being used it should be AC-coupled into one of the XO inputs, and the other input should be AC-coupled to ground. A crystal oscillator typically takes many milliseconds to settle, and so for applications requiring rapid pulsed operation of t he PLL (such as a TDMA system, or Rx/Tx half -duplex system) it is necessary to keep the XO running between bursts. However, when the PLL is used less frequently, it is desirable to turn off the XO to minimize current draw. The REFSTBY register is pro- vided to allow for either mode of operation. If REFSTBY is programmed high, the XO will continue to run even when ENBL is asserted low. Thus the XO will be stable and a clock is immediately available when ENBL is asserted high, allowing the chip to assume normal operation. On cold start, or if REFSTBY is programmed low, the XO will need a warm-up period before it can pro- vide a stable clock. The length of this warm-up period will be dependant on the crystal characteristics. The crystal oscillator circuit contains inte rnal loading capacitors. No external loading capacitors are required, dependant on the crystal loading specification. The internal loading capacitors are a combination of fixed capacitance, and an array of switched capacitors. The switched capacitors can be used to tune the crystal oscillator onto the required center frequency and minimize frequency error. The PCB stray capacitance and oscillat or input and output capacitance will also contribute to the crystal’s total load capacitance. The register settings in the CFG4 register for the switched capacitors are as follows:

• Coarse Tune XO_CT (4 bits) 15*0.55pF, default 0100
• Fine Step XO_CR_S (1 bit) 1*0.25pF , default 0 The on chip fixed capacitance is approximately 4.2pF. Wideband Mixer The RF2052 includes a wideband, double-balanced Gilbert cell mixer. It supports RF/IF frequencies of 30MHz to 2500MHz using the internal VCO to provide the LO frequency of 300MHz to 2400MHz. The mixer has an input port and an output port that can be used for either IF or RF, i.e. for up conversi on or down conversion. The mixer current can be programmed to between 15mA and 35mA depending on linearity requirements , using the MIX2_IDD<3:0> word in the CFG2 register. The majority of the mixer current is sourced through the output pins via either a centre-tapped balun or an RF choke in the external matching circuitry to the supply. The RF mixer input and output ports are differential and require simple matching circuits optimized to the specific application frequencies. A conversion gain of approximately -3dB to 0dB is achieved with 100 differential input impedance, and the out- puts driving 200 differential load impedance. Increasing the mixer output load increases the conversion gain. The mixer has a broadband common gate input. The input impe dance is dominated by the resistance set by the mixer 1/gm term, which is inversely proportional to the mixer current setting. The resistance will be approximately 85 at the default mixer current setting (100). There is also some shunt capacitance at the mixer input, and the inductance of the bond wires to con- sider at higher frequencies. The mixer output is high impedance, consisting of a resistance of approximately 2k  in parallel with some capacitance. The mixer output does not need to be matched as such, just to see a resistive load. A higher resistance load will give higher output voltage and gain. A shunt inductor can be used to resonate with the mixer output capacitance at the frequency of interest. This inductor may not be required at lower frequencies where the impedance of the output capacitance is less significant. At higher output frequencies the inductance of the bond wires becomes more significant. For more information about the mixer port impedances and matc hing, please refer to the RF205x Family Application Note on Matching Circuits and Baluns.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . General Programming Information Serial Interface All on-chip registers in the RF2052 are progra mmed using a 3-wire serial bus which supports both write and read operations. Synthesizer programming, device configuration and control are achieved through a mixture of hardware and software controls. Certain functions and operations require the use of hardware controls via the ENBL, MODE, and RESETB pins in addition to programming via the serial bus. For most applications the MODE pin can be held high. Serial Data Timing Characteristics Parameter Description Time t1 Reset delay >5ns t2 Programming setup time >5ns t3 Programming hold time >5ns t4 ENX setup time >5ns t5 ENX hold time >5ns t6 Data setup time >5ns t7 Data hold time >5ns t8 ENBL setup time >0ns t9 ENBL hold time >0ns MCU ENX SCLK SDATA ENBL RESETB MODE 3-wire bus Hardware Controls RF2052 RESETB ENX SCLK SDATA ENBL X Reset chip Initial programming of device Programming updates Serial bus X XX X X X X t8t6 t7 t9

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Write Initially ENX is high and SDATA is high impedance. The write operation begins with the controller starting SCLK. On the first fall- ing edge of SCLK the baseband asserts ENX lo w. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In write mode the baseband will drive SDATA for the entire telegram. RF2052 will read the data bit on the rising edge of SCLK. The next 7 data bits are the register address, MSB first. This is followed by the payload of 16 data bits for a total write mod e transfer of 24 bits. Data is latched into RF2052 on the last rising edge of SCLK (after ENX is asserted high). For more information, please refer to the timing diagram on page 14. The maximum clock speed for a register write is 19.2MHz. A re gister write therefore takes approximately 1.3us. The data is latched on the rising edge of the clock. Th e datagram consists of a single start bit followed by a ‘0’ (to indicate a write opera- tion). This is then followed by a seven bit address and a sixteen bit data word. Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional risi ng clock edge before the ENX line is set low to ensure the address/data are read correctly. Read Initially ENX is high and SDATA is high impedance. The read operation begins with the controller starting SCLK. The controller is in control of the SDATA line during the address write operation. On the first falling edge of SCLK the baseband asserts ENX low. The second rising edge of SCLK is reserved to allow the SDI to initialize, and the third rising edge is used to define whether the operation will be a write or a read operation. In read mode the baseband will drive SDATA for the address portion of the tele- gram, and then control will be handed over to RF2052 for the data portion. RF2052 will read the data bits of the address on the rising edge of SCLK. After the address has been written, control of the SDATA line is handed over to RF2052. One and a half clocks are reserved for turn-around, and then the data bits ar e presented by RF2052. The data is set up on the rising edge of SCLK, and the controller latches the data on the falling edge of SCLK. At the end of the data transmission, RF2052 will release control of the SDATA line, and the controller asserts ENX high. The SDATA port on RF2052 transitions from high impedance to low impedance on the first rising edge of the data portion of the transaction (for example, 3 rising edges after the last address bit has been read), so the controller chip should be presenting a high impedance by that time. For more information, please refer to the timing diagram on page 14. The maximum clock speed for a register read is 19.2MHz. A register read therefore takes approximately 1.4us. The address is latched on the rising edge of the clock and the data output on the falling edge. The datagram consists of a single start bit fo l- A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENX SCLK SDATA XA 6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ENX SCLK SDATA XA 6 A5

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . lowed by a ‘1’ (to indicate a read operation), followed by a seven bit address. A 1.5 bit delay is introduced before the sixteen bit data word representing the register content is presented to the receiver. Note that since the serial bus does not require the presence of the crystal clock, it is necessary to insert an additional risi ng clock edge before the ENX line is set low to ensure the address is read correctly. Hardware Control Three hardware control pins are provided: ENBL, MODE, and RESETB. ENBL Pin The ENBL pin has two functions: to enable the analog circuits in the chip and to trigger the VCO band selection as described in the VCO section on page 10. As outlined in the VCO section the chip has a built-in automatic VCO band selection to tune the selected VCO to the desired fre- quency. The band selection is initiated when the ENBL pin is taken high. Every time the frequency of the synthesizer is re-pro- grammed, the ENBL has to be inserted high to initiate the automatic VCO band selection (VCO coarse tune). RESETB Pin The RESETB pin is a hardware reset control that will reset all digital circuits to th eir start-up state when asserted low. The device includes a power-on-reset function, so this pin should not normally be required, in which case it should be connected to the positive supply. MODE Pin The MODE pin controls which PLL programming register bank is active. For normal operation of the RF2052 the MODE pin should be set high to select the default PLL2 programming registers. It is possible to set the FULLD bit in the CFG1 register high. This a l l o w s t h e M O D E p i n t o s e l e c t e i t h e r P L L 1 r e g i s t e r b a n k (MODE=low) or PLL2 register bank (MODE=high). This may be useful for some applications where two LO frequencies can be programmed into the registers then the MODE pin used to toggle between them. The ENBL pin will also need to be cycled to re- lock the synthesizer for each frequency. ENBL Pin REFSTBY Bit XO and Bias Block Analogue Block Digital Block Low 0 Off Off On Low 1 On Off On H i g h0 O nO nO n H i g h1 O nO nO n Parameter Description Time t1 MODE setup time >5ns t2 MODE hold time >5ns ENBL MODE

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Programming the RF2052 The figure below shows an overview of the device programming. Note: The set-up processes 1 to 2, 2 to 3, and 3 to 4 are explained further below. Additional information on device use and programming can be found on the RF 205x family page of the RFMD web site (http://www.rfmd.com/rf205x). The following documents may be particularly helpful:

• RF205x Frequency Synthesizer User Guide
• RF205x Calibration User Guide Device off Set-up device operation Set operating frequencies Set calibration mode ENABLE device Apply power Reset device Apply power to the device. Ensure the device is set into a known and correct state. To use the device it will be necessary to program the registers with the desired contents to achieve the required operating characteristics. See following sections for details. When programming is complete the device can be enabled.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Start-up When starting up and following device reset then REFSTBY=0, REFSTBY should be asserted high approximately 500 s before ENBL is taken high. This is to allow the XO to settle and will depend on XO characteristics. The various calibration routines w ill also take some time depending on whether they are enabled or not. Coarse tuning calibration takes about 50 s and VCO tun- ing gain compensation takes about 100 s. Additionally, time for the PLL to settle wi ll be required. All of these timings will be dependant upon application specific factors such as loop filter bandwidth, reference clock freq uency, XO characteristics and so on. The fastest turn-on and lock time will be obtained by leaving REFSTBY asserted high, disabling all calibration routines, and setting the PLL loop bandwidth as wide as possible. The device can be reset into its initial state (default settings) at any time by performing a hard reset. This is achieved by setting the RESETB pin low for at least 100ns. Setting Up Device Operation The device offers a number of operating modes which need to be set up in the device before it will work as intended. This is achieved as follows. Three registers need to be written, taking 3.9us at the maximum clock speed. If the device is used with an active filter in sim - plex operation it will not be necessary to program CFG1 reducing the programming time to 2.6us. Set-up device operation Disable active loop filter? Default Yes LF_ACT Set to 0 Program MIX2_IDD Set-up complete Program XO_CT, XO_CR_S and CLK_DIV Internal capacitors used to set Xtal load Mixer linearity When setting up the device it is necessary to decide if an active or passive loop filter will be used in the phase locked loop. The LF_ACT bit is located in the CFG1 register and is active by default. Set the phase detector polarity bit in CFG1since the active filter inverts the loop filter voltage. The mixer linearity setting is then selected. The default value is 4 with 1 being the lowest setting and 5 the highest. The MIX2_IDD bits are located in the CFG2 register. The internal crystal loading capacitors are also programmed to present the correct load to the crystal. The capacitance internal to the chip can be varied from 8-16pF in 0.25pF steps (default=10pF). The reference divider must also be set to determine the phase detector frequency (default=1). These bits are located in the CFG4 register.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Setting Up VCO Coarse Tuning and Loop Filter Calibration If the user wishes to disable the VCO coarse tune calibration or enable the loop filter calibration then the following program- ming operation will need to take place. Two registers need to be written taking 2.6us at maximum clock speed if the course tuning is deactivated or the loop filter cal- ibration activated. Since it is necessary to program these registers when setting the operating frequency (see next section) this operation usually carries no overhead. The coarse tune calibration takes approximately 50us when using a 26MHz reference clock (it will take proportionally longer if a slower clock is used, and vice versa). Disable VCO coarse tune? Default Yes P2_CT_EN Set to 00 Set calibration mode Operating mode set Enable loop filter cal? Default Yes Loop filter calibration When setting up the device it is necessary to decide whether to deactivate the devices' internal VCO calibration or provide the calibration information directly. These bits are located in the PLL2x0 register and are active by default. It is also necessary to decide whether to activate the loop filter calibration mode, only necessary when operating the device over very wide band of frequencies. These bits are also located in the PLL2x0 register. The default setting assumes an active loop filter is used.

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Setting The Operating Frequency Setting the operating frequency of the device requires a number of registers to be programmed. A total of four registers must be programmed to set the device operating frequency. This will take 5.2us for each path at maxi- mum clock speed. To change the frequency of the VCO it will be necessary to repe at these operations. However, if the frequency shift is small it may not be necessary to reprogram the VCOSEL and LODIV bits reducing the register writes to three. For an example on how to determine the integer and fractional pa rts of the synthesizer PLL divisi on ratio please refer to the detailed description of the PLL on page 11. Set operating frequencies Program P2_VCOSEL and P2_LODIV Program P2_N Program P2_NUM_MSB Program P2_NUM_LSB, P2_CT_DEF Frequency programmed When programming the operating frequency it is necessary to select the appropriate VCO and LODIV values. The P2_VCOSEL and P2_LODIV bits are located in the PLL2x0 register. If the LO frequency is above 2GHz the LO path current (CFG5) should be set to 0xC The integer part of the PLL division ratio is programmed into the PLL2x3 register. The MSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL2x1 register.The LSB of the fractional part of the synthesizer PLL divider value is programmed into the PLL2x2 register together with the CT_CAL bits if fast frequency switching is required. (Depending on required frequency resolution and coarse tune settings this may not be required.)

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Programming Registers Register Map Diagram Reg. Name R/W Add Data 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CFG1 R/W 00 LD_EN LD_LEV TVCO PDP LF_ACT CPL CT_POL Res EXT_VCO FULLD CP_LO_I CFG2 R/W 01 MIX1_IDD MIX1_VB MIX2_IDD MIX2_VB Res KV_RNG NBR_CT_AVG NBR_KV_AVG CFG3 R/W 02 TKV1 TKV2 Res FLL_FACT CT_CPOLREFSTBY CFG4 R/W 03 CLK_DIV_BYPASS XO_CT XO_I2 XO_I1 XO_CR_S TCT CFG5 R/W 04 LO1_I LO2_I T_PH_ALGN CFG6 R/W 05 SU_WAIT Res PLL1x0 R/W 08 P1_VCOSEL P1_CT_E N P1_KV_E N P1_LO- DIV Res P1_CP_DEF PLL1x1 R/W 09 P1_NUM_MSB PLL1x2 R/W 0A P1_NUM_LSB P1_CT_DEF Res PLL1x3 R/W 0B P1_N Res P1_VCOI PLL1x4 R/W 0C P1_DN P1_CT_GAIN P1_KV_GAIN Res PLL1x5 R/W 0D P1_N_PHS_ADJ Res P1_CT_V PLL2x0 R/W 10 P2_VCOSEL P2_CT_E N P2_KV__E N P2_LO- DIV Res P2_CP_DEF PLL2x1 R/W 11 P2_NUM_MSB PLL2x2 R/W 12 P2_NUM_LSB P2_CT_DEF Res PLL2x3 R/W 13 P2_N Res P2_VCOI PLL2x4 R/W 14 P2_DN P2_CT_GAIN P2_KV_GAIN Res PLL2x5 R/W 15 P2_N_PHS_ADJ Res P2_CT_V GPO R/W 18 Res P1_G- PO1 Res P1_ GPO P1_ GPO Res P2_G- PO1 Res P2_G- PO3 P2_ GPO Res CHIPREV R 19 PARTNO REVNO RB1 R 1C LOCK CT_CAL CP_CAL Res RB2 R 1D V0_CAL V1_CAL RB3 R 1E RSM_STATE Res TEST R 1F TEN TMUX CPU CPD FNZ LDO _BY P TSEL Res DACTEST Res

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . CFG1 (OOh) - Operational Configuration Parameters CFG2 (O1h) - Mixer Bias and PLL Calibration # Bit Name Default Function

15 LD_EN 1 9 Enable lock detector circuitry

14 LD_LEV 0 Modify lock range for lock detector

13 TVCO(4:0) 0 VCO warm-up time=TVCO/(F

REF*256) 12 0 11 0 1 10 0

8 PDP 1 Phase detector polarity: 0=positive, 1=negative

7 LF_ACT 1 C Active loop filter enable, 1=Active 0=Passive

6 CPL(1:0) 1 Charge pump leakage current: 00=no leakage, 01=low leakage, 10=mid leakage, 11=high

4 CT_POL 0 Polarity of VCO coarse-tune word: 0=positive, 1=negative

2 EXT_VCO 0 0=Normal operation 1=external VCO (VCO 3 disabled, KV_CAL and CT_CAL must be dis-

abled)

1 FULLD 0 0=Half duplex, mixer is enabled according to MODE pin, 1=Full duplex, both mixers enabled

0 CP_LO_I 0 0=High charge pump current, 1=low charge pump current

# Bit Name Default Function 15 MIX1_IDD 1 8 This register is not used for the RF2052. 14 0 13 0 12 MIX1_VB 0 This register is not used for the RF2052. 11 1 C 1 0 MIX2_IDD 1 Mixer 2 current setting: 000=0mA to 111=35mA in 5mA steps

7 MIX2_VB 0 5 Mixer 2 voltage bias

4 KV_RNG 1 Sets accuracy of voltage measurement during KV calibration: 0=8bits, 1=9bits

3 NBR_CT_AVG 1 8 Number of averages during CT cal

1 NBR_KV_AVG 0 Number of averages during KV cal

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . CFG3 (O2h) - PLL Calibration CFG4 (O3h) - Crystal Oscillator and Reference Divider # Bit Name Default Function

15 TKV1 0 0 Settling time for first measurement in LO KV compensation

11 TKV2 0 4 Settling time for second measurement in LO KV compensation

3 FLL_FACT 0 4 Default setting 01. Needs to be set to 00 for N<28. This case can arise when higher phase detector frequencies are used.21 1C T _ C P O L 0

0 REFSTBY 0 Reference oscillator standby mode 0=XO is off in standby mode, 1=XO is on in standby mode

# Bit Name Default Function

15 CLK_DIV 0 1 Reference divider, divide by 2 (010 ) to 7 (111) when reference divider is enabled

12 CLK_DIV_BYPASS 1 Reference divider enabled=0, divider bypass (divide by 1)=1

11 XO_CT 1 8 Crystal oscillator coarse tune (approximately 0.5pF steps from 8pF to 16pF) 10 0

7 XO_I2 0 0 Crystal oscillator current setting

6 XO_I1 0

5 XO_CR_S 0 Crystal oscillator additional fixed capacitance (approximately 0.25pF)

4 TCT 0 Duration of coarse tune acquisition

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . CFG5 (O4h) - LO Bias CFG6 (O5h) - Start-up Timer # Bit Name Default Function

15 LO1_I 0 0 Local oscillator Path1 current setting

11 LO2_I 0 0 Local oscillator Path2 current setting

7 T_PH_ALGN 0 0 Phase alignment timer

# Bit Name Default Function 15 SU_WAIT 0 0 Crystal oscillator settling timer. 14 0 13 0 12 0 11 0 1 10 0 70 0 30 0

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL1x0 (08h) - VCO, LO Divider and Calibration Select PLL1x1 (09h) - MSB of Fractional Divider Ratio # Bit Name Default Function

15 P1_VCOSEL 0 7 Path 1 VCO band select: 00=VCO1, 0 1=VCO2, 1 0=VCO3, 11=Reserved

13 P1_CT_EN 1 Path 1 VCO coarse tune: 00=disabled, 11=enabled

11 P1_KV_EN 0 1 Path 1 VCO tuning gain ca libration: 00=disabled, 11=enabled

9 P1_LODIV 0 Path 1 local oscillator divider: 00=divide by 1, 0 1=divide by 2, 1 0=divide by 4, 11=reserved 70 1

5 P1_CP_DEF 0 Charge pump current setting

If P1_KV_EN=11 this value sets charge pump current during KV compensation only41 31 F # Bit Name Default Function

15 P1_NUM_MSB 0 6 Path 1 VCO divider numerator value, most significant 16 bits

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL1x2 (0Ah) - LSB of Fractional Divider Ratio and CT Default PLL1x3 (0Bh) - Integer Divider Ratio and VCO Current # Bit Name Default Function

15 P1_NUM_LSB 0 2 Path 1 VCO divider numerator value, least significant 8 bits

7 P1_CT_DEF 0 7 Path 1 VCO coarse tuning value, used when P1_CT_EN=00

# Bit Name Default Function

15 P1_N 0 2 Path 1 VCO divider integer value

2 0 Path 1 VCO bias setting: 000=minimum value, 111=maximum value

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL1x4 (0Ch) - Calibration Settings PLL1x5 (0Dh) - More Calibration Settings # Bit Name Default Function

15 P1_DN 0 1 Path 1 frequency step size used in VCO tuning gain calibration

6 P1_CT_GAIN 1 Path 1 coarse tuning calibration gain

3 P1_KV_GAIN 0 4 Path 1 VCO tuning gain calibration gain

# Bit Name Default Function

15 P1_N_PHS_ADJ 0 0 Path 1 frequency step size used in VCO tuning gain calibration

4 P1_CT_V 1 Path 1 course tuning voltage setting when performing course tuning calibration. Default value is 16. Change to 12 when using VCO1 for frequencies above 2.2GHz.30 0

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL2x0 (10h) - VCO, LO Divider and Calibration Select PLL2x1 (11h) - MSB of Fractional Divider Ratio # Bit Name Default Function

15 P2_VCOSEL 0 7 Path 2 VCO band select: 00=VCO1, 0 1=VCO2, 1 0=VCO3, 11=Reserved

13 P2_CT_EN 1 Path 2 VCO coarse tune: 00=disabled, 11=enabled

11 P2_KV_EN 0 1 Path 2 VCO tuning gain ca libration: 00=disabled, 11=enabled

9 P2_LODIV 0 Path 2 local oscillator divider: 00=divide by 1, 0 1=divide by 2, 1 0=divide by 4, 11=reserved 5 P2_CP_DEF 0 Charge pump current setting. If P2_KV_EN=11 this value sets charge pump current during KV compensation only41 31 F # Bit Name Default Function

15 P2_NUM_MSB 0 6 Path 2 VCO divider numerator value, most significant 16 bits

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL2x2 (12h) - LSB of Fractional Divider Ratio and CT Default PLL2x3 (13h) - Integer Divider Ratio and VCO Current # Bit Name Default Function 15 P2_NUM_LSB 0 2 Path 2 VCO divider numerator value, least significant 8 bits. 14 0 13 1 12 0 11 0 7 10 1

7 P2_CT_DEF 0 7 Path 2 VCO coarse tuning value, used when P2_CT_EN=00

# Bit Name Default Function

15 P2_N 0 2 Path 2 VCO divider integer value

2 P2_VCOI 0 Path 1 VCO bias setting: 000=minimum value, 111=maximum value

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . PLL2x4 (14h) - Calibration Settings PLL2x5 (15h) - More Calibration Settings # Bit Name Default Function

15 P2_DN 0 1 Path 2 frequency step size used in VCO tuning gain calibration

6 P2_CT_GAIN 1 Path 2 coarse tuning calibration gain

3 P2_KV_GAIN 0 4 Path 2 VCO tuning gain calibration gain

# Bit Name Default Function

15 P2_N_PHS_ADJ 0 0 Path 2 synthesizer phase adjustment

4 P2_CT_V 1 Path 2 course tuning voltage setting when performing course tuning calibration. Default value is 16. Change to 12 when using VCO1 for frequencies above 2.2GHz.30 0

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . GPO (18h) - Internal Control Output Settings CHIPREV (19h) - Chip Revision Information # Bit Name Default Function 15 0 0

14 P1_GPO1 0 Setting of GPO1 when path 1 is active, used internally only

12 P1_GPO3 0 Setting of GPO3 when path 1 is active, used internally only

11 P1_GPO4 0 0 Setting of GPO4 when path 1 is active, used internally only

6 P2_GPO1 0 Setting of GPO1 when path 2 is active, used internally only

4 P2_GPO3 0 Setting of GPO3 when path 2 is active, used internally only

3 P2_GPO4 0 0 Setting of GPO4 when path 2 is active, used internally only

# Bit Name Default Function 1 5 P A R T N O 00R F M D P a r t n u m b e r f o r d e v i c e 14 0 13 0 12 0 11 0 0 10 0

7 REVNO X X Part revision number

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . RB1 (1Ch) - PLL Lock and Calibration Results Read-back RB2 (1Dh) - Calibration Results Read-Back # Bit Name Default Function

15 LOCK X X PLL lock detector, 0=PLL locked, 1=PLL unlocked

14 CT_CAL X CT setting (either result of course tune calibration, or CT_DEF, depending on state of CT_EN). Also depends on the MODE of the device13 X 12 X

11 X X

7 CP_CAL X X CP setting (either result of KV cal, or CP_DEF, depending on state of KV_EN). Also depends on the MODE of the device6X 3X X # Bit Name Default Function

15 VO_CAL X X The VCO voltage measured at the start of a VCO gain calibration

7 V1_CAL X X The VCO voltage measured at the end of a VCO gain calibration

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . RB3 (1Eh) - PLL state Read-Back TEST (1Fh) - Test Modes # Bit Name Default Function

15 RSM_STATE X X State of the radio state machine

# Bit Name Default Function 1 5 T E N 00E n a b l e s t e s t m o d e

14 TMUX 0 Sets test multiplexer state

11 CPU 0 0 Set charge pump to pump up, 0=normal operation 1=pump down

10 CPD 0 Set charge pump to pump down, 0=normal operation 1=pump down

9 FNZ 0 0=normal operation, 1=fractional divider modulator disabled

8 LDO_BYP 0 On chip low drop out regulator bypassed

4 DACTEST 0 DAC test

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Evaluation Board The following diagrams show the schematic and PCB layout of the RF2052 evaluation board.The standard evaluation board has been configured for wideband operation. Application note s have been produced showing how the device is matched and on balun implementations for narrowband applications. The evalua tion board is provided as part of a design kit (DK2052), along with the necessary cables and programming software tool to enable full evaluation of the RF2052. Evaluation Board Schematic 12 k 470 pF 22 pF R20 0 R R19 DNI 820 R C10 330 pF 820 R C17 330 pF Loop Filter 2527 2630 29 283132 9 1110 141312 15 16 51 k 77 strip 77 strip 33 pF C34 10 nF VDDA C35 33 pF ENBL DNI CP_OP LFILT2 DNI VTUNE C36 33 pF MODE C16 DNI GND GND

226 MHz XTAL

0 R 50 strip J2

0 R 50 strip J1

100 k CB2 CB4 CTS# DSR# UIO CB0 CB1 VCC RST# VDD CB3 PU1 PU2 VCC USB SLD Socket for USB Interface 13 14 15 16 17 18 19 20 21 22 23 24 HDR_2X12 1211 109 VDD VDD SCLK ENX RESETB VDDA ENBL SDATA VTUNE CP_OP VDDD MODE C12 10 uF C11 10 uF LFILT1 LFILT2 LFILT3 LFILT1 LFILT3 Component Designator 60 kHz Active Loop Filter (As Fitted on Evaluation Board) 60 kHz Passive Loop Filter (Alternative Configuration) R3 12 k 12 k C9 470 pF 560 pF C8 22 pF 39 pF R19 DNI 3.9 k R20 0  DNI R2 820  0  C10 330 pF 0  R6 820  DNI C17 330 pF 120 pF Loop Filter Component Values

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Evaluation Board Layout Board Size 2.5”x2.5” Board Thickness 0.040”, Board Material FR-4

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com .

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com . Package Drawing QFN, 32-Pin, 5mmx5mm Support and Applications Information Application notes and support material can be downloaded from the product web page: www.rfmd.com/rf205x.

Ordering Information

Part Number Package Quantity RF2052 32-Pin QFN 25pcs sample bag RF2052SB 32-Pin QFN 5pcs sample bag RF2052SR 32-Pin QFN 100pcs reel RF2052TR13 32-Pin QFN 2500pcs reel DK2052 Complete Design Kit 1 box 0.08 C 0.1 C -C- 0.85±0.10 Detail ‘D’ Rotated CW Shaded area indicates pin 1. Dimensions in mm. 0.00 0.05 SEATING PLANE -A- -B- 5.00 5.000 3.70±0.10 0.1 CM A B 0.25 Typ. 0.1 CM A B0.23±0.05 32x 0.1 C 0.85±0.10 SEE DETAIL ‘D’ See Detail ‘D’ 0.35±0.05 32x 0.50 Typ.