R1LV0108E RENESAS | Alldatasheet
Document overview
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- PDF pages: 17
Technical content
Features
- Single 2.7~3.6V power supply
- Small stand-by current: 1µA (3.0V, typical)
- No clocks, No refresh
- All inputs and outputs are TTL compatible.
- Easy memory expansion by CS1# and CS2
- Common Data I/O
- Three-state outputs: OR-tie Capability
- OE# prevents data contention on the I/O bus R10DS0049EJ0200 Rev.2.00 2011.01.14
R10DS0049EJ0200 Rev.2.00 Page 2 of 15 2011.01.14
Ordering Information
Orderable Part Name Access time Temperature Range Package Shipping Container Quantity R1LV0108ESP-5SR#B0 0 ~ +70°C R1LV0108ESP-5SI#B0 55 ns -40 ~ +85°C R1LV0108ESP-7SR#B0 0 ~ +70°C R1LV0108ESP-7SI#B0 70 ns -40 ~ +85°C Tube Max. 25pcs/Tube Max. 225pcs/Inner Bag Max. 900pcs/Inner Box R1LV0108ESP-5SR#S0 0 ~ +70°C R1LV0108ESP-5SI#S0 55 ns -40 ~ +85°C R1LV0108ESP-7SR#S0 0 ~ +70°C R1LV0108ESP-7SI#S0 70 ns -40 ~ +85°C 525-mil 32-pin plastic SOP PRSP0032DA-A (32P2M-A) Embossed tape 1000pcs/Reel R1LV0108ESA-5SR#B0 0 ~ +70°C R1LV0108ESA-5SI#B0 55 ns -40 ~ +85°C R1LV0108ESA-7SR#B0 0 ~ +70°C R1LV0108ESA-7SI#B0 70 ns -40 ~ +85°C Tray Max. 234pcs/Tray Max. 1872pcs/Inner Box R1LV0108ESA-5SR#S0 0 ~ +70°C R1LV0108ESA-5SI#S0 55 ns -40 ~ +85°C R1LV0108ESA-7SR#S0 0 ~ +70°C R1LV0108ESA-7SI#S0 70 ns -40 ~ +85°C 8mm×13.4mm 32-pin plastic sTSOP (normal-bend type) PTSA0032KB-A (32P3K-B) Embossed tape 1000pcs/Reel R1LV0108ESF-5SR#B0 0 ~ +70°C R1LV0108ESF-5SI#B0 55 ns -40 ~ +85°C R1LV0108ESF-7SR#B0 0 ~ +70°C R1LV0108ESF-7SI#B0 70 ns -40 ~ +85°C Tray Max. 156pcs/Tray Max. 1248pcs/Inner Box R1LV0108ESF-5SR#S0 0 ~ +70°C R1LV0108ESF-5SI#S0 55 ns -40 ~ +85°C R1LV0108ESF-7SR#S0 0 ~ +70°C R1LV0108ESF-7SI#S0 70 ns -40 ~ +85°C 8mm×20mm 32-pin plastic TSOP (normal-bend type) PTSA0032KA-A (32P3H-E) Embossed tape 1000pcs/Reel
R10DS0049EJ0200 Rev.2.00 Page 3 of 15 2011.01.14 Pin Arrangement NC A16 A14 A12 DQ0 DQ1 DQ2 GND Vcc A15 CS2 WE# A13 A11 OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 32-pin SOP A11 A13 WE# CS2 A15 Vcc NC A16 A14 A12 OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 32-pin sTSOP A11 A13 WE# CS2 A15 Vcc NC A16 A14 A12 OE# A10 CS1# DQ7 DQ6 DQ5 DQ4 DQ3 GND DQ2 DQ1 DQ0 32-pin TSOP (normal-bend)
R10DS0049EJ0200 Rev.2.00 Page 4 of 15 2011.01.14 Pin Description Pin name Function Vcc Power supply Vss Ground A0 to A16 Address input DQ0 to DQ7 Data input/output CS1# Chip select 1 CS2 Chip select 2 WE# Write enable OE# Output enable NC Non connection
R10DS0049EJ0200 Rev.2.00 Page 5 of 15 2011.01.14 Block Diagram CS1# WE# OE# A16 DQ0 DQ1 DQ7 Vcc Vss COLUMN DECODER DQ BUFFER ADDRESS BUFFER ROW DECODER SENSE / WRITE AMPLIFIER CLOCK GENERATOR MEMORY ARRAY 128k-word x8-bit CS2
R10DS0049EJ0200 Rev.2.00 Page 6 of 15 2011.01.14 Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read L H H H High-Z Output disable Note 1. H: V IH L : VIL X : VIH or VIL Absolute Maximum Parameter Symbol Value unit Power supply voltage relative to Vss Vcc -0.3 to +4.6 V Terminal voltage on any pin relative to Vss V T -0.3 *1 to Vcc+0.3*2 V Power dissipation PT 0.7 W R Ver. 0 to +70 Operation temperature Topr*3 I Ver. -40 to +85 °C Storage temperature range Tstg -65 to 150 °C R Ver. 0 to +70 Storage temperature range under bias Tbias*3 I Ver. -40 to +85 °C Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Maximum voltage is +4.6V. 3. Ambient temperature range depends on R/I-version. Please see table on page 1.
R10DS0049EJ0200 Rev.2.00 Page 7 of 15 2011.01.14 DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Note Vcc 2.7 3.0 3.6 V Supply voltage Vss 0 0 0 V Input high voltage VIH 2.0 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.6 V 1 R Ver. 0 - +70 °C 2 Ambient temperature range I Ver. Ta -40 - +85 °C 2 Note 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1. DC Characteristics Parameter Symbol Min. Typ. Max. Unit Test conditions Input leakage current | ILI | - - 1 μA Vin = Vss to Vcc Output leakage current | ILO | - - 1 μA CS1# =VIH or CS2 =VIL or OE# =VIH, VI/O =Vss to Vcc ICC1 - 15 25 mA Min. cycle, duty =100%, II/O = 0mA CS1# =VIL, CS2 =VIH, Others = VIH/VIL Average operating current ICC2 - 2 5 mA Cycle =1μs, duty =100%, II/O = 0mA CS1# ≤ 0.2V, CS2 ≥ Vcc-0.2V, VIH ≥ Vcc-0.2V, VIL ≤ 0.2V Standby current ISB - - 0.33 mA “CS2 =VIL“ or “CS2 = VIH and CS1# =VIH”, Others = Vss to Vcc - 1 *1 2 μA ~+25°C - - 3 μA ~+40°C - - 8 μA ~+70°C Standby current ISB1 - - 10 μA ~+85°C Vin = Vss to Vcc (1) CS2 ≤ 0.2 or (2) CS1# ≥ Vcc-0.2V, C S 2 ≥ Vcc-0.2V VOH 2.4 - - V I OH = -0.5mA Output high voltage VOH2 Vcc Output low voltage VOL - - 0.4 V I OL = 2mA Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (T a= 25ºC), and not 100% tested.
R10DS0049EJ0200 Rev.2.00 Page 8 of 15 2011.01.14 Capacitance Parameter Symbol Min. Typ. Max. Unit Test conditions Note Input capacitance C in - - 8 pF Vin =0V 1 Input / output capacitance C I/O - - 10 pF V I/O =0V 1 Note 1. This parameter is sampled and not 100% tested. 2. Ambient temperature range depends on R/I-version. Please see table on page 1. AC Characteristics Test Conditions (Vcc = 2.7V ~ 3.6V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)
- Input pulse levels: VIL = 0.4V, VIH = 2.2V
- Input rise and fall time: 5ns
- Input and output timing reference level: 1.5V
- Output load: See figures (Including scope and jig) Note 1. Ambient temperature range depends on R/I-version. Please see table on page 1. DQ 1.5V RL = 500 ohm CL = 30 pF
R10DS0049EJ0200 Rev.2.00 Page 9 of 15 2011.01.14 Read Cycle R1LV0108E**-5S* R1LV0108E**-7S* Parameter Symbol Min. Max. Min. Max. Unit Note Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns tACS1 - 55 - 70 ns Chip select access time tACS2 - 55 - 70 ns Output enable to output valid tOE - 30 - 35 ns Output hold from address change t OH 5 - 10 - ns tCLZ1 5 - 10 - ns 2,3 Chip select to output in low-Z tCLZ2 5 - 10 - ns 2,3 Output enable to output in low-Z tOLZ 5 - 5 - ns 2,3 tCHZ1 0 20 0 25 ns 1,2,3 Chip deselect to output in high-Z tCHZ2 0 20 0 25 ns 1,2,3 Output disable to output in high-Z t OHZ 0 20 0 25 ns 1,2,3
R10DS0049EJ0200 Rev.2.00 Page 10 of 15 2011.01.14 Write Cycle R1LV0108E**-5S* R1LV0108E**-7S* Parameter Symbol Min. Max. Min. Max. Unit Note Write cycle time tWC 55 - 70 - ns Address valid to end of write tAW 50 - 55 - ns Chip select to end of write tCW 50 - 55 - ns 5 Write pulse width tWP 45 - 50 - ns 4 Address setup time tAS 0 - 0 - ns 6 Write recovery time tWR 0 - 0 - ns 7 Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns Output enable from end of write tOW 5 - 5 - ns 2 Output disable to output in high-Z tOHZ 0 20 0 25 ns 1,2 Write to output in high-Z tWHZ 0 20 0 25 ns 1,2 Note 1. t CHZ, tOHZ and tWHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. This parameter is sampled and not 100% tested. 3. At any given temperat ure and voltage condition, tHZ max is less than t LZ min both for a given device and from device to device. 4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE#. A write begins at the latest transition among CS1# going low, CS2 going high and WE# going low. A write ends at the earliest transition among CS1# going high, CS2 going low and WE# going high. tWP is measured from the beginning of write to the end of write. 5. t CW is measured from the later of CS1# going low or CS2 going high to end of write. 6. t AS is measured the address valid to the beginning of write. 7. t WR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle. 8. Don’t apply inverted phase signal externally when DQ pin is output mode.
R10DS0049EJ0200 Rev.2.00 Page 11 of 15 2011.01.14 Timing Waveforms Read Cycle tAA CS1# A0~16 tOH tCLZ1 tACS1 tOE tOLZ tCHZ1 OE# WE# DQ0~7 VIH tOHZ High impedance WE# = “H” level tRC Valid Data CS2 tCLZ2 tACS2 tCHZ2
R10DS0049EJ0200 Rev.2.00 Page 12 of 15 2011.01.14 Write Cycle (1) (WE# CLOCK) CS1# tCW tOW tWC DQ0~7 tDW tDH Valid Data tOHZ OE# WE# tAW tAS tWP tWR tWHZ tOLZ A0~16 CS2 tCW
R10DS0049EJ0200 Rev.2.00 Page 13 of 15 2011.01.14 Write Cycle (2) (CS1#, CS2 CLOCK) CS1# A0~16 tCW tWC tAW tAS tWR OE# WE# DQ0~7 VIH OE# = “H” level tDW tDH tWP Valid Data CS2 tCW t WRtAS
R10DS0049EJ0200 Rev.2.00 Page 14 of 15 2011.01.14 Low Vcc Data Retention Characteristics Parameter Symbol Min. Typ. Max. Unit Test conditions*2 VCC for data retention VDR 2.0 - 3.6 V Vin ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - 1 *1 2 μA ~+25°C - - 3 μA ~+40°C - - 8 μA ~+70°C Data retention current I CCDR - - 10 μA ~+85°C Vcc=3.0V, Vin ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V Chip deselect to data retention time t CDR 0 - - ns Operation recovery time tR 5 - - ms See retention waveform. Note 1. Typical parameter indicates the value for the center of distribution at 3.0V (T a= 25ºC), and not 100% tested. 2. CS2 controls address buffer, WE# buffer, CS1# bu ffer, OE# buffer and Din buffer. If CS2 controls data retention mode, Vin levels (address, WE#, CS1#, OE#, DQ) can be in the high impedance state. If CS1# controls data retent ion mode, CS2 must be CS2 ≥ Vcc-0.2V or 0V ≤ CS2 ≤ 0.2V. The other input levels (address, WE# ,OE#, DQ) can be in the high impedance state.
R10DS0049EJ0200 Rev.2.00 Page 15 of 15 2011.01.14 Low Vcc Data Retention Timing Waveforms CS1# Vcc (1) CS1# Controlled tCDR t R 2.7V 2.7V 2.2V 2.2V VDR CS1# ≥ Vcc - 0.2V CS2 Vcc (2) CS2 Controlled tCDR t R 2.7V 2.7V 0.2V 0.2V VDR 0V ≤ CS2 ≤ 0.2V
All trademarks and registered trademarks are the property of their respective owners. Revision History R1LV0108E Series Data Sheet
Description
Rev. Date Page Summary 1.00 2010.12.27 - First Edition issued 2.00 2011.01.14 2 Ordering Information is revised
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