PS12014-A

PS12014-A POWEREX | Alldatasheet

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 4-φ4 8.5 (7.75) 2 – 0.3 92.5 – 1 2.45 – 0.3 83.5 – 0.5 6 – 0.3 56 – 0.8 71.5 – 0.5 80.5 – 1 0.6 0.5 78.75 1.2 31 32 34 35 36 4-R4 LABEL 0.5 2.5 231 76.5 – 1 20.4 – 1 50.8 – 0.8 27 – 1 10.16 – 0.3 (10.35)

1 CBU+

2 CBU–

3 CBV+

4 CBV–

5 CBW+

6 CBW–

7 GND

8 VDL

9 VDH

11 FO1

12 FO2

13 FO3

Terminals Assignment: PS12014-A PACKAGE OUTLINES MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLAT-BASE TYPE INSULATED TYPE (Fig. 1) INTEGRATED FUNCTIONS AND FEATURES

• 3-Phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability Io (Note 1) : APPLICATION Acoustic noise-less 0.75kW/AC400V Class 3 Phase inverter and other motor control appli- cations. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs : Drive circuit, High-speed photo-couplers, Short circuit protection (SC), Bootstrap circuit supply scheme (Single drive power supply ) and Under-voltage protection (UV).
• For N-Side IGBTs :Drive circuit, Short-circuit protection (SC), Control supply Under voltage and Over voltage protection (OV/UV), System Over temperature protection (OT), Fault output signaling circuit (Fo), and Current-Limit warning signal out- put (CL).
• For Brake circuit IGBT : Drive circuit.
• Warning and Fault signaling : F O1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV) FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase current (3f).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection. T ype Name PS12014-A 100% load 3.4A (rms) 150% over load 5.1A (rms), 1min (Note 1) : The inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : Iop = Io 5 Ö‘2

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 CBU– CBU+ CBV– CBV+ CBW– CBW+ GND VDL VDH Fo Logic Application Specific Intelligent Power Module CU CV CW CL,FO 1,FO2,FO3U P VP W P VN W N BrU N B P Protection Circuit Photo Coupler Input Circuit Drive Circuit Drive Circuit Input signal conditioning Current sensing circuit Protection circuit Control supply fault sense R S T Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit may become necessary depending on the application environment]. CZ N MW AC 400V class line output V U Brake resistor connection, AC 400V class line input Inrush prevention circuit, etc. T S Analogue signal output corresponding to each phase current (5V line) Note 1) PWM input (5V line) Note 2) Note 1) To prevent chances of signal oscillation, a series resistor (1kΩ ) coupling at each output is recommended. Note 2) By virtue of integrating a photo-coupler inside the module, direct coupling to CPU, without any extemal opto or transformer isolation is possible. Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC power input pins. Fault output (5V line) Note 3) INTERNAL FUNCTIONS BLOCK DIAGRAM (Fig. 2) –Ic(–Icp) Ic(Icp) IF(IFP) V V V 900 1000 1200 Applied between P-N Applied between P-N, Surge-value Applied between P-U, V , W, Br or U, V , W , Br-N Supply voltage Supply voltage (surge) Each output IGBT collector-emitter static voltage ConditionSymbol Item Ratings Unit VCC VCC(surge) VP or VN MAXIMUM RATINGS (Tj = 25°C) INVERTER PART (Including Brake Part) VP(S) or VN(S) Each output IGBT collector-emitter surge voltage Each output IGBT collector current Brake IGBT collector current Brake diode anode current Applied between P-U, V , W, Br or U, V , W , Br-N TC = 25°C Note : “( )” means IC peak value 1200 –10 (–20) 5 (10) 5 (10) V A A A VCIN VFO IFO VCL ICL ICO V7Applied between VDL-GNDSupply voltageVDL Symbol Item Ratings Unit CONTROL PART Condition Input signal voltage Fault output supply voltage Fault output current Current-limit warning output voltage CL output current Analogue-current-signal output current –0.5 ~ VDL+0.5 V V mA V mA mA Applied between UP · VP · WP · UN · VN · W N · Br-GND Applied between FO1 · FO2 · FO3 -GND Sink current of FO1 · FO2 · FO3 Applied between CL-GND Sink current of CL Sink current of CU · CV · CW –0.5 ~ 7 –0.5 ~ 7 VDH , VDB Supply voltage V20Applied between VDH -GND, CBU+ -CBU– , C BV+ -CBV– , CBW+ -CBW–

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 TC ConditionSymbol Item Ratings Unit (Note 2) (Fig. 3)

60 Hz sinusoidal AC for 1 minute, between all terminals

and base plate. Mounting screw: M3.5 Tj Tstg TC VISO Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.78 ~ 1.27 Vrms N·m TOTAL SYSTEM Note 2) : The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. However, these power elements can endure instantaneous junction temperature as high as 150°C. T o make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is to be provided before use. CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface) (Fig. 3) °C/W °C/W °C/W °C/W °C/W Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Case to fin, thermal grease applied (1 Module) Junction to case Thermal Resistance Contact Thermal Resistance R th(jc)Q R th(jc)F R th(jc)QB R th(jc)FB R th(c-f) ConditionSymbol Item Ratings Min. THERMAL RESISTANCE Typ. Max. 2.0 5.5 3.0 7.3 0.040 Unit mA mA V V kW 150 2.0 4.0 1.4 3.0 150 0.8 2.5 V DH Circuit Current VDL Circuit Current Input on threshold voltage Input off threshold voltage Input pull-up resistor Min. V ms ms ms ms ms 3.5 2.0 1.4 4.0 1.6 1.2 0.5 2.2 0.9 0.2 I DH IDL Vth(on) Vth(off) R i VCC £ 800V, Input = ON (One-Shot) Tj = 125°C start 13.5V £ VDH = VDB = £ 16.5V VCC £ 800V , Tj £ 125°C, Ic < IOL (CL) operation level, Input = ON, 13.5V £ VDH = VDB = £ 16.5V VFBr ton tc(on) toff tc(off) trr VCE(sat) VEC VDL = 5V , VDH = VDB = 15V Input = ON, Tj = 25°C, Ic = 10A Tj = 25°C, Ic = –10A, Input = OFF ConditionSymbol Item Ratings Typ. Max. Unit

• No destruction
• FO output by protection operation ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V , VDB = 15V, VDL = 5V unless otherwise noted) Collector-emitter saturation voltage FWDi forward voltage Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage VCE(sat)Br Tj = 25°C, IF = 5A, Input = OFF VDL = 5V , VDH = 15V Input = ON, Tj = 25°C, Ic = 5A Switching times FWD reverse recovery time 1/2 Bridge inductive, Input = ON VCC = 600V, Ic = 10A, Tj = 125°C VDL = 5V, VDH = 15V , VDB = 15V Note : ton, toff include delay time of the internal control circuit. Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA VDL = 5V, VDH = 15V , VCIN = 5V VDL = 5V, VDH = 15V , VCIN = 5V 0.3 3.6 3.5 3.6 V V V
• No destruction
• No protecting operation
• No FO output Integrated between input terminal-VDH

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V , VDB = 15V, VDL = 5V unless otherwise noted) (Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen- tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri- ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its FO1 pin of the ASIPM indicating a short circuit situation. SC OT OTr UV DB UV DBr UV DH UV DHr OV DH OV DHr tdv IFO(H) IFO(L) ±IOL VDL = 5V, VDH = 15V , TC = –20 ~ 100°C (Note 4) td(read) ICL(H) ICL(L) VDH = 15V VDL = 5V TC = –20 ~ 100°C (Fig.4) tint VCO VC+(200%) VC–(200%) |ΔV CO | VC+ VC– Ratings Min. Trip level Reset level Trip level Reset level Trip level Reset level Trip level Reset level Filter time Over tenperature protection Signal output cur- rent of CL operation Ic = 0A Ic = I OP(200%) Ic = –IOP(200%) Allowable input signal dead time for blocking arm shoot-through TC ≤ 100°C, Tj ≤ 125°C VDH = 15V, VDL = 5V, TC = –20°C ~ +100°C Note 3) Relates to corresponding inputs (Except brake part) Relates to corresponding inputs (Except brake part) ConditionSymbol Item Typ. Max. Unit Input inter-lock sensing Offset change area vs temperature Idle Active Supply circuit under and over voltage protection Idle ActiveFault output current kHz µs tdead Analogue signal linearity with output current VDH = 15V, VDL = 5V, TC = –20 ~ 100°C Analogue signal output voltage limitIc > IOP(200%) , VDH = 15V , VDL = 5V (Fig. 4) Δ VC (200%) Analogue signal overall linear variation Analogue signal data hold accuracy |VCO -VC ±(200%)| rCH Correspond to max. 500µs data hold period only, Ic = IOP(200%) (Fig. 5) After input signal trigger point (Fig. 8) Open collector onput Tj = 25°C (Fig. 7), (Note 5) VDL = 5V, VDH = 15V Tj ≤ 125°C Open collector output 4.0 1.87 0.77 2.97 4.0 9.14 15.30 100 10.0 10.5 11.05 11.55 18.00 16.50 2.27 1.17 3.37 1.1 11.05 26.80 110 11.0 11.5 12.00 12.50 19.20 17.50 500 100 2.57 1.47 3.67 0.7 13.90 38.90 120 12.0 12.5 12.75 13.25 20.15 18.65 µs ns V V V mV V V V µs µA mA A A V V V V V V µs µA mA Analogue signal reading time CL warning operation level Short circuit current trip level f PWM txx PWM input frequency Allowable input on-pulse width V5.04.8VDL VDH , VDB 800 Control supply voltage —Applied between P-N Applied between VDH -GND, CBU+ -CBU– , CBV+ -CBV– , C BW+ -CBW– ConditionSymbol Item Ratings VCC Supply voltage Min. RECOMMENDED CONDITIONS Typ. Max. Unit Control supply voltage Applied between VDL -GND 13.5 600 15.0 16.5 5.2 V V Δ VDH , Δ VDB , Δ VDL VCIN(on) VCIN(off) fPWM tdead Using application circuit Using application circuit 4.8 4.0 0.3 V/µs V V kHz µs Supply voltage ripple Input ON voltage Input OFF voltage PWM Input frequency Arm shoot-through blocking time

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 SC delay time Short circuit sensing signal VS Error output FO1 Gate signal Vo of each phase upper arm(ASIPM internal) Input signal VCIN of each phase upper arm 0V 0VInput signal VCIN(p) of each phase upper arm Input signal VCIN(n) of each phase lower arm Gate signal Vo(p) of each phase upper arm (ASIPM internal) Gate signal Vo(n) of each phase upper arm (ASIPM internal) Error output FO1 VCH (5µs) V CH (505µs)0V VC 500µs rCH = VCH (505µs)-VCH (5µs) VCH (5µs) Note ; Ringing happens around the point where the signal output voltage changes state from “analogue” to “data hold” due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 µs delayed point. 200–200 Analogue output signal data hold range 4003001000–100–300–400 VC +(200%) VC0 VC –(200%) VC(V) VC+ VC – min max Real load current peak value.(%)(Ic=Io5 2) VDH =15V VDL=5V TC=–20~100˚C Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING “DA TA HOLD” DEFINITION Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART Note : Short circuit protection operation. The protection operates with “FO ” flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”). Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in “LOW” level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O ” signal is outputted. After an “input interlock” operation the circuit is latched. The “FO ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS12014-A FLA T-BASE TYPE INSULATED TYPE Jan. 2000 U P,VP,WP,UN ,VN ,WN ,Br FO1 ,FO2 ,FO3 ,CL CU,CV,CW GND(Logic) VDL (5V) ASIPM CPU 10kΩ 5.1kΩ 0.1nF R R 0.1nF on on on on 0VPNDC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO 1 output signal VDB VCIN(N) VCIN(P) VCIN(Br) FOI VDH, DL PWM starts N-side IGBT Current N-side FWDi Current t(hold) td(read) Delay time +ICL –ICL on off on off on off Ref VCIN V(hold) IC (VS) VC VCL Fig. 9 START-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to VDL voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT . This can happen particularly when the boot-strap capacitor is of large size. F O1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20ms number of pulses =10 ~ 500 de- pending on the boot-strap capacitor size) b) F O1 resetting sequence: Apply ON signals to the following input pins : Br fi Un/Vn/Wn fi Up/Vp/Wp in that order. Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART.