PS11017

PS11017 POWEREX | Alldatasheet

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MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2001 Some parametric limits are subject to change. LABEL Terminals Assignment: 115 – 1 8.5 10 10 15.5 15.5 2.5 105 – 0.5 63.5 – 0.8 17.5 (102) (22) 0.50.5 12.7 – 0.3 76 – 1 41 – 0.5 2 – 0.3 56 – 0.8 20.4 – 1 17 – 0.8 60 – 0.5 63 – 0.8 1 – 0.3 15.5 6 – 0.3 4-f5 4-R2 4-R5 4-f4.5 4-f3.2 MOUNTING HOLE1 7 23 31 36

1 CBU+

2 CBU–

3 CBV+

4 CBV–

5 CBW+

6 CBW–

7 GND

9 VDH

11 FO1

12 FO2

13 FO3

PS11017 INTEGRATED FUNCTIONS AND FEATURES

• 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technologies.
• Circuit for dynamic braking of motor regenerative energy.
• Inverter output current capability I O (Note 1): PACKAGE OUTLINES MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLAT-BASE TYPE INSULATED TYPE (Note 1) : The inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : I OP = IO × √ 2 (Fig. 1) Type Name PS11017 100% load 17.0A (rms) 150% over load 25.5A (rms), 1min APPLICATION Acoustic noise-less 3.7kW/AC200V class 3 phase inverter and other motor control applica- tions. INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For P-Side IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short-circuit protection (SC), Bootstrap circuit supply scheme (Single drive-power-supply) and Under voltage protection (UV).
• For N-Side IGBTs : Drive circuit, Short circuit protection (SC), Control-supply Under voltage and Over voltage protection (OV/UV), Sys- tem Over-temperature protection (OT), Fault output (FO ) signaling circuit, and Current-Limit warning signal output (CL)
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling : F O1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV) FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter phase current (3φ).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2001 Each output IGBT collector current Brake IGBT collector current Brake diode anode current INTERNAL FUNCTIONS BLOCK DIAGRAM (Fig. 2) V V 450 500 Applied between P-N Applied between P-N, Surge-value Applied between P-U, V , W, Br or U, V , W, Br-N Applied between P-U, V , W, Br or U, V , W, Br-N T C = 25°C Note: “( )” means IC peak value Supply voltage Supply voltage (surge) V CC VCC(surge) ConditionSymbol Item Ratings Unit MAXIMUM RATINGS (Tj = 25°C) INVERTER P ART (Including Brake Part) VP or VN VP(S) or VN(S) ±IC (±ICP ) IC (ICP ) IF(IFP) Each output IGBT collector-emitter static voltage Each output IGBT collector-emitter switching surge voltage 600 600 ±50 (±100) 15 (30) 15 (30) V V A A A VDH GND B P R S T C Z N M CBU– CBU+ CBV– CBV+ CBW– CBW+Application Specific Intelligent Power Module CU CV CW CL, FO1, FO2, FO3U P VP W P VN W N BrU N Protection circuit Control supply fault senseFo Logic Drive Circuit Input signal conditioning Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit may become necessary depending on the application environment]. W AC 200V line output V U AC 200V line input Brake resistor connection, Inrush prevention circuit, etc. Protection Circuit Level shifter Drive Circuit Current sensing circuit Note 1) To prevent chances of signal oscillation, a series resistor (1kW ) coupling at each output is recommended. Note 2) By virtue of integrating an photo-coupler inside the module, direct coupling to CPU, without any external opto or transformer isolation is possible. Note 3) All outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kW resistance. Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film snubber capacitor (0.1~0.22mF, high voltage type) is recommended to be mounted close to these P and N DC power input pins. Analogue signal output corresponding to each phase current (5V line) Note 1) PWM input (5V line) Note 2) Fault output (5V line) Note 3) T S V20Applied between VDH -GND, CBU+ -CBU– , C BV+ -CBV– , CBW+ -CBW– Applied between UP · VP · WP · UN · VN · W N · Br-GND Applied between FO1 · FO2 · FO3 -GND Sink current of FO1 · FO2 · FO3 Applied between CL-GND Sink current of CL Sink current of CU · CV · CW V DH , VDB Supply voltage Symbol Item Ratings Unit CONTROL PART Condition –0.5 ~ 7 –0.5 ~ 7 V V mA V mA mA V CIN V FO IFO V CL ICL ICO Input signal voltage Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current Analogue current signal output current –0.5 ~ 7.5

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2001 Tc LABEL 1.75 2.4 2.9 4.5 0.031 °C/W °C/W °C/W °C/W °C/W Junction to case Thermal Resistance Condition Symbol Item Ratings Unit (Note 2) (Fig. 3)

60 Hz sinusoidal AC applied between all terminals and

the base plate for 1 minute. Mounting screw: M4.0 T j Tstg TC Viso Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.98 ~ 1.47 Vrms N·m TOTAL SYSTEM Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How- ever, these power elements can endure instantaneous junction temperature as high as 150°C instantaneously . To make use of this ad- ditional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. Condition Symbol Item Ratings Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Case to fin, thermal grease applied Rth(j-c) Q Rth(j-c)F Rth(j-c)Q Rth(j-c)F Rth(c-f) Min. THERMAL RESISTANCE Typ. Max. Unit (Fig. 3) CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface) Contact Thermal Resistance Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resister Min. V FBr ton tc(on) toff tc(off) trr Collector-emitter saturation voltage FWDi forward voltage VCE(sat) VEC Ratings VDH = VDB = 15V , Input = ON, Tj = 25°C, Ic = 50A ConditionSymbol Item Typ. Max. Unit

• No destruction
• F O output by protection operation ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V , VDB = 15V unless otherwise noted) Tj = 25°C, Ic = –50A, Input = OFF IDH Vth(on) Vth(off) Ri
• No destruction
• No protecting operation
• No F O output VCE(sat)Br Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage VDH = 15V , Input = ON, Tj = 25°C, Ic = 15A Tj = 25°C, IF = 15A, Input = OFF Switching times 1/2 Bridge inductive, Input = ON V CC = 300V, Ic = 50A, Tj = 125°C VDH = 15V, VDB = 15V Note : ton, toff include delay time of the internal control circuitFWD reverse recovery time Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) V CC ≤ 400V, Input = ON (one-shot) Tj = 125°C start 13.5V ≤ VDH = VDB ≤ 16.5V VCC ≤ 400V , Tj ≤ 125°C, Ic < IOL (CL) operation level, Input = ON, 13.5V ≤ VDH = VDB ≤ 16.5V Switching SOA VDH = 15V, VCIN = 5V 0.8 2.5 Integrated between input terminal-VDH — 0.40 0.40 1.5 1.4 3.0 150 0.8 0.15 0.6 2.9 2.9 3.5 1.0 2.4 150 2.0 4.0 2.9 2.0 1.3 V V V V µs µs µs µs µs mA V V kΩ

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2001 10.0 16.50 18.00 11.55 t d(read) ICL(H) ICL(L) ±IOL SC OT OTr UV DH UV DHr OV DH OV DHr UV DB UV DBr tdV IFO(H) IFO(L) 0.77 txx ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted) 3.37 Idle Active T rip level Reset level T rip level Reset level T rip level Reset level T rip level Reset level Filter time Idle Active Ic = 0A Ic = I OP (200%) Ic = –IOP (200%) tint VCO V C+ (200%) V C–(200%) |ΔVCO | VC+ VC– ΔVC (200%) TC = –20 ~ +100°C, Tj ≤ 125°C VDH = 15V TC = –20°C ~ 100°C (Fig. 4) TC ≤ 100°C, Tj ≤ 125°C VDH = 15V , TC = –20°C ~ +100°C (Note 3) PWM input frequency ConditionSymbol Ratings fPWM Min. Typ. Max. Unit VDH = 15V , TC = –20°C ~ 100°C Ic > IOP (200%), VDH = 15V (Fig. 4) |VCO -VC ±(200%)| After input signal trigger point (Fig. 8) Fault output current Open collector output V D = 15V , TC = –20°C ~ 100°C (Note 4) Tj = 25°C (Fig. 7) (Note 5) Analogue signal over all linear variation Item tdead Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Relates to corresponding input (Except break part) Analogue signal linearity with output current Offset change area vs temperature Analogue signal output voltage limit r CH Analogue signal data hold accuracy Analogue signal reading time Correspond to max. 500µs data hold period only, Ic = I OP (200%) (Fig. 5) CL warning operation level Short circuit over current trip level 2.5 1.87 4.0 48.2 79.2 100 11.05 Open collector output — 2.27 1.17 1.1 60.0 102 110 11.0 12.00 12.50 19.20 500 100 2.57 1.47 3.67 0.7 72.0 120 12.0 12.5 12.75 13.25 20.15 18.65 kHz µs µs ns V V V mV V V V µs µA mA A A V V V V µs µA mA 17.50 Relates to corresponding inputs, (Except brake part), T C = –20°C ~ +100°C Input inter-lock sensing 2.97 Signal output current of CL operation — Over temperature protection Supply circuit under & over voltage protection 11.510.5 V V V DH = 15V (Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen- tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri- ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its F O1 pin of the ASIPM indicating a short circuit situation. Supply voltage ripple Input on voltage Input off voltage PWM Input frequency Arm shoot-through blocking time Supply voltage Δ VDH , ΔV DB VCIN(on) VCIN(off) fPWM tdead RECOMMENDED CONDITIONS V400 (max.)Applied across P-N terminals ConditionSymbol Item Ratings VCC Unit VDH , VDB Control Supply voltage Applied between VDH -GND, CBU+ -CBU– , CBV+ -CBV– , C BW+ -CBW– Using application circuit Using application circuit 15±1.5 ±1 (max.) 0 ~ 0.3 4.8 ~ 5.0 2 ~ 15 2.5 (min.) V V/µs V V kHz µs

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2001 SC delay time Short circuit sensing signal VS Error output FO1 Gate signal Vo of each phase upper arm(ASIPM internal) Input signal V CIN of each phase upper arm 0V 0VInput signal V CIN(p) of each phase upper arm Input signal VCIN(n) of each phase lower arm Gate signal Vo(p) of each phase upper arm (ASIPM internal) Gate signal V o(n) of each phase upper arm (ASIPM internal) Error output FO1 200 –200 Analogue output signal data hold range 400 300 100 0 –100 –300 –400 VC +(200%) VC0 VC –(200%) VC(V) VC+ VC – min max Real load current peak value.(%)(Ic=Io5 2) VDH =15V TC=–20~100˚C (Fig. 4) Fig. 4 OUTPUT CURRENT ANALOGUE SIG- NALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING “DATA HOLD” DEFINITION Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in “LOW” level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F O ” signal is outputted. After an “input interlock” operation the circuit is latched. The “FO ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION Note : Short circuit protection operation. The protection operates with “FO ” flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”). VCH (5ms) V CH (505ms)0V VC 500ms rCH = VCH (505ms)-VCH (5ms) VCH (5ms) Note ; Ringing happens around the point where the signal output voltage changes state from “analogue” to “data hold” due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 ms delayed point.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11017 FLA T-BASE TYPE INSULATED TYPE May 2 001 R U P,VP,WP,UN ,VN ,WN ,Br F01,F02,F03,CL CU,CV,CW GND(Logic) ASIPM CPU R5.1kW 10k W 0.1nF 0.1nF on on on on VPNDC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO 1 output signal VDB VCIN(N) VCIN(P) VCIN(Br) FOI VDH PWM starts N-side IGBT Current N-side FWDi Current t(hold) td(read) Delay time +ICL –ICL on off on off on off Ref VCIN V(hold) IC (VS) VC VCL Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART Fig. 10 RECOMMENDED I/O INTERFACE CIRCUITFig. 9 START-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, F O1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT . This can happen particularly when the boot-strap capacitor is of large size. F O1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for ad- equate charging (pulse width = approx. 20µs number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) F O1 resetting sequence: Apply ON signals to the following input pins : Br → Un/Vn/Wn → Up/Vp/Wp in that order.