PS11014

PS11014 POWEREX | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 6

Technical content

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan . 2000

1 CBU+

2 CBU–

3 CBV+

4 CBV–

5 CBW+

6 CBW–

7 GND

9 VDH

11 FO1

12 FO2

13 FO3

2 – 0.3 54 – 0.5 0.5 – 0.03 0.8 0~0.8 0~0.8 0.4 0.562 – 1 20.4 – 1 27 – 1 94.2 – 1 82 – 0.8 4-R2 2-R4 0.5 0.5 0.6 8.5 (16.25) 50 1 2 34 56 789 10 1112131415161718192021 23 31 32 33 34 35 36 37 38 39 40 Terminals Assignment: 2-φ4 1.2 LABEL 3.5 ] Control Pin top portion details ] Main terminal top portion details 0.3 – 0.5 12 0.6 0.35MAX – 0.5 PS11014 INTEGRATED FUNCTIONS AND FEATURES

• Converter bridge for 3 phase AC-to-DC power conversion.
• Circuit for dynamic braking of motor regenerative energy.
• 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology .
• Inverter output current capability IO (Note 1): APPLICATION Acoustic noise-less 0.75kW/AC200V class 3 phase inverter and other motor control appli- cations PACKAGE OUTLINES MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLAT-BASE TYPE INSULATED TYPE (Note 1) : The inverter output current is assumed to be sinu- soidal and the peak current value of each of the above loading cases is defined as : IOP = IO · Ö‘2 (Fig. 1) Type Name PS11014 100% load 5.0A (rms) 150% over load 7.5A (rms), 1min INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
• For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC). Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV).
• For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC). Control supply circuit under- & over- voltage protection (OV/UV). System over temperature protection (OT). Fault output signaling circuit (F O ) and Current limit warn- ing signal output (CL).
• For Brake circuit IGBT : Drive circuit
• Warning and Fault signaling : FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV). FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition
• For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3f).
• Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 Each output IGBT collector current Brake IGBT collector current Brake diode anode current INTERNAL FUNCTIONS BLOCK DIAGRAM (Fig. 2) V V 450 500 Applied between P2-N Applied between P2-N, Surge-value Applied between P-U, V, W, Br or U, V , W, Br-N Applied between P-U, V, W, Br or U, V , W, Br-N TC = 25°C Note: “( )” means IC peak value Supply voltage Supply voltage (surge) VCC VCC(surge) ConditionSymbol Item Ratings Unit MAXIMUM RATINGS (Tj = 25°C) INVERTER P ART (Including Brake Part) VP or VN VP(S) or VN(S) –IC (–ICP ) IC (ICP ) IF(IFP) Each output IGBT collector-emitter static voltage Each output IGBT collector-emitter switching surge voltage 600 600 –15 (–30) 4 (8) 4 (8) V V A A A V20 Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current Analogue current signal output current Applied between V DH -GND, CBU+ -CBU– , C BV+ -CBV– , CBW+ -CBW– Applied between UP · VP · WP · UN · VN · W N · Br-GND Applied between FO1 · FO2 · FO3 -GND Sink current of FO1 · FO2 · FO3 Applied between CL-GND Sink current of CL Sink current of CU · CV · CW V DH , VDB Supply voltage Symbol Item Ratings Unit CONTROL PART Condition VFO IFO VCL ICL ICO VCIN Input signal voltage –0.5 ~ 7.5 –0.5 ~ 7 –0.5 ~ 7 V V mA V mA mA 3f rectifying circuit 1 cycle at 60Hz, peak value non-repetitive Value for one cycle of surge current ConditionSymbol Item Ratings Unit VRRM Ea IO IFSM I2t Repetitive peak reverse voltage Recommended AC input voltage DC output current Surge (non-repetitive) forward current I 2t for fusing 800 220 196 160 V V A A A 2s CONVERTER P ART (15V line) VDHGND CUCVCW U P VP W P U N VN W N Br CL FO1 FO2 FO3 B R S T CZ N MW V U AC200V line input C3 ; 3.3µF or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change depending on the type PWM control scheme used in the applied system) C4 ; 2µF R-category ceramic condenser for noise filtering. C2 ; 3.3µF or more FO Logic Protection Circuit Level shifter Drive Circuit Drive Curcuit Trig signal conditioning Current sensing circuit Protection circuit Control supply fault sense Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit maybe necessary depending on the application environment]. AC 200V line output Brake resistor connection, Inrush prevention circuit, etc. Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10) Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10) Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1kΩ resistance. (see also Fig.10) Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22µF, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins. Analogue signal output corresponding to each phase current (5V line) Note 1) Each phase input (PWM) (5V line) Note 2) Fault output (5V line) Note 3) CBU– CBU+ CBV– CBV+ CBW– CBW+ C4,C3 Application Specific Intelligent Power Module T.S.

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan . 2000 TC 2.8 3.9 5.8 6.0 4.3 0.044 °C/W °C/W °C/W °C/W °C/W °C/W Junction to case Thermal Resistance Condition Symbol Item Ratings Unit (Note 2) (Fig. 3)

60 Hz sinusoidal AC applied between all terminals and

the base plate for 1 minute. Mounting screw: M3.5 Tj Tstg TC Viso Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque –20 ~ +125 –40 ~ +125 –20 ~ +100 2500 0.78 ~ 1.27 Vrms kg·cm TOTAL SYSTEM Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. How- ever, these power elements can endure junction temperature as high as 150°C instantaneously . T o make use of this additional tem- perature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use. ConditionSymbol Item Ratings Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Converter Di (1/6) Case to fin, thermal grease applied (1 Module) Rth(j-c) Q Rth(j-c)F Rth(j-c)QB Rth(j-c)FB Rth(j-c)FR Rth(c-f) Min. THERMAL RESISTANCE Typ. Max. Unit (Fig. 3) CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface) Contact Thermal Resistance —0.1 VCC £ 400V, Input = ON (one-shot) Tj = 125°C start 13.5V £ VDH = VDB £ 16.5V VCC £ 400V , Tj £ 125°C, Ic < IOL (CL) operation level, Input = ON 13.5V £ VDH = VDB £ 16.5V V V VFBr IRRM VFR ton tc(on) toff tc(off) trr Collector-emitter saturation voltage FWDi forward voltage Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage Converter diode reverse current Converter diode voltage Switching times FWD reverse recovery time VCE(sat) VEC Ratings VDH = VDB = 15V, Input = ON, Tj = 25°C, IC = 15A ConditionSymbol Item Min. Typ. Max. Unit

• No destruction
• FO output by protection operation ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V, VDB = 15V unless otherwise noted) Tj = 25°C, IC = –15A, Input = OFF
• No destruction
• No protecting operation
• No F O output VCE(sat)Br VDH = 15V, Input = ON, Tj = 25°C, IC = 4A Tj = 25°C, IF = 4A, Input = OFF VR = VRRM , Tj = 125°C Tj = 25°C, IF = 10A 1/2 Bridge inductive load, Input = ON VCC = 300V, Ic = 15A, Tj = 125°C VDH = 15V, VDB = 15V Note : ton, toff include delay time of the internal control circuit Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA 0.3 0.6 0.2 1.1 0.4 2.9 2.9 3.5 2.9 1.5 1.5 0.6 1.8 1.0 V V mA V ms ms ms ms ms

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 Applied across P2-N terminals 150— Trip level Reset level Trip level Reset level Trip level Reset level Trip level Reset level Filter time Idle Active td(read) –IOL ICL(H) ICL(L) SC OT OTr UV DH UV DHr OV DH OV DHr UV DB UV DBr tdV IFO(H) IFO(L) tint VCO V C+ (200%) V C–(200%) |DVCO | VC+ VC– DVC (200%) Ic = 0A Ic = IOP (200%) Ic = –IOP (200%) Input on threshold voltage Input off threshold voltage Input pull-up resistor 1.87 0.77 2.97 4.0 23.2 100 11.05 11.55 18.00 16.50 10.0 10.5 T C = –20°C ~ +100°C Tj £ 125°C 43.0 110 12.00 12.50 19.20 17.50 11.0 11.5 VDH = 15V (Fig. 4) 0.8 2.5 Integrated between input terminal-VDH TC £ 100°C, Tj £ 125°C VDH = 15V, TC = –20°C ~ +100°C (Note 3) Relates to corresponding input (Except brake part) TC = –20°C ~ +100°C Relates to corresponding input (Except brake part) ConditionSymbol Ratings Vth(on) Vth(off) R i fPWM txx Min. Max. Unit ELECTRICAL CHARACTERISTICS (Tj = 25°C, VDH = 15V , VDB = 15V unless otherwise noted) (Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momen- tarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropri- ately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its FO1 pin of the ASIPM indicating a short circuit situation. Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Input inter-lock sensing Analogue signal linearity with output current Offset change area vs temperature VDH = 15V, TC = –20°C ~ +100°C Ic > IOP (200%), VDH = 15V (Fig. 4) Analogue signal output voltage limit |VCO -VC –(200%)|Analogue signal over all linear variation Analogue signal data hold accuracy After input signal trigger point (Fig. 8)Analogue signal reading time Current limit warning (CL) operation level VDH =15V Open collector output 2.2 14.05 Open collector output 1.4 3.0 150 2.27 1.17 3.37 1.1 17.30 62.0 120 12.75 13.25 20.15 18.65 12.0 12.5 2.0 4.0 500 100 2.57 1.47 3.67 0.7 20.80 mA mA A V V V V V V ms mA mA V V kW kHz ms ms ns V V V mV V V V ms A PWM input frequency VDH =15V, TC = –20°C ~ +100°C (Note 4) Item tdead Correspond to max. 500ms data hold period only, Ic = IOP (200%) (Fig. 5)rCH Short circuit over current trip level Signal output current of CL operation Idle Active Tj = 25°C (Fig. 7) (Note 5) Supply circuit under & over voltage protection Over temperature protection Fault output current IDH Circuit current VDH = 15V , VCIN = 5V —m A Typ. D VDH , DV DB VCIN(on) VCIN(off) fPWM tdead RECOMMENDED CONDITIONS V400 (max.) ConditionSymbol Item Ratings VCC Supply voltage Unit VDH , VDB Control supply voltage Supply voltage ripple Input on voltage Input off voltage PWM Input frequency Arm shoot-through blocking time Applied between VDH -GND, CBU+ -CBU– , CBV+ -CBV– , C BW+ -CBW– Using application circuit Using application circuit 15–1.5 –1 (max.) 0 ~ 0.3 4.8 ~ 5.0 2 ~ 20 2.2 (min.) V V/ms V V kHz ms

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan . 2000 SC delay time Short circuit sensing signal VS Error output FO1 Gate signal Vo of each phase upper arm(ASIPM internal) Input signal VCIN of each phase upper arm 0V 0VInput signal VCIN(p) of each phase upper arm Input signal VCIN(n) of each phase lower arm Gate signal Vo(p) of each phase upper arm (ASIPM internal) Gate signal Vo(n) of each phase upper arm (ASIPM internal) Error output FO1 VCH (5µs) V CH (505µs)0V VC 500µs rCH = VCH (505µs)-VCH (5µs) VCH (5µs) Note ; Ringing happens around the point where the signal output voltage changes state from “analogue” to “data hold” due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 µs delayed point. 200–200 Analogue output signal data hold range 4003001000–100–300–400 VC +(200%) VC0 VC –(200%) VC(V) VC+ VC – min max Real load current peak value.(%)(Ic=Io5 2) VDH =15V TC=–20~100˚C (Fig. 4) Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta- neously in “LOW” level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “FO ” signal is outputted. After an “input interlock” operation the circuit is latched. The “FO ” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later. Note : Short circuit protection operation. The protection operates with “FO ” flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”). Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING “DATA HOLD” DEFINITION Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION

MITSUBISHI SEMICONDUCTOR <Application Specific Intelligent Power Module> PS11014 FLA T-BASE TYPE INSULATED TYPE Jan. 2000 R U P,VP,WP,UN ,VN ,WN ,Br F01,F02,F03,CL CU,CV,CW GND(Logic) ASIPM CPU R5.1kΩ 10k Ω 0.1nF0.1nF on on on on 0VPNDC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO 1 output signal VDB VCIN(N) VCIN(P) VCIN(Br) FOI VDH PWM starts N-side IGBT Current N-side FWDi Current t(hold) td(read) Delay time +ICL –ICL on off on off on off Ref VCIN V(hold) IC (VS) VC VCL Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART Fig. 10 RECOMMENDED I/O INTERFACE CIRCUITFig. 9 START-UP SEQUENCE Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT . This can happen particularly when the boot-strap capacitor is of large size. F O1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for ad- equate charging (pulse width = approx. 20ms number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) F O1 resetting sequence: Apply ON signals to the following input pins : Br fi Un/Vn/Wn fi Up/Vp/Wp in that order.