PLC810PG POWERINT | Alldatasheet
Document overview
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- PDF pages: 26
Technical content
Features
- Highly integrated, eliminates external components
- Frequency and phase synchronized PFC and LLC
- Reduced noise and EMI
- Ripple current reduction in PFC output capacitor
- Edge collision-avoidance simplifies layout
- Comprehensive PFC and LLC fault handling and current limiting
- Proprietary continuous conduction mode PFC for high efficiency with low component cost
- High efficiency Zero Voltage Switching (ZVS) LLC
- Off-time PFC control eliminates AC input sensing components
- Configurable, precise dead time control and frequency limit
- Prevents hard MOSFET switching
- Tight LLC duty cycle symmetry for balanced O/P diode currents
- Lead and halogen free Green package
Applications
- 32” to 60” LCD TV power supplies
- Off-line 150 W to 600 W efficiency-optimized power supplies
- LED street lighting
Description
The PLC810PG is a combined PFC and LLC off-line controller with integrated high voltage half-bridge drivers. Figure 1 shows a simplified schematic of a PLC810PG based power supply where the LLC resonant inductor is integrated into the Figure 1. Typical Application Circuit – LCD TV Power Supply. cost and external components. the traditional frequency of operation found in televisions. currents reducing output diode cost. operating frequency as a result of line and load changes.
Rev. F 08/09 PLC810PG www.powerint.com becomes discontinuous improving light load operation and reducing power line harmonics. PFC and LLC primary side fault management is provided. The phase of the PFC PWM output is dynamically adjusted relative to the LLC phase such that the switching edges do not coincide with noise sensitive events in the PWM and LLC timing circuits. This edge-collision avoidance technology simplifies power supply layout and improves performance. Phase synchronization reduces EMI spectral components and reduces ripple current in the PFC capacitor.
Rev. F 08/09 PLC810PG www.powerint.com Pin Description VCC Pins VCC VCC powers the small signal analog circuitry inside the IC. A bypass capacitor must be connected from the VCC pin to the GND pin. This capacitor needs to be a 10 mF ceramic capacitor, or a parallel combination of a 10 mF electrolytic capacitor and a 0.1 mF ceramic capacitor. VCCL VCCL is the supply pin for the LLC low side driver. It powers only the LLC low side MOSFET driver and the communications circuitry between the analog circuitry and the LLC drivers. A 1 mF ceramic bypass capacitor must be connected from the VCCL pin to the GNDL pin. This capacitor provides the instantaneous current for turning on the gate of the LLC low-side MOSFET. VCCHB VCCHB is the floating supply pin for the LLC high-side driver, which is referenced to the HB pin. The HB pin is in turn connected to the LLC MOSFET half-bridge center point. A 1 mF ceramic bypass capacitor must be connected from the VCCHB pin to the HB pin. This capacitor provides the instantaneous current for turning on the gate of the high side LLC MOSFET. In a typical application, VCC is connected to the standby supply. VCCL should be connected to the VCC pin through a 5 W resistor for noise immunity. VCCHB is connected to the standby supply through a series combination of a high voltage diode and a 5 W resistor. This diode plus resistor combination charges the 1 mF decoupling capacitor whenever the LLC low- side MOSFET is on. The resistor limits the peak instantaneous charging current. See R42 and D8 in Figure 4. GND Pins GND GND is the return node for all analog small signals. All small signal pin bypass capacitors must be connected to this pin via short traces. This pin must have a single point connection, via a dedicated trace to the PFC current sense resistor, which in turn must be placed close to the PFC MOSFET. It must not be connected to any other point in the PFC/LLC power train. The VCC bypass capacitor must also be connected to this pin. GNDP GNDP is the return for the PFC gate drive signal only. This pin must be connected on the PCB directly to the GND pin. GNDL GNDL is the return for the LLC low side gate driver only. This pin must be connected to the LLC low side MOSFET Source pin, with a dedicated trace, and a small ferrite bead. This pin must be connected to the GND pin via a 1 W resistor for noise immunity. The VCCL bypass capacitor must also be returned to this pin. Other Pins HB Half-bridge pin. This pin is the return of the LLC high side MOSFET driver. It must be connected to the center of the half- bridge formed by the LLC MOSFETs. The VCCHB bypass capacitor must also be returned to this pin. ISP Current sense, PFC. It is for sensing the negative voltage on the current sense resistor (which describes PFC inductor current). This sense resistor is connected between PFC MOSFET Source and Bridge ‘-’ terminal. The signal must pass through an RC low-pass filter with a time constant between 100 and 200 ns. The resistor must be no greater than 150 W due to internal offset current requirements for the ISP pin. The average inductor current (measured over several switching cycles) is used for the PFC control algorithm. This pin also Implements pulse-by-pulse current limiting. ISL Current sense, LLC. This pin is for sensing transformer primary current, to detect LLC overload. It should be connected to the current sense resistor, which is connected between the LLC low side MOSFET Source pin and the bottom side of the trans- former primary. The signal must pass through an RC low-pass filter with a time constant between 200 ns and 1 ms. The capacitor in the low-pass filter must be connected to the GND pin. The current limit has 2 levels, a lower, slow current limit for output overload, and a higher, fast current limit for component failure protection. The series resistor in the low-pass filter should be 1 kW or greater to limit current into the ISL pin. GATEP Gate drive output signal for the PFC MOSFET gate drive circuit. GATEL Gate drive for the low side LLC MOSFET. GATEH Gate drive for the high side LLC MOSFET. VREF 3.3 V reference pin for the LLC feedback circuitry. A 1 mF ceramic decoupling capacitor must be connected from the V REF pin to the GND pin. FBP The Feedback PFC pin is connected to the external resistor divider that senses PFC output voltage. This is a non-inverting input to a transconductance amplifier. The transconductance amplifier output is connected to the VCOMP pin, to which the feedback compensation is also connected. A 10 nF decoupling capacitor must be connected from the FBP pin to the GND pin. VCOMP This pin is the connection point for PFC feedback loop components. The voltage on this pin is used as an input to the PFC controller multiplier. The linear voltage range for this pin is nominally 0.5 V to 2.5 V, where higher voltage signifies less power. FBL LLC Feedback pin. Current entering this pin determines LLC switching frequency. It has a Thevenin equivalent circuit of nominally 0.65 V and 3.3 kW. FBL must be decoupled to the GND pin with a 1 nF capacitor. Note that this capacitor forms a pole with the input resistance.
the LLC high and low side drivers turn both LLC MOSFETs off. be connected to the GND pin. Figure 2. Pin Numbering and Designation (Top View).
Figure 3. Block Diagram of PLC810PG. Reserved Pins are not Shown. of the functional blocks are shared. the VUVLO(+) and VUVLO(-) thresholds to start/stop the PLC810PG. charge for the LLC high-side MOSFET for gate drive.
3.3 V LINEAR
Rev. F 08/09 PLC810PG www.powerint.com PLC810PG PFC Control Block The PLC810PG PFC is a boost converter which conditions the average input current to make it (typically) sinusoidal and in phase with the input voltage. In normal operation the PFC operates in continuous conduction mode (CCM). Under light load, depending on the PFC inductor value, the converter may enter a discontinuous conduction mode (DCM). The PLC810PG PFC controller does not need to sense the input voltage. The PLC810PG PFC controller exploits the fact that the input voltage (VIN) is effectively constant over a few adjacent switching cycles, because the input is changing at 60 Hz while the switching frequency is 1500 times higher. Using the average input voltage and output voltage values, the off-time for the boost converter is: D D V V1OFF O IN = - =] g The input current is the same as the inductor current (sensed current), thus from the previous equation, it can be deduced that: I V D I V IN IN OFF SENSE O In order to make the input impedance look resistive, the input current must be proportional to the input voltage: I V R NI E N Thus, Doff has to be controlled by: D V R IOFF O E SENSE#= c m If (DOFF) changes slowly with the input voltage, the average current will be in-phase with the input voltage. The PLC810PG PFC block controls the PFC off-time (DOFF = (1–D)). The output voltage needs to be regulated and R E needs to be adjusted as a function of the load and the input voltage. The PLC810PG PFC has two inputs:
- The feed-back PFC output voltage is reduced by a resistor divider and sensed and via the FBP pin.
- The instantaneous inductor current, sensed via the ISP pin. The PFC output voltage is sensed at the FBP pin through an external resistive divider so that the desired DC boost voltage (typically 385 V) is reduced to match the internally generated VFBPREF (2.2 V) reference voltage. The FBP input pin and the VFBPREF voltage are inputs to an operational transconductance amplifier (OTA). The output of the OTA drives the VCOMP pin, allowing external compensation of the low frequency voltage loop. The purpose of the phase alignment block is to set the edges of the PFC MOSFET gate drive signal to avoid the LLC converter switching edges. This eliminates switching-noise coupling between LLC and PFC circuits. The compensation components are connected between VCOMP and the analog ground pin (GND). The VCOMP pin is used to apply compensation to the low frequency voltage loop. The voltage developed across the PFC current sense resistor and applied to the ISP pin is compared against an overcurrent threshold (which has built in hysteresis). This implements a pulse-by-pulse current limit to protect the PFC MOSFET against overcurrent. The ISP pin voltage is also averaged (over several switching cycles), and used as an input to the PFC multiplier. The Discrete Variable Gain Amplifier, DVGA/LPF block is responsible for averaging the ISP pin voltage (over several switching cycles) and implementing a multiplier as part of the PFC control loop, under control of the VCOMP signal. Using the feedback voltage on FBP, PFC and LLC circuit protection is provided:
- PFC overvoltage protection: The feedback voltage on the FBP pin is compared against an overvoltage threshold (VOV(H)). If the voltage at the FBP pin is greater than VOV(H), the PFC MOSFET gate signal is turned OFF immediately, and held off for at least one cycle. When FBP drops below VOV(H), PFC switching recommences.
- Minimum boost voltage detection: The feedback voltage on FBP is compared against a minimum boost voltage thresh- old (VIN(H)/VIN(L)). The PFC is inhibited if the FBP voltage is below VIN(L). The gate of the PFC MOSFET is driven via GATEP if the FBP voltage is above VIN(H)). This is done to prevent PFC startup in brownout or during AC failure conditions.
- Minimum boost voltage for LLC startup: The feedback voltage on FBP is compared against an LLC shutdown voltage threshold (VSD(H))/ VSD(L)). This inhibits LLC startup until the PFC output voltage is close to regulation. The purpose of VSD(L) is to shutdown the LLC when the PFC output voltage is low (~64% of nominal), which may occur during AC dropout, shutdown, or overload conditions.
- PFC open-loop protection: The FBP pin includes a high- impedance (5 MW) pull-down resistor to protect against a floating FBP pin resulting in an open-loop condition. PLC810 LLC Control Block The PLC810PG LLC controller supports half-bridge topologies. The LLC circuit relies on two switches in a half-bridge topology driving a resonant tank (LLC) and power transformer. The LLC circuit has two resonant frequencies: the series resonant frequency and the parallel resonant frequency. Typically, an LLC converter is designed to operate at a switching frequency which is slightly higher than the series resonant frequency when at nominal input voltage. In this operating region, the MOSFET switching can be performed at zero voltage, reducing the switching losses. In the normal mode of operation, the LLC controller will vary its switching frequency around a narrow range of frequencies to regulate the output voltage. Feedback and Maximum Frequency Limit The PLC810PG LLC controller has nominal operating frequency of 100 kHz. For voltage regulation, with input voltage and load variations, the operating frequency will vary and may exceed 250 kHz. The maximum frequency set by the resistor on FMAX pin is typically chosen to be two to three times the nominal operating frequency. The appropriate maximum frequency is set
Rev. F 08/09 PLC810PG www.powerint.com using a resistor connected between the VREF pin and the FMAX pin using the curve in Figure 15. The resistor on the FMAX pin also sets the LLC dead time interval (see Figure 14). The FBL pin provides output voltage regulation. As such the current entering this pin modulates the switching frequency. More current forces a higher switching frequency. The FMAX pin sets an upper limit for the switching frequency to ensure zero voltage switching. Minimum switching frequency is determined by the adjusting minimum bias applied to the FBL pin. If the external feedback circuit attempts to push the LLC controller to a frequency equal to or higher than the maximum frequency limit set by the resistor at FMAX pin, the LLC MOSFET gate driver outputs are turned off until the current into the FBL pin drops below the FMAX pin current. The gate outputs are turned off synchronously with the clock for whole cycles. LLC Soft Start The LLC controller implements a soft start to prevent excessive currents during startup, and to prevent overshoot on the output when the feedback loop comes into operation. The soft start time is determined by external components on the FBL pin. In the event of an LLC fault turning off the LLC circuit, the external circuit is allowed to discharge, initiating a new soft start. When the soft start signal is asserted, the FBL pin is pulled up to V REF (3.3 V), keeping the current applied to the FBL pin to maximum. During the soft start cycle, the LLC outputs turn on and the switching frequency slowly decays from its maximum to the nominal operating point. LLC Overcurrent Detection (ISL Pin) Overcurrent in the LLC converter is detected via a sense resistor in series with the low side of the transformer’s primary winding. When the overcurrent condition is detected, the LLC MOSFETS are turned OFF. The overcurrent detection has two thresholds; fast overcurrent threshold (V ISL(F)) and slow over- current threshold (V ISL(S)). The fast overcurrent threshold is triggered by abnormally high current. The LLC is shutdown immediately if the pulse on the ISL pin exceeds this threshold. The slow overcurrent threshold is lower than the fast over- current threshold. The slow overcurrent response is triggered and the LLC is shutdown if the ISL pin voltage exceeds this threshold for eight consecutive clock cycles. Typically the (VISL(F)) threshold is used to detect catastrophic failures such as shorted components, while the slow V ISL(S) threshold is used to detect overload conditions. This over- current detection circuit prevents the LLC converter from operating in the capacitive region of the LLC, thus avoiding failure of the converter components from overheating. Other LLC Control Blocks The non-overlap (dead time) generator creates two non- overlapping signals with equal on-times to drive the LLC MOSFETS. The drive signal for the two LLC MOSFETS is symmetrical with a 50% duty cycle. The dead time block is used both by the PFC and LLC to control the dead time of the switching function. The dead time in the PLC810PG is configurable via the FMAX pin. The dead time allows zero voltage switching, reducing the body diode losses in the switching MOSFETs and minimizing the reverse recovery time of the body diodes. Start-up Once the VCC voltages reach the startup voltage (V UVLO(+)), the PLC810PG starts switching the PFC MOSFET and the PFC output ramps to its nominal value. When the PFC boost voltage (sensed through FBP pin) raises the FBP pin voltage above the LLC start threshold (V SD(H)), the LLC circuit is enabled and the LLC soft start begins.
Figure 4. PLC810PG LCD TV Power Supply Application Circuit, PFC Circuit Control Inputs and LLC Stage.
5 V_STBY
5 V Main
200 VC24
Figure 5. PLC810PG LCD TV Power Supply Application Circuit, Input Circuit and PFC Power Stage. Figure 6. PLC810PG LCD TV Power Supply Application Circuit, Standby Supply.
250 VAC
275 VAC
320 VAC
25 V RTN
Rev. F 08/09 PLC810PG www.powerint.com Applications Example Circuit Description Figures 4, 5, and 6 show the schematic of a typical 280 W LCD TV power supply application using HiperPLC and TinySwitch-III. The PSU contains PFC + LLC stage using a PLC810PG which provides the high power outputs, plus a standby power supply using a TNY275PN. The design has 4 outputs: 12 V and 24 V, 5 V main and 5 V standby. The 5 V main and 5 V standby are provided by the TinySwitch-III flyback circuit. See the Typical Application section of the TinySwitch-III data sheet found on the Power Integrations website for a description of a TinySwitch-III flyback converter. The PSU has a standby input signal, which enables the main converter (PLC810PG). EMI Filtering and Rectification Capacitors C42, C1, C5, C3, C4, C2, C6 and common mode chokes L1 and L2 perform EMI filtering. Diode bridge BR1 rectifies the input AC with D14 and D15 providing a separate full-wave rectified signal for the brownout circuit. Inrush Limiting Thermistor RT1 provides inrush limiting. It is bypassed by a relay (RL1) which is driven by the power supply remote-on signal. The use of a relay increases efficiency by approximately 1%. Diode D3 provides an inrush path to the bulk capacitor C9 that bypasses the PFC inductor L4 to prevent it from saturating. PFC Stage The main PFC inductor L4, MOSFET Q2, boost diode D2, and bulk cap C9, form a PFC boost converter. Capacitor C8 and R5 damp reverse recovery ringing on D2. Inductor L4 uses a small low cost Sendust core. Two key advantages of this continuous mode PFC design are that the low ripple current allows the use of: 1. High BSAT material (such as low-cost Sendust), allowing fewer turns which saves copper cost and reduces size. 2. Low-cost magnet wire rather than Litz wire. Diode D2 is a low-cost silicon ultrafast PFC boost diode. Components Q1, Q3, C10 and R7 form the gate drive circuit. See description under “Recommended PFC Gate Drive Circuit“. PFC Current sense resistors R6 and R8 are clamped by D3 and D4 to protect the current sense input of the controller IC during inrush. Capacitor C11 is positioned close to the PFC MOSFET and diode to limit the size of the high frequency loop around components Q2, D2 and C9. This reduces EMI. Low-loss film capacitor C7 functions as the input capacitance to the PFC boost converter, and also filters EMI. LLC Stage LLC Input Stage MOSFETs Q10 and Q11 form the LLC half-bridge. They are driven directly by the PLC810 via gate resistors R56 and R58. Capacitor C39 is the primary resonating capacitor, and should be a low-loss type rated to tolerate the highest RMS current seen at maximum load. Transformer T2 has a large built-in leakage inductance which acts with C39 to form the series resonant tank. Capacitor C40 is used for local bypassing, and is located directly adjacent to Q10 and Q11. Resistor R59 provides primary current sensing to the controller for overload protection. LLC Outputs The secondary ouputs of transformer T2 are rectified and filtered by D9, D10, C38, C39 and C53 to provide the + 12 and +24 V outputs. Switched +5 V Main Output MOSFET Q12 is used to switch the output of the +5 V logic supply. The AC signal from one side of the 12 V output rectifier is used to drive Q12 via R60, R61, D11, and C43. Capacitor C44 provides filtering near the output connection. Bias Regulator / Remote On/Off and Brownout Shutdown Circuit Components Q4, U1, C17 , and associated components constitute the bias regulator and provide the remote on-off function. Darlington transistor Q4, R14, and VR2 form a simple emitter follower voltage regulator that is switched via optocoupler U1. Capacitor C17 limits the rate of rise of the bias voltage. Transistor Q5 and R20 quickly discharge C17 when optocoupler U1 is turned off. On the secondary, optocoupler U1 is turned on via Q8 when the standby signal is high. This turns on the PFC LLC stages. A brownout shutdown circuit is provided to actively shutdown the PSU when the output turns off due to a brownout condition. This circuit operates by sensing the AC input voltage together with the presence of the GATEL signal from the LLC controller. During a brownout condition, the PFC output voltage will drop until the VFB pin voltage drops to INH, turning off the LLC stage. If at this point the AC voltage is below 82 VAC, the brownout circuit will turn off the PLC810 via the bias regulator, preventing the PFC from charging up the bulk capacitor again, restarting the LLC, and repeating the cycle (and creating output voltage glitches). Resistor R24, R26, R28-30, C21, VR4, and Q7 are used to sense the AC input voltage. The voltage threshold of this circuit is set below the turn-on threshold of the standby/primary bias converter. Sufficient AC voltage turns on Q7, discharging capacitor C22, which is charged via R15. Components R32, R35, and Q9 sense the switching GATEL signal. Transistor Q9 discharges capacitor C22 when the switching signal is present.
Rev. F 08/09 PLC810PG www.powerint.com of an operational transconductance amplifier (OTA). The output of this OTA is connected to the VCOMP pin. The feedback loop operates to keep the voltage on the FBP pin (and therefore the PFC output voltage) to a fixed value, depending on the resistor divider ratio. When the PFC output voltage is higher than the set point, the transconductance amplifier will source current, raising the voltage on the VCOMP pin. When the PFC output voltage is lower than the set point, the transconductance amplifier will sink current, lowering the voltage on VCOMP pin. The gain of the stage is equal to the product of the OTA gain (GM), and the impedance of the network connected to the VCOMP pin. The PFC controller senses the voltage on the VCOMP pin. A higher voltage tends to reduce the PFC MOSFET’s duty cycle, while a lower voltage tends to increase it. The VCOMP pin has a linear operating range of 0.5 V to 2.5 V, and is scaled and multiplied by the average inductor current to set DOFF, the off-duty-cycle of the PFC gate signal. During closed-loop steady state operation, the VCOMP voltage is a function of the line voltage and the PFC load. A low voltage on VCOMP signifies high power, while a high voltage corresponds to low power. The VCOMP pin is internally connected to an input of a multiplier which is part of the PFC modulator. The linear range of this pin signifies minimum power. The FBP pin has 3 start-up and shutdown voltage thresholds. 1. INH – Inhibits PFC start-up at low AC input voltage. 2. VSD(H) – inhibits LLC start-up after PFC start-up. LLC start-up is delayed until the PFC output voltage is close to its regulation set point. 3. VSD(L) – shuts down the LLC converter when the bulk cap has discharged to a low voltage – typically at the end of holdup time. Before PFC start-up, the voltage on the bulk cap is approx- imately equal to the peak of the input voltage, and INH acts as an AC undervoltage lockout. After the PFC starts, the PFC output voltage no longer tracks the input voltage and there is no low AC voltage shutdown function. For a typical design with a PFC voltage set point of 385 V, the PFC is inhibited when bulk voltage <100 V (typical), which is equivalent to VAC <71 V (typical). LLC start-up is inhibited until the PFC output voltage reaches 368 V (typical). For the same design, the LLC will shut down when the PFC output voltage drops below 246 V (typical). LLC Controller Section The LLC converter is a variable frequency converter (an LLC converter’s output power decreases as frequency increases). The designer needs to set the minimum and maximum frequencies of the PLC810PG to suit the power train. FMAX Pin The FMAX pin is connected via a programming resistor to the VREF pin. This resistor programs the current into the FMAX pin. This pin has a nominal Thevenin equivalent circuit of 0.65 V and 1.5 kW. The programmed current into the FMAX pin controls two parameters: 1. The LLC drive (GATEL and GATEH) dead-time. The smaller the resistor value, the greater the current and the higher the maximum frequency, see Figure 15. 2. The maximum LLC operating frequency. When the FBL pin current increases above the FMAX pin current, the LLC MOSFETs will be shut down. Switching will restart when the FBL pin current drops below the FMAX pin current. The dead-time should be longer than the actual voltage rise and fall times of the LLC half-bridge center-point (longest times at minimum load). If the programmed dead-time is shorter than the actual rise and fall times, the MOSFETs will no longer operate in the ZVS region, and losses will increase. Dead-times somewhat longer than this required minimum have very little impact on efficiency. During long dead-times the body diodes of the LLC switching MOSFETs will conduct current just before turn-on; the additional conduction loss is very small compared to other losses. The FMAX pin programming resistor sets both dead- time and maximum frequency. Setting a longer dead-time than that required at no-load is the recommended approach if a lower maximum frequency is desired If the required dead-time is very long, and the resulting F MAX is lower than that required for light load regulation (for the worst case at maximum input voltage), then the solution is to limit F MAX and allow the LLC to enter burst-mode under light load (maximum frequency) in order to keep the output in regulation. Maximum input voltage occurs during a 100-0% load step which causes the PFC output voltage to overshoot to VOV(H) triggering the PFC output overvoltage protection circuit (which is nominally 105% of the PFC nominal voltage set point). For a typical design, an LLC converter requires an F MAX of 1.5x ~ 2x the nominal operating frequency (measured at full load and nominal input voltage). If burst-mode regulation is required for light load operation, the FBL pin resistors must be chosen such that the maximum current driven by the feedback loop into the FBL pin is greater than the FMAX pin current (set by the FMAX pin resistor). When the FBL pin current is greater than the FMAX pin current, the LLC gate drivers turn off both MOSFETs. During line/load conditions that require higher frequency than F MAX to maintain regulation, the LLC converter will go into hysteretic burst-mode to maintain regulation. When burst mode is used, care must be taken to ensure that during startup, the peak primary currents do not trigger primary over current (ISL pin). This is because switching frequency cannot be higher than FMAX (even during soft start) and the peak primary currents with a low soft start frequency will therefore be higher.
Figure 7. Typical LLC Feedback Network. stability the 1 nF capacitor should not be increased. start-up currents into the FBL pin. (nominal) of the regulation set point. pin current, the LLC gate drivers turn both MOSFETs off. FBL pin current comes from R3. The procedure for selecting the resistor values is as follows. This is the main load resistance in series with the optocoupler. FSTART is typically chosen to be equal to or just less than F MAX. have a value close to that of the FMAX resistor. load, then burst mode operation will be required.
voltages and currents for all inputs and outputs of PLC810PG. respectively to GNDP/GND, GNDL and HB. ESD handling precautions are recommended. Table 1. Absolute Maximum Ratings.
Rev. F 08/09 PLC810PG www.powerint.com Parameter Symbol Pin Notes Min Typ Max Units Undervoltage Lockout VCC Start Threshold Voltage VUVLO(+) VCC Device exits UVLO state when VCC exceeds VUVLO(+) 8.2 9.1 10 VVCCHB - HB 9.2 VCC Shutdown Threshold Voltage VUVLO(-) VCC Device enters UVLO state when VCC falls below VUVLO(-) 7.2 8.1 9.0 VVCCHB - HB 8.7 VCC Start-up/ Shutdown Hysteresis VUVLO(HYST) VCC 0.7 1.0 1.3 V LLC VCO VCO Frequency Range FRANGE FBL LLC/PFC Synchronized 50 300 kHz Accuracy of VCO Min Frequency Limit FMINACC FBL R(FBL) = 100 kW to VREF -15 +15 % Accuracy of VCO Max Frequency Limit FMAXACC FMAX R(FMAX) = 17.8 kW to VREF -15 +15 % LLC Duty Cycle DVCO GATEH, GATEL On-time matching GATEH (GATEH + GATEL) 49 50 51 % Dead Time Accuracy tDVCOACC GATEH, GATEL R(FMAX) = 17.8 kW to VREF -8 +12 % Maximum FMAX Current IFMAX FMAX Power dissipation limit, IFBL is limited by the current into FMAX 135 mA FBL Current Upper Limit IFBL FBL Operating range of FBL controlled VCO 95 % IFMAX FBL Equivalent Input Circuit VIN(FBL) FBL FBL input behaves as RIN(FBL) in series with VIN(FBL). I(FBL) from 50 to 130 mA 0.65 V RIN(FBL) 3.3 kW FBL Pin Voltage VFBL FBL FVCO = 100 kHz 0.83 V FBL Soft Start Pull-up Resistance RPU(SS) FBL Internal pull-up to VREF during soft start reset (4096 FMAX cycles instantaneous) 900 1500 W Fast LLC Overcurrent Fault Voltage Threshold VISL(F) ISL 1.33 1.4 1.47 V Slow LLC Overcurrent Fault Voltage Threshold VISL(S) ISL 8 Cycle de-bounce 0.385 0.5 0.525 V LLC Overcurrent Fault Pulse Width TOVL ISL Minimum time VISL exceeds VISL(F)/VISL(S) per cycle to trigger fault 75 ns
Rev. F 08/09 PLC810PG www.powerint.com Parameter Symbol Pin Notes Min Typ Max Units PFC PFC Overcurrent Limit Threshold VOC ISP Static Measurement -440 -480 -520 mV PFC Output Continuous Duty Cycle Range DCPFC GATEP 0 100 % PFC Error Amplifier Reference VFBPREF FBP 2.2 V PFC Error Amplifier Reference Accuracy FBPREF FBP -2 2 % PFC Overvoltage Threshold VOV(H) FBP See Note 1 103 105 107 %VFBPREF PFC Inhibit Upper Threshold INH FBP See Note 1 25 26 27 %VFBPREF PFC Inhibit Lower Threshold INL FBP See Note 1 22 23 24 %VFBPREF Transconductance GM FBP VFBP = VFBPREF ±85 mV 55 85 115 mA/V LLC LLC Shutdown Upper Threshold VSD(H) FBP See Note 1 94.5 95.5 96.5 %VFBPREF LLC Shutdown Lower Threshold VSD(L) FBP See Note 1 63 64 65 %VFBPREF Reference Reference Voltage VREF VREF Loaded with IREF 3.09 3.25 3.41 V Current Source Capability of VREF Pin IREF VREF 5 mA VREF Capacitance CREF VREF Required external decoupling capacitance on VREF pin 1 mF PFC GATE Output PFC GATE Output Voltage VGATE(P) GATEP GND VCC Output Short-circuit Current Driving High ISC(H) GATEP 25 mA Output Short-circuit Current Driving Low ISC(L) GATEP 60 mA Output High Voltage VO(H) GATEP VCC = 12 V IOH = 1.25 mA 11.5 11.8 V Output Low Voltage VO(L) GATEP VCC = 12 V IOL = 5 mA 0.5 0.75 V
Table 2. DC Operating Characterisitics.
- This parameter tracks VFBPREF.
shows the package outline and dimensions. Figure 18. PLC810PG Part Marking.
- Package dimensions conform to JEDEC
- Controlling dimensions are inches.
- Dimensions shown do not include mold
shall not exceed 0.006 (0.15) on any side.
- A and B are reference datums on the
- Dimensioning and tolerancing per ASME
Figure 19. PDIP-24 Package Marking.
Rev. F 08/09 PLC810PG www.powerint.com Revision Notes Date A Initial Release 11/08 B Revised figures and text 11/08 C Text, schematic updates 12/08 D Schematic updates 02/09 E Fixed schematic Figure 4 error and removed Note 2 from Parameter Table 05/09 F Updated Figures 4, 6, 14 and 18 08/09
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