PL384XAQ8 CYSTEKEC | Alldatasheet

Document overview

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Technical content

Features

  • Trimmed oscillator for precise frequency control
  • Oscillator frequency guaranteed at 250 kHz
  • Current mode operation to 500kHz
  • Automatic feed forward compensation
  • Latching PWM for cycle-by-cycle current limiting
  • Internally trimmed reference with undervoltage lockout
  • High current totem pole output
  • Undervoltage lockout with hysteresis
  • Low start-up and operating current Block Diagram( toggle flip flop used only in PL3844A and PL3845A) S/R REF 2.50V VREF GOOD LOGIC INTERNAL BIAS OSC ERROR AMP. R 1V R S T CURRENT SENSE COMPARATOR PWM LATCH VREF 5V50mA OUTPUT VI GROUND RT/CT VFB COMP CURRENT SENSE 34V UVLO PL3842A

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 2/15 PL384XAQ8 CYStek Product Specification Absolute Maximum Ratings Symbol Parameter Value Unit VI Supply Voltage (low impedance source) 30 V VI Supply Voltage (Ii<30mA) Self Limiting IO Output Current ± 1 A EO Output Energy (capacitive load) 5 µJ Analog Inputs (pins 2, 3) -0.3 to 5.5 V Error Amplifier Output Sink Current 10 mA Ptot Power Dissipation at Tamb≤ 25℃ 1.25 W Tstg Storage Temperature Range -65 to +150 ℃ TJ Junction Operating Temperature -40 to +150 ℃ TL Lead Temperature (soldering 10s) 300 ℃ Note : All voltages are with respect to pin 5, all currents are positive into the specified terminal. Pin Connection (top view) Pin Functions No Function Description 1 COMP This pin is the Error Amplifier output and is made available for loop compensation. 2 V FB This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. 3 I SENSE A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction.

4 R T/CT The oscillator frequency and maximum output duty cycle are programmed by connecting

resistor RT to VREF and capacitor CT to ground. Operation to 500kHz is possible. 5 GROUND This pin is the combined control circuitry and power ground. 6 OUTPUT This output directly drives the gate of a power MOSFET. Peak currents up to 1A are sourced and sunk by this pin. 7 V CC This pin is the positive supply of the control IC. 8 V REF This is the reference output. It provides charging current for capacitor C T through resistor RT. Thermal Data Symbol Description Value Unit Rth, j-amb Thermal Resistance, junction to ambient 150 ℃/W COMP VFB ISENSE RT/CT VREF VCC OUTPUT GROUND

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 3/15 PL384XAQ8 CYStek Product Specification Electrical Characteristics (〔note 1〕Unless otherwise stated, these specifications apply for 0≤Tamb≤70℃,Vi=15V(note 5),RT=10k,CT=3.3nF) Parameter Test Conditions Symbol Min. Typ. Max. Unit Reference Section Output V oltage Tj=25℃,IO=1mA VREF 4.9 5.0 5.1 V Line Regulation 12V ≤ VI≤ 25V ∆VREF - 2 20 mV Load Regulation 1mA ≤ IO ≤ 20mA ∆VREF - 3 25 mV Temperature Stability (Note 2) ∆VREF / ∆T - 0.2 - mV/℃ Total Output Variation Line, Load, Temperature 4.82 - 5.18 V Output Noise V oltage 10Hz ≤ f ≤10kHz,Tj=25℃ (note 2) eN - 50 - µV Long Term Stability Tamb=125℃, 1000 Hrs (note 2) - 5 25 mV Output Short Circuit I SC -30 -100 -180 mA Oscillator Section Frequency Tj=25℃ TA= 0 to 70 ℃ Tj=25℃(RT=6.2k,CT=1nF) fosc 225- 250 275 kHz kHz kHz Frequency Change with V olt V CC=12V to 25V ∆fosc/∆V - 0.2 1.0 % Frequency Change with Temp TA= 0 to 70 ℃ ∆fosc/∆T - 0.5 1.0 % Oscillator V oltage Swing Peak to peak V osc - 1.6 - V Discharge Current (V osc=2V) TJ=25℃ TA= 0 to 70 ℃ Idischg 7.8 7.6 8.3 8.8 8.8 mA mA Error Amp Section Input V oltage V PIN 1=2.5V V 2 2.42 2.50 2.58 V Input Bias Current V FB=5V Ib - -0.1 -2 µA AVOL 2V ≤ Vo ≤ 4V 65 90 - dB Unity Gain Bandwidth TJ = 25℃ BW 0.7 1 - MHz Power Supply Rejec. Ratio V I = 12V to 25V PSRR 60 70 - dB Output Sink Current V PIN 2 = 2.7V , VPIN 1 = 1.1V I O 2 12 - mA Output Source Current V PIN 2 = 2.3V , VPIN 1 = 5V I O -0.5 -1 - mA VOUT High V PIN 2 = 2.3V , RL = 15kΩ to ground 5 6.2 - V VOUT Low V PIN 2 = 2.7V , RL = 15kΩ to Pin 8 - 0.8 1.1 V Current Sense Section Gain (note 3 & 4) G V 2.85 3 3.15 V/V Maximum Input Signal V PIN 1 = 5V (note 3) V 3 0.9 1 1.1 V Supply V oltage Rejection 12V ≤ VI ≤ 25V SVR - 70 - dB Input Bias Current Ib - -2 -10 µA Delay to Output - 150 300 ns Output Section ISINK = 20mA - 0.1 0.4 V Output Low Level ISINK = 200mA VOL - 1.6 2.2 V ISOURCE = 20mA 13 13.5 - V Output High Level ISOURCE = 200mA VOH 12 13.5 - V UVLO Saturation V CC = 6V , ISINK = 1mA V OLS - 0.1 1.1 V Rise Time Tj=25℃, CL=1nF (note 2) tr - 50 150 ns Fall Time Tj=25℃, CL=1nF (note 2) tf - 50 150 ns

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 4/15 PL384XAQ8 CYStek Product Specification Electrical Characteristics (continued) Parameter Test Conditions Symbol Min. Typ. Max. Unit Undervoltage Lockout Section PL3842A/PL3844A 14.5 16 17.5 V Start Threshold PL3843A/PL3845A 7.8 8.4 9.0 V Min Operating V oltage After Turn-on PL3842A/PL3844A PL3843A/PL3845A 8.5 7.0 7.6 11.5 8.2 V PWM Section PL3842A/PL3843A 94 96 100 % Maximum Duty Cycle PL3844A/PL3845A 47 48 50 % Minimum Duty Cycle - - 0 % Total Standby Current VI=6.5V for PL3843A/45A Ist - 0.17 0.3 mA Start-up Current VI=14V for PL3842A/44A - 0.17 0.3 mA Operating Supply Current V PIN 2 = VPIN 3 = 0V I I - 12 17 mA Zener V oltage I I = 25 mA V IZ 30 38 - V Notes: 1. Max. package power dissipation limits must be respected; low duty cycle pulse techniques are used during test maintain Tj as close to Tamb as possible. 2.These parameters, although guaranteed, are not 100% tested in production. 3.Parameter measured at trip point of latch with VPIN 2= 0 . 4.Gain defined as: 5. Adjust VI above the start threshold before setting at 15V. ∆VPIN 1 ∆VPIN 3 , 0 ≤ VPIN 3 ≤ 0.8V

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 11/15 PL384XAQ8 CYStek Product Specification Figure 18: Error Amplifier Compensation 2.5V EA 1mA Rf Cf Ri Rd From Vo R Error Amp compensation circuit for stabilizing any current -mode topology except for boost and flyback converters operating with continuous inductor current. 2.5V EA 1mA Rf Cf Ri Rd From Vo R Rp Cp Error Amp compensation circuit for stabilizing current--mode boost and flyback

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 12/15 PL384XAQ8 CYStek Product Specification Figure 19:External Duty Cycle Clamp and Multi Unit Synchronization

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 13/15 PL384XAQ8 CYStek Product Specification Figure 20:Soft-Start Circuit S R Q 5Vref BIAS OSC R EA 1mA R R C 1MΩ

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 14/15 PL384XAQ8 CYStek Product Specification Figure 21:Soft-Start and Error Amplifier Output Duty Cycle Clamp. S R Q 5Vref BIAS OSC R EA 1mA R R C BC109 Vclamp Comp/Latch Vcc Vin Rs VCLAMP = R 1+ R2 - where 0< VCLAMP <1V Ipk(max) = V Rs CLAMP

CYStech Electronics Corp. Spec. No. : C510Q8-A Issued Date : 2003.08.12 Revised Date : Page No. : 15/15 PL384XAQ8 CYStek Product Specification SO-8 Dimension *: Typical DIM Inches Millimeters Inches Millimeters H 0.1889 0.2007 4.80 5.10 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material:

  • Lead: 42 Alloy; solder plating
  • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0 Important Notice:
  • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
  • CYStek reserves the right to make changes to its products without notice.
  • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
  • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. 8-Lead SO-8 Plastic Package CYStek Package Code: Q8 Marking: Top View A B Front View F C D E G Part A I H J K O M L N Right side View Part A 384XA