PFS704

PFS704 POWERINT | Alldatasheet

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Technical content

www.powerint.com December 2011 High Power PFC Controller with Integrated High-Voltage MOSFET Key Benefits

• Single chip solution for boost power factor correction (PFC)
• EN61000-3-2 Class C and D compliant
• High light load efficiency at 10% and 20% load
• >95% efficiency from 10% load to full load
• <130 mW no-load consumption at 230 VAC with output in regulation
• <50 mW no-load consumption at 230 VAC in remote off state
• Frequency adjusted over line voltage, and line cycle
• Spread-spectrum across >60 kHz window to simplify EMI filtering requirements
• Lower boost inductance
• Provides up to 1 kW peak output power
• >1 kW peak power delivery in power limit voltage regulation mode
• High integration allows smaller form factor, higher power density designs
• Incorporates control, gate driver, and high-voltage power MOSFET
• Internal current sense reduces component count and system losses
• Protection features include: UV, OV, OTP , brown-in/out, cycle- by-cycle current limit, and power limiting for overload protection
• Halogen free and RoHS compliant

Applications

• PC • High power adaptors
• Printer • High power LED lighting
• LCD TV • Industrial and appliance
• Video game consoles • Generic PFC converters

Figure 1. Typical Application Schematic.

90 VAC

180 VAC

Table 1. Output Power Table (see Notes on page 9)

Rev. D 12/11 PFS704-729EG www.powerint.com Section List

Rev. D 12/11 PFS704-729EG www.powerint.com

Description

The HiperPFS device family members incorporate a continuous conduction mode (CCM) boost PFC controller, gate driver, and high voltage power MOSFET in a single, low-profile eSIP™ power package that is able to provide near unity input power factor. The HiperPFS devices eliminate the PFC converter’s need for external current sense resistors, the power loss associated with those components, and leverages an innovative control technique that adjusts the switching frequency over output load, input line voltage, and even input line cycle. This control technique is designed to maximize efficiency over the entire load range of the converter, particularly at light loads. Additionally, this control technique significantly minimizes the EMI filtering requirements due to its wide-bandwidth spread spectrum effect. HiperPFS includes Power Integrations’ standard set of comprehensive protection features, such as integrated soft-start, UV, OV, brown-in/out, and hysteretic thermal shutdown. HiperPFS also provides cycle-by-cycle current limit for the power MOSFET, power limiting of the output for over- load protection, and pin-to-pin short-circuit protection. HiperPFS’s innovative variable-frequency continuous conduction mode of operation (VF-CCM) minimizes switching losses by maintaining a low average switching frequency, while also varying the switching frequency in order to suppress EMI, the traditional challenge with continuous-conduction-mode solutions. Systems using HiperPFS typically reduce the total X and Y capacitance requirements of the converter, the inductance of both the boost choke and EMI noise suppression chokes, reducing overall system size and cost. Additionally, compared with designs that use discrete MOSFETs and controllers, HiperPFS devices dramatically reduce component count and board footprint while simplifying system design and enhancing reliability. The innovative variable-frequency, continuous conduction mode controller enables the HiperPFS to realize all of the benefits of continuous-conduction mode operation while leveraging low-cost, small, simple EMI filters. Many regions mandate high power factor for many electronic products with high power requirements. These rules are combined with numerous application-specific standards that require high power supply efficiency across the entire load range, from full load to as low as 10% load. High efficiency at light load is a challenge for traditional PFC approaches in which fixed MOSFET switching frequencies cause fixed switching losses on each cycle, even at light loads. HiperPFS simplifies compliance with new and emerging energy-efficiency standards over a broad market space in applications such as PCs, LCD TVs, notebooks, appliances, pumps, motors, fans, printers, and LED lighting. HiperPFS advanced power packaging technology and high efficiency simplifies the complexity of mounting the package and thermal management, while providing very high power capabilities in a single compact package; these devices are suitable for PFC applications from 75 W to 1 kW Product Highlights Protected Power Factor Correction Solution

• Incorporates high-voltage power MOSFET, controller, and gate driver
• EN61000-3-2 Class D compliance
• Integrated protection features reduce external component count
• Accurate built-in brown-in/out protection
• Accurate built-in undervoltage (UV) protection
• Accurate built-in overvoltage (OV) protection
• Hysteretic thermal shutdown (OTP)
• Internal power limiting function for overload protection
• Cycle-by-cycle power switch current limit
• No external current sense required
• Provides “lossless” internal sensing via sense-FET
• Reduces component count and system losses
• Minimizes high current gate drive loop area
• Minimizes output overshoot and stresses during start-up
• Integrated power limit and frequency soft start
• Improve dynamic response
• Input line feed-forward gain adjustment for constant loop gain across entire input voltage range
• Eliminates up to 40 discrete components for higher reliability and lower cost Intelligent Solution for High Efficiency and Low EMI
• Continuous conduction mode PFC uses novel constant volt/ amp-second control engine
• High efficiency across load using a UF boost diode
• Low cost EMI filter
• Universal input device (PFS704 – PFS716) utilize frequency sliding technique for light load efficiency improvements
• >95% efficiency from 10% load to full load at low line input voltage
• >96% efficiency from 10% load to full load at high line input voltage
• High line input device (PFS723 – PFS729) maintain higher average switching frequency to minimize boost inductance and core size
• >94% efficiency from 10% load to full load
• Variable switching frequency to simplify EMI filter design
• Varies over line input voltage to maximize efficiency and minimize EMI filter requirements
• Varies with input line cycle voltage by >60 kHz to maximize spread spectrum effect Advanced Package for High Power Applications
• Up to 1 kW peak output power capability in a highly compact package
• Simple clip mounting to heat sink
• Can be directly connected to heat sink with insulation pad
• Provides thermal impedance equivalent to a TO-220
• Staggered pin arrangement for simple routing of board traces and high voltage creepage requirements
• Single package solution for PFC converter reduces assembly costs and layout size

Figure 3. Functional Block Diagram.

9 MW for PFS72x) to minimize power dissipation and standby

features both brown-in and brown-out protection. switching noise. This pin is also used for loop compensation. SIGNAL GROUND pin must not be tied to the SOURCE pin. This pin is the source connection of the power switch. This is the tab and drain connection of the internal power switch. Figure 2. Pin Configuration.

of the maximum value at low input line conditions. the IC will reinitiate the start-up sequence. device from starting at very low input AC voltage. Figure 8. (a) Frequency Variation Over Line Half-Cycle as a Function of Input V oltage (b) Frequency Variation Over Line Half-Cycle as a Function of Load. Figure 9. VOFF vs. VE and VOFF vs. Input Voltage.

230 VAC 180 VAC 135 VAC 115 VAC

Figure 10. Line Dependant OCP . below the brown-out threshold. excess of the 2 ms delay will terminate the switch cycle immediately. This detection circuit also includes some hysteresis. detection, this mode has a deglitch filter of approximately 100 ms. soft-start once the VCC pin voltage exceeds the V CC+ threshold. to prevent damage to the IC. short-circuit or overload fault conditions. input is at high input line. OCP) and the on-time is less than tSOA.

90 VAC2

180 VAC4

Table 2. Output Power Table.

1. See Key Application considerations.
2. Maximum practical continuous power at 90 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
3. Recommended lower range of maximum continuous power for best light load efficiency; HiperPFS will operate and perform below this level.
4. Maximum practical continuous power at 180 VAC in an open-frame design with adequate heat sinking, measured at 50 °C ambient.
5. Internal output power limit.

device from the HiperPFS family of integrated PFC controllers. components across the input when AC is removed. supply while simultaneously regulating the output DC voltage. current of the circuit at start-up and prevents saturation of L5. MOSFET inside U1 at each switching instant. prevents the supply voltage to IC U1 from exceeding 12 V. response by improving the response time of the PFC circuit.

275 VAC

250 VAC

320 VAC

380 VDC

50 V C18

Figure 11. 347 W PFC using PFS714EG.

Figure 12. 180 W PFC using PFS708EG. Figure 13. 900 W PFC using PFS729EG.

Rev. D 12/11 PFS704-729EG www.powerint.com Design, Assembly, and Layout Considerations Power Table The data sheet power table as shown in Table 2 represents the maximum practical continuous output power based on the following conditions: For the universal input devices (PFS704-716): 1. An input voltage range of 90 VAC to 264 VAC 2. Overall efficiency of at least 93% at the lowest operating voltage 3. Use of ultrafast recovery diode or high performance diode for PFC output. 4. Sufficient heat sinking to keep device temperature ≤100 ºC 5. 380 V to 385 V nominal output For the 230 V only devices (PFS723-729): 1. An input voltage range of 180 VAC to 264 VAC 2. Overall efficiency of at least 96% at the lowest operating voltage 3. Use of ultrafast recovery diode or high performance diode for PFC output. 4. Sufficient heat sinking to keep device temperature ≤100 ºC 5. 380 V to 385 V nominal output Operation beyond the limits stated above will require derating. Use of a nominal output voltage higher than 390 V is not recommended for HiperPFS based designs. Operation at voltages higher than 390 V can result in higher than expected drain-source voltage during line and load transients. HiperPFS Selection Selection of the optimum HiperPFS part depends on required maximum output power, PFC efficiency and overall system efficiency (when used with a second stage DC-DC converter), heat sinking constraints, system requirements and cost goals. The HiperPFS part used in a design can be easily replaced with the next higher or lower part in the power table to optimize performance, improve efficiency or for applications where there are thermal design constraints. Minor adjustments to the inductance value and EMI filter components may be necessary in some designs when the next higher or the next lower HiperPFS part is used in an existing design for performance optimization. Every HiperPFS family part has an optimal load level where it offers the most value. Operating frequency of a part will change depending on load level. Change of frequency will result in change in peak to peak current ripple in the inductance used. Change in current ripple will affect input PF and total harmonic distortion of input current. Input Fuse and Protection Circuit The input fuse should be rated for a continuous current above the input current at which the PFC turns-off due to input under voltage. This voltage is referred to as the brown-out voltage. The fuse should also have sufficient I 2t rating in order to avoid nuisance failures during start-up. At start a large current is drawn from the input as the output capacitor charges to the peak of the applied voltage. The charging current is only limited by any inrush limiting thermistors, impedance of the EMI filter inductors and the forward resistance of the input rectifier diodes. A MOV will typically be required to protect the PFC from line surges. Selection of the MOV rating will depend on the energy level (EN1000-4-5 Class level) to which the PFC is required to withstand. Input EMI Filter The variable switching frequency of the HiperPFS effectively modulates the switching frequency and reduces conducted EMI peaks associated with the harmonics of the fundamental switching frequency. This is particularly beneficial for the average detection mode used in EMI measurements. The PFC is a switching converter and will need an EMI filter at the input in order to meet the requirements of most safety agency standards for conducted and radiated EMI. Typically a common mode filter with X capacitors connected across the line will provide the required attenuation of high frequency components of input current to an acceptable level. The leakage reactance of the common mode filter inductor and the X capacitors form a low pass filter. In some designs, additional differential filter inductors may have to be used to supplement the differential inductance of the common mode choke. A filter capacitor with low ESR and high ripple current capability should be connected at the output of the input bridge rectifier. This capacitor reduces the generation of the switching frequency components of the input current ripple and simplifies EMI filter design. Typically, 0.33 mF per 100 W should be used for universal input designs and 0.15 mF per 100 W of output power should be used for 230 VAC only designs. It is often possible to use a higher value of capacitance after the bridge rectifier and reduce the X capacitance in the EMI filter. Regulatory requirements require use of a discharge resistor to be connected across the input (X) capacitance on the AC side of the bridge rectifier. This is to ensure that residual charge is dissipated after the input voltage is removed when the capacitance is higher than 0.1 mF. Use of CAPZero integrated circuits from Power Integrations, helps eliminate the steady state losses associated with the use of discharge resistors connected permanently across the X capacitors. Inductor Design It is recommended that the inductor be designed with the maximum operating flux density less than 0.3 T and a peak flux density less than 0.42 T at maximum current limit when a ferrite core is used. If a core made from Sendust or MPP is used, the flux density should not exceed 1 T. A powder core inductor will have a significant drop in inductance when the flux density approaches 1 T. For high-line only designs, the value of K P (the ratio of peak to ripple current) of the drain current at the peak of the input voltage waveform should be kept below 0.5 for ferrite core and

Rev. D 12/11 PFS704-729EG www.powerint.com 0.675 for powder core designs respectively. For universal input designs, KP should be kept below 0.25 for ferrite core and 0.625 for powder core respectively. For high performance designs, use of Litz wire is recommended to reduce copper loss due to skin effect and proximity effect. For toroidal inductors the numbers of layers should be less than 3 and for bobbin wound inductors, inter layer insulation should be used to minimize inter layer capacitance. Output Diode For a 385 V nominal PFC output voltage, use of a diode with 600 V or higher PIV rating is recommended. CCM operation with hard switching demands that diodes with low reverse recovery time and reverse recovery charge should be used. The variable frequency CCM operation of HiperPFS reduces diode switching losses as compared to fixed frequency solutions and enables use of easily available high frequency diodes such as the Turbo-2 series from STMicroelectronics. Diodes with soft recovery characteristics that result in a reduced EMI are available from a number of manufacturers. For highly demanding applications such as 80 PLUS Gold power supplies, use of Silicon Carbide diodes may be considered. These uses will typically provide further full load improvement in efficiency. The diodes will be required to have a forward continuous current rating of at least 1.2 A to 1.5 A for every 100 W of output power. Output Capacitor For a 385 V nominal PFC, use of a electrolytic capacitor with 450 V or higher continuous rating is recommended. The capacitance required is dependent on the acceptable level of output ripple and any hold up time requirements. The equations below provide an easy way to determine the required capacitance in order to meet the hold up time requirement and also to meet the output ripple requirements. The higher of the two values would be required to be used: Capacitance required for meeting the hold up requirement is calculated using the equation: C VV Pt2 O OUTO UT MIN OUTH OLDU P ##= - CO PF C output capacitance in F. PO PF C output power in watts. tHOLD-UP Hold-up time specification for the power supply in seconds. VOUT Low est nominal output voltage of the PFC in volts. VOUT(MIN) Lowest permissible output voltage of the PFC at the e nd of hold-up time in volts. Capacitance required for meeting the low frequency ripple specification is calculated using the equation: C fV I O LO PFC OM AX ## ##rh D= fL In put frequency in Hz ΔVO Peak-peak output voltage ripple in volts ηPFC PFC operating efficiency IO(MAX) Maximum output current in amps Capacitance calculated using the above method should be appropriately increased to account for ageing and tolerances. Power Supply for the IC A 12 V regulated supply should be used for the HiperPFS. If the V CC exceeds 13.4 V, the HiperPFS may be damaged. In most applications a simple series pass linear regulator made using an NPN transistor and Zener diode is adequate since the HiperPFS only requires approximately 3.4 mA maximum for its operation. It is recommended that a 1 mF or higher, low ESR ceramic capacitor be used to decouple the V CC supply. This capacitor should be placed directly at the IC on the circuit board. Line-Sense Network The line-sense network connected to the V pin provides input voltage information to the HiperPFS. The value of this resistance sets the brown-in and brown-out threshold for the part. A value of 4 MW is recommended for use with the universal input parts and a value of 9 MW is recommended for the 230 VAC only parts. Only 1% tolerance resistors are recommended. This resistance value may be modified to adjust the brown-in threshold if required however change of this value will affect the maximum power delivered by the part. A decoupling capacitor of 0.1 mF is required to be connected from the VOLTAGE MONITOR pin to the GROUND pin of the HiperPFS for the universal input parts and a decoupling capacitor of 0.047 mF is required for the 230 VAC only parts. This capacitor should be placed directly at the part on the circuit board. Feedback Network A resistor divider network that provides 6 V at the feedback pin at the rated output voltage should be used. The compensation elements are included with the feedback divider network since the HiperPFS does not have a separate pin for compensation. The HiperPFS based PFC has two loops in its feedback. It has an inner current loop and a low bandwidth outer voltage loop which ensures high input power factor. The compensation RC circuit included with the feedback network reduces the response time of the HiperPFS to fast changes in output voltage resulting from transient loads. The feedback circuit recommended for use with the HiperPFS includes a pair of transistors that are biased in a way that the transistors are in cutoff during normal operation. When a rapid change occurs in the output voltage, these transistors conduct momentarily to correct the feedback pin voltage rapidly thereby helping the HiperPFS to respond to the changes in output voltage without the delay associated with a low bandwidth feedback loop. The recommended circuit and the associated component values are shown in Figure 14. Resistors, R1 to R5 comprise of the main output voltage divider network. The sum of resistors R1, R2 and R3 is the upper divider resistor and the lower feedback resistor is comprised of the sum of resistors R4 and R5. Capacitor C1 is a soft-finish capacitor that reduces output voltage overshoot at start-up. Resistor R8 and capacitor C3 form a low pass filter to filter any switching noise from coupling into the FEEDBACK pin. Resistor

diode is not recommended including small signal diodes (e.g. 1N4148) which are typically also fast recovery. feedback signal, a 20 nF capacitor may be used). recovery diode should only be used). Figure 14. Recommended Feedback Circuit.

301 V, resistor R1 may have to be divided into two or more

ratings of the resistor used. output of the PFC during transient loading and should be verified. feedback circuit, and transistor. applications up to 300 W, the heat spreader is not essential. heat sink can easily exceed 400 V during transient conditions. on applicable safety specification.

to waveform instability or dissymmetry. output diode of the PFC or the PFC inductor. Figure 19. PCB Layout Example for System Power Supply consisting of a PFC and a Second Stage Converter. traversing through the loop. connecting the feedback circuit components to the GROUND pin.

Rev. D 12/11 PFS704-729EG www.powerint.com To minimize effect of trace impedance affecting regulation, output feedback should be taken directly from the output capacitor positive terminal. The upper end of the line-sense resistors should be connected to the high frequency filter capacitor connected at the output of the bridge rectifier. Quick Design Checklist As with any power supply design, all HiperPFS designs should be verified on the bench to make sure that component specifications are not exceeded under worst-case conditions. The following minimum set of tests is strongly recommended: 1. Maximum drain voltage – verify that peak V DS does not exceed 530 V at lowest input voltage and maximum overload output power. Maximum overload output power occurs when the output is overloaded to a level just above the highest rated load or before the power supply output voltage starts falling out of regulation. Additional external snubbers should be used if this voltage is exceeded. In most designs, addition of a ceramic capacitor in the range of 33 pF and 100 pF connected across the PFC output diode will reduce the maximum drain-source voltage to a level below the BV DSS rating. When measuring drain-source voltage of the MOSFET, a high voltage probe should be used. When the probe tip is removed, a silver ring in the vicinity of the probe tip can be seen. This ring is at ground potential and the best ground connection point for making noise free measurements. Wrapping stiff wire around the ground ring and then connecting that ground wire into the circuit with the shortest possible wire length, and connecting the probe tip to the point being measured, ensures error free measurement. 2. Maximum drain current – at maximum ambient temperature, minimum input voltage and maximum output load, verify drain current waveforms at start-up for any signs of inductor saturation and excessive leading edge current spikes. HiperPFS has a leading edge blanking time of 220 ns to prevent premature termination of the ON-cycle. Verify that the leading edge current spike is below the allowed current limit for the drain current waveform at the end of the 220 ns blanking period. If a wire loop is inserted in series with the drain, it forms a small stray inductance in series with the drain. This stray inductance will add to the leading edge voltage spike on the drain source waveform. The drain- source voltage waveform should therefore never be measured with this loop. An alternate measurement that can provide drain current level and information regarding slope of the inductor current can be obtained by monitoring the inductor current instead. A wire loop can be added in series with the PFC inductor connection that connects the inductor to the input rectifier for the purpose of measurement. 3. Thermal check – at maximum output power, minimum input voltage and maximum ambient temperature; verify that temperature specifications are not exceeded for the HiperPFS, PFC inductor, output diodes and output capacitors. Enough thermal margin should be allowed for the part-to-part variation of the R DS(ON) of HiperPFS, as specified in the data sheet. A maximum package temperature of 100 °C is recommended to allow for these variations. 4. Input PF should improve with load, if performance is found to progressively deteriorate with loading then that is a sign of possible noise pickup by the VOLTAGE MONITOR pin circuit or the feedback divider network and the compensation circuit.

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Control Functions Maximum Operating ON-time tON(MAX) 0 °C < TC < 100 °C 30 40 50 ms Minimum Operating ON-time t ON(MIN) See Note A 0 °C < TC < 100 °C 0 1 Maximum Operating OFF-time t OFF(MAX) 0 °C < TC < 100 °C 30 40 50 Minimum Operating OFF-time t OFF(MIN) 0 °C < TC < 100 °C 1 3 Internal Feedback Voltage Reference V REF TC = 25 °C See Note A 5.955 6.00 6.045 V FEEDBACK Pin Voltage V FB 0 °C < TC < 100 °C (In Regulation) 5.82 6.00 6.18 V FEEDBACK Pin Current I FB TC = 25 °C 340 500 640 nA Soft-Start Time tSOFT TC = 25 °C 12 ms Internal Compensation Frequency f COMP See Note A Pole (fp) 1 kHz Error-Amplifier Gain Av See Note A 100 - Absolute Maximum Ratings Notes: 1. All voltages referenced to SOURCE, TA = 25 °C. 2. Normally limited by internal circuitry. 3. 1/16 in. from case for 5 seconds. Thermal Resistance Thermal Resistance: e Package: Notes: 1. MOSFET only – controller junction temperature (TC) may be less than the power MOSFET junction temperature (TM).

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Line-Sense/Peak Detector Brown-In Threshold Current IUV+ 0 °C < TC < 100 °C 27.50 28.88 mA Brown-Out Threshold Current I UV- 0 °C < TC < 100 °C 22.52 24.50 mA Brown-In/Out Hysteresis I UV(HYST) TC = 25 °C 1 5.5 mA Soft-Start Brown-Out Threshold Current I UV-SS TC = 25 °C 20.5 22.5 24.5 mA VOLTAGE MONITOR Pin Voltage Threshold V V(THR) 0 °C < TC < 100 °C IV = IUV+ 2.3 V VOLTAGE MONITOR Pin Short-Circuit Current I V(SC) 0 °C < TC < 100 °C VV = 6 V 350 mA VOLTAGE MONITOR Pin Pre-Soft-Start Current I V(SS) 0 °C < TC < 100 °C VV = 3 V 6 mA Maximum Line Sample Refresh Period TREFRESH TC = 25 °C 30 60 ms VOLTAGE MONITOR Pin Shutdown Current Threshold I V(OFF) 0 °C < TC < 100 °C 200 mA VOLTAGE MONITOR Pin Shutdown Delay t V(OFF) TC = 25 °C 65 110 135 ms

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection Over-Current Protection IOCP PFS704 di/dt = 250 mA/ms TC = 25 °C IV < 48 mA 3.8 4.1 4.3 A IV > 59 mA 2.5 2.7 2.8 PFS706 di/dt = 300 mA/ms TC = 25 °C IV < 48 mA 4.5 4.8 5.1 IV > 59 mA 3.0 3.2 3.4 PFS708 di/dt = 400 mA/ms TC = 25 °C IV < 48 mA 5.5 5.9 6.2 IV > 59 mA 3.7 4.0 4.2 PFS710 di/dt = 500 mA/ms TC = 25 °C IV < 48 mA 6.8 7.2 7.5 IV > 59 mA 4.6 4.9 5.1 PFS712 di/dt = 650 mA/ms TC = 25 °C IV < 48 mA 8.0 8.4 8.8 IV > 59 mA 5.4 5.7 6.0 PFS714 di/dt = 800 mA/ms TC = 25 °C IV < 48 mA 9.0 9.5 9.9 IV > 59 mA 6.0 6.3 6.6 PFS716 di/dt = 920 mA/ms TC = 25 °C IV < 48 mA 9.5 10.0 10.5 IV > 59 mA 6.3 6.7 7.0 PFS723 di/dt = 250 mA/ms TC = 25 °C 3.8 4.1 4.3 PFS724 di/dt = 300 mA/ms TC = 25 °C 4.5 4.8 5.1 PFS725 di/dt = 400 mA/ms TC = 25 °C 5.5 5.9 6.2 PFS726 di/dt = 500 mA/ms TC = 25 °C 6.8 7.2 7.5 PFS727 di/dt = 650 mA/ms TC = 25 °C 8.0 8.4 8.8 PFS728 di/dt = 800 mA/ms TC = 25 °C 9.0 9.5 9.9 PFS729 di/dt = 920 mA/ms TC = 25 °C 9.7 10.2 10.7

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Current Limit/Circuit Protection (cont.) SOA Protection Time-out tOCP TC = 25 °C 200 280 360 ms SOA On-time tSOA See Note A 1 ms Leading Edge Blanking Time t LEB See Note A 220 ns Current Limit Delay tIL(D) See Note A 100 ns LEB + ILD + Driver Delay tLEB + tIL(D) + tDRIVER TC = 25 °C 370 470 570 ns Thermal Shutdown Temperature TSHUT See Note A 111 118 126 °C Thermal Shutdown Hysteresis T HYST See Note A 50 °C FEEDBACK Pin Undervoltage FBUV TC = 25 °C 3 3.5 4 V FEEDBACK Pin Undervoltage Delay t FB(UV) TC = 25 °C 65 110 135 ms FEEDBACK Pin Overvoltage Threshold and Hysteresis FB OV 0 °C < TC < 100 °C Threshold VFB +40 mV VFB +90 mV VFB +160 mV V 0 °C < TC < 100 °C Hysteresis 75 mV FEEDBACK Pin Overvoltage Delay t FB(OV) TC = 25 °C 1 2 3 ms FEEDBACK Pin Start-Up Threshold FBOFF 0 °C < TC < 100 °C 0.5 1.2 1.65 V FEEDBACK Pin OFF Delay t FB(OFF) 0 °C < TC < 100 °C 0.5 2 4 ms Start-Up VCC (Rising Edge) VCC+ TC = 25 °C 9.5 10.2 V Shutdown VCC (Falling Edge) VCC- TC = 25 °C 9.0 9.5 V VCC Hysteresis VCC(HYST) TC = 25 °C 0.2 0.5 0.8 V Supply Current Characteristics I CD1 0 °C < TC < 100 °C Switching 3.5 mA ICD2 0 °C < TC < 100 °C Not Switching 1.5 VCC Power-Up Reset Threshold VCC(POR) TC = 25 °C 2.85 3.6 4.25 V VCC Power-Up Reset Current IVCC(POR) TC = 25 °C 1.5 mA

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Power MOSFET ON-State Resistance RDS(ON) PFS704 ID = IOCP × 0.5 See Note E TM = 25 °C 0.61 0.72 W TM = 100 °C 1.16 PFS706 TM = 25 °C 0.52 0.61 TM = 100 °C 0.97 PFS708 TM = 25 °C 0.41 0.48 TM = 100 °C 0.77 PFS710 TM = 25 °C 0.35 0.41 TM = 100 °C 0.65 PFS712 TM = 25 °C 0.30 0.35 TM = 100 °C 0.55 PFS714 TM = 25 °C 0.26 0.31 TM = 100 °C 0.48 PFS716 TM = 25 °C 0.22 0.26 TM = 100 °C 0.42 PFS723 TM = 25 °C 0.58 0.69 TM = 100 °C 1.10 PFS724 TM = 25 °C 0.49 0.58 TM = 100 °C 0.92 PFS725 TM = 25 °C 0.39 0.46 TM = 100 °C 0.73 PFS726 TM = 25 °C 0.33 0.39 TM = 100 °C 0.62 PFS727 TM = 25 °C 0.28 0.33 TM = 100 °C 0.52 PFS728 TM = 25 °C 0.25 0.29 TM = 100 °C 0.46 PFS729 TM = 25 °C 0.21 0.25 TM = 100 °C 0.40

Rev. D 12/11 PFS704-729EG www.powerint.com Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Power MOSFET (cont.) Effective Output Capacitance COSS TC = 25 °C, VGS = 0 V, VDS = 0 to 80% VDSS See Note A PFS704 176 pF PFS706 210 PFS708 265 PFS710 312 PFS712 320 PFS714 420 PFS716 487 PFS723 185 PFS724 221 PFS725 278 PFS726 328 PFS727 389 PFS728 441 PFS729 511 Breakdown Voltage BVDSS TM = 25 °C, VCC = 12 V ID = 250 mA, VFB = VV = 0 V 530 V Breakdown Voltage Temperature Coefficient BV DSS(TC) 0.048 %/°C

Rev. D 12/11 PFS704-729EG www.powerint.com NOTES: A. Not a tested parameter. Guaranteed by design. B. Tested in typical boost PFC application circuit with 0.1 mF capacitor between the V pin and G pin and a 4 MW resistor from rectified line to the V pin for PFS70x and PFS71x. C. Tested in typical boost PFC application circuit with 0.047 mF capacitor between the V pin and G pin and a 9 MW resistor from rectified line to the V pin for PFS72x. D. Normally limited by internal circuitry. E. Refer to IOCP with IV <48 mA for PFS704-716. Parameter Symbol Conditions SOURCE = 0 V; TC = -40 °C to 125 °C (Note D) (Unless Otherwise Specified) Min Typ Max Units Power MOSFET (cont.) OFF-State Drain Current Leakage IDSS TM = 100 °C VDS = 80% BVDSS VCC = 12 V VFB = VV = 0 PFS704 80 mA PFS706 100 PFS708 120 PFS710 150 PFS712 170 PFS714 200 PFS716 235 PFS723 84 PFS724 105 PFS725 126 PFS726 158 PFS727 179 PFS728 210 PFS729 247 Turn-Off Voltage Rise Time t R See Note A, B, C ns Turn-On Voltage Fall Time t F 100 Start-up Time Delay tSTART-DELAY 0 °C < TC < 100 °C See Note A, B, C 2 6 10 ms

0 PFS704

Figure 20. Thermal Resistance (qJC ). Figure 21. Typical Characteristic: VOL TAGE MONITOR Pin Voltage vs. Current. Figure 22. Typical Characteristic: FEEDBACK Pin Current vs. V oltage.

Figure 23. Typical Characteristic: VCC Pin Current vs. V oltage (Device not Switching).

Rev. D 12/11 PFS704-729EG www.powerint.com PI-5711-110810 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.007 (0.18) per side. 3. Dimensions noted are inclusive of plating thickness. 4. Does not include interlead flash or protrusions. 5. Controlling dimensions in inches (mm). eSIP-7G (E Package) 0.378 (9.60) Ref. 0.019 (0.48) Ref. 0.027 (0.70) 0.023 (0.58) 0.020 (0.50) 0.060 (1.52) Ref. 10° Ref. All Around 0.016 (0.41) Ref. 0.290 (7.37) Ref. Detail A 0.047 (1.19) Pin 1 I.D. 0.118 (3.00) FRONT VIEW SIDE VIEW BACK VIEW Detail AEND VIEW 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 6×0.016 (0.41) 0.011 (0.28) 0.020 M 0.51 M C 0.403 (10.24) 0.397 (10.08) 0.021 (0.53) 0.046 (1.17) 0.325 (8.25) 0.320 (8.13) C A B 0.221 (5.61) Ref. 0.519 (13.18) Ref. 0.100 (2.54) 0.211 (5.36) Ref. 0.207 (5.26) 0.187 (4.75) 6×0.033 (0.84) 0.028 (0.71) 0.010 M 0.25 M C A B 4A A 3 MOUNTING HOLE PATTERN (not to scale) PIN 7 PIN 1 0.059 (1.50) 0.059 (1.50) 0.050 (1.27) 0.050 (1.27) 0.100 (2.54) 0.155 (3.93)

Rev. D 12/11 PFS704-729EG www.powerint.com Part Marking Information

• HiperPFS Product Family
• PFS Series Number
• Package Identifier E Plastic eSIP-7G
• Pin Finish G Halogen Free and RoHS Compliant Part Ordering Information Part Number Option Quantity PFS704EG Tube 48 PFS706EG Tube 48 PFS708EG Tube 48 PFS710EG Tube 48 PFS712EG Tube 48 PFS714EG Tube 48 PFS716EG Tube 48 PFS723EG Tube 48 PFS724EG Tube 48 PFS725EG Tube 48 PFS726EG Tube 48 PFS727EG Tube 48 PFS728EG Tube 48 PFS729EG Tube 48 PFS 704 E G

A Initial Release. 11/09/10 B Updated Figure 9 and deleted sentence on page 7. 02/11 C Updated FEEDBACK pin voltage rating in Absolute Maximum Rating table. 02/11 D Updated Inductor Design paragraph on page 12 and BVDSS(TC). 12/11 For the latest updates, visit our website: www.powerint.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered complete list of Power Integrations patents may be found at www.powerint.com. Power Integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: 1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS, HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, StakFET, PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2011, Power Integrations, Inc. Power Integrations Worldwide Sales Support Locations World Headquarters

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