PFS5173F POWERINT | Alldatasheet
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5 V GATE DRIVER
Figure 3. Functional Block Diagram.
Rev. C 03/22 PFS5173-5178/5274 www.power.com Pin Functional Description VALLEY SENSING (VS) Pin (Pin 1) This pin is used to sense voltage on the auxiliary winding of the PFC inductor. The VS pin is connected to the auxiliary winding on a PFC inductor through an external resistor. The voltage on the auxiliary winding on a PFC inductor provides the controller information about the drain voltage. The external resistor is used to limit the current through VS pin and for fine adjustment of timing for valley switching. SIGNAL GROUND (G) Pin (Pin 2, 13) Discrete components used in the feedback circuit, including loop compensation, decoupling capacitors for the BIAS POWER (VCC), REFERENCE (REF) and VOLTAGE MONITOR (V) must be referenced to the SIGNAL GROUND (G) pin. The SIGNAL GROUND pin is also connected to the exposed pad of the device. The SIGNAL GROUND pin should not be tied directly to the SOURCE pin external to the IC. T Pin (Pin3) Must be connected to REF pin. VOLTAGE MONITOR (V) Pin (Pin 4) The VOLTAGE MONITOR pin is tied to the rectified high-voltage DC rail through a 100:1, 1% high-impedance resistor divider to minimize power consumption in standby. The recommended resistance value is between 8 MΩ and 16 MΩ. Changing this divider ratio affects the input current waveform, reduces power factor and increases THD. A small ceramic capacitor forming an 80 µs time constant must be connected between the VOLTAGE MONITOR pin and the SIGNAL GROUND pin to bypass any switching noise present on the rectified DC bus. This pin also features brown-in/out detection thresholds and incorporates a weak current source that acts as a pull-down in the event of an open-circuit condition. COMPENSATION (C) Pin (Pin 5) This pin is used for loop pole/zero compensation of the OTA error amplifier via a network of capacitors and a resistor between the COMPENSATION pin and SIGNAL GROUND pin. FEEDBACK (FB) Pin (Pin 6) This pin is connected to the main voltage regulation feedback resistor divider network and is also used for fast over and undervoltage protection. This pin also detects the presence of the feedback voltage divider network at start-up. The divider ratio should be the 400/3.85 to ensure that nominal PFC output voltage is 400 V. Positioning a large upper resistor between 8 M Ω and 16 MΩ ±1% is recommended. A small ceramic capacitor between FEEDBACK and SIGNAL GROUND, forming a 80 µs time-constant with the bottom resistor, is required. POWER GOOD (PG) Pin (Pin 7) Use of the PG function is optional for PFS517xF. The POWER GOOD pin is an active low, open-drain connection which sinks current when the output voltage is in regulation. At start-up, once the FEEDBACK pin voltage has risen to ~95% of the internal reference voltage, the POWER GOOD pin is asserted low. After start-up, the output voltage threshold at which the PG signal becomes high-impedance and depends on the threshold programmed by the POWER GOOD THRESHOLD pin resistor. When not used, the POWER GOOD pin should be left floating. For PFS527xF this pin is used to implement the boost follower feature. This is an active low, open-drain connection which sinks current when the peak detected input voltage is determined to be high-line. Connect an additional feedback resistor RBF between BF pin and the FB pin to change the output voltage between low-line and high-line inputs. This feature improves efficiency particularly at low-line AC input. POWER GOOD THRESHOLD (PGT) Pin (Pin 8) This pin is used to program the output voltage threshold at which the PG signal becomes high-impedance representing the PFC stage falling out of regulation. The low threshold for the PG signal is programmed with a resistor between the POWER GOOD THRESHOLD and SIGNAL GROUND pins. Tying the POWER GOOD THRESHOLD to the REFERENCE pin disables the power good function (i.e. POWER GOOD pin remains high impedance). In boost follower mode, the PGT pin has no function and should be connected to REFERENCE pin. POWER SELECTION (PS) Pin (Pin 9) This pin is used to program the output power of the HiperPFS-5. The power is programmed with a resistor connected to the SIGNAL GROUND pin. The power is programmed in 10% steps, between 70% to 100% of nominal power. VPP Pin (Pin 10) Must be connected to REF pin. REFERENCE (R) Pin (Pin 11) This pin is connected to an external bypass capacitor. The voltage on this pin is nominally 5 V and is used to supply the control circuitry inside PFS PowiGaN. DRIVER VCC DECOUPLING (VDR) Pin (Pin 12) This pin is connected to an external bypass capacitor. There is an internal linear regulator which supplies the VDR pin with a regulated voltage of (5 V nominally). This voltage is used to supply the driver section of the PFS PowiGaN controller. BIAS POWER (VCC) Pin (Pin 14) This is the input for the 6.5-35 VDC bias supply used to power the IC. The maximum operating voltage must be externally clamped to prevent the BIAS POWER pin from exceeding 35 VDC. X CAPACITOR DISCHARGE TERMINAL D1 (Pin 15-16) Connected together internally to one terminal of the X capacitor. These two pins are connected together with a bond wire inside package. For selection of the discharge resistors follow the recommendations in CAPZero-2 data sheet. X CAPACITOR DISCHARGE TERMINAL D2 (Pin 18-19) Connect one pair of pins via a series resistor to each side of the X capacitor. These two pins are connected together internally with a bond wire inside package. To select the values for the discharge resistors follow the recommendations in the CAPZero-2 data sheet.
negative bulk capacitor terminal connection. This is the drain connection for the internal power switch. provides a thermal path for cooling of the power switch. Figure 4. Pin Configuration.
14 VCC
12 VDR
11 REF
10 VPP
8 PGT
with regulatory harmonic current limits and (high power factor). the boost inductor and thus regulates the output voltage and power. fundamental requirement for power factor correction. proportional to the input voltage. network, and improve power factor. switch power limit over the input line range. Figure 5. Idealized Converter Waveforms.
requests a turn-on, it immediately turns on the PowiGaN switch. and the point when the PowiGaN power switch is actually turned on. of 1 µs) and distortion of the input current is the most pronounced. the voltage on the VDR pin to 5.25 V. The voltage on the VDR pin is used to supply the internal controller. high-frequency impedance path to ground. voltage on the VCC pin form the external bias circuit is established. control circuitry and disable the self-supply circuit. above the brown-in threshold, the engine enables switching. the maximum overshoot and undershoot during load transient events. during start-up, resulting in a soft controlled start-up. in the PFC inductor if the control loop requires larger duty cycle. temperature status is confirmed to be false. determined the switching is enabled. Figure 6. Start-up Flow Chart.
load to minimize the burden on EMI components. Figure 9. EcoSmart Frequency Sliding VOFF vs. VERR and VOFF(MAX) vs. Input Voltage. high-impedance state (internal switch is in off-state). PFC output falls out of regulation. output voltage has fallen below the user programmed V PG- threshold. fallen below the VFB(UV) threshold for greater than t FB(UV) seconds.
the PowiGaN happens at the valley of the voltage on the DRAIN pin. effective capacitance on the VS pin is smaller with a shorter delay. brown-in point and above input peak voltages of 400 V PK. feature will not be activated. the bridge rectifier and prevent false restarts. Table 2. Power Programming Resistances (Resistor between PS pin and G pin). expires a shutdown will occur. representative of a sine wave or a high-duty-cycle square wave. (UPS) square wave is detected. above the VCCUVLO+ threshold. until the BIAS POWER pin voltage has fallen below the VCC UVLO- level. the converter from output short-circuit or overload fault conditions. levels as a function of VOLTAGE MONITOR pin line sense. for auxiliary winding is ranged from 10 to 15.
set-points if the drop-out exceeds 37 ms (nominal). is small resulting in too little inductor reset time. response), to prevent hazardous voltage conditions from occurring. drop of 10 V) before switching is re-started. regulation components (FEEDBACK pin divider). will re-initiate the start-up sequence. Figure 13. Line Dependent OCP.
other AC input line input through a separate external resistor. existing systems where X capacitor discharge function is not used. capacitor discharge function is not disabled. Table 3. X Capacitance and Discharge Resistance. capacitor discharge function. Table 4. Single Point of Failure (SPOF) Tests as Pertaining to Failure Modes of the X Capacitor Discharge. HiperPFS-5 Device Passes Both Tests.
Rev. C 03/22 PFS5173-5178/5274 www.power.com Absolute Maximum Ratings 1,2 Notes: 1. All voltages referenced to SOURCE, TA = 25 °C 2. Maximum ratings specified may be applied one at a time without causing permanent damage to the product. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect product reliability. 3. Self-supply not active. 4. Normally limited by internal circuitry. 5. 1/16” from case for 5 seconds. 6. Non-repetitive pulse. 7. Voltage of D1 pin relative to D2 pin in either polarity. 8. The peak current is allowed while the D1/D2 voltage is simultane- ously less than 400 V. Thermal Resistance Thermal Resistance: PFS5x73F PFS5x78F Notes: 2. Soldered to 1 sq. inch (645 mm2), 2 oz. (610 g/m2) copper clad. 3. The case temperature is measured at the bottom of the package body on the exposed pad. Parameter Symbol Conditions SOURCE = 0 V, TJ = -40 to +125 °C (See Note C) Pin Min Typ Max Units Currents Current Consumption – In Burst Mode No Switching ICC(BURST) VCC = 12 V, FB = 3.85 V, C < VERR_MIN 0 °C < TJ < 100 °C V = 1.414 V VCC 720 µA Leakage Current in UVLO State Ioz 0 °C < Pin Voltage < REF TJ = 25 °C VDR < VDRUV+ V, FB, C, PGT ±10 nA VPG = REF TJ = 25 °C VPG = V PG ±0.1 µA Pull-Down Current on Feedback IFB(PD) 0 °C < TJ < 100 °C VFB = 5 V FB 100 150 nA
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units Control Functions Maximum Operating “On-Time” Controller tON(MAX) 34 µs Maximum Operating “Off-Time” Controller tOFF(MAX) No valleys detected on the VS pin (operation in CCM mode) 248 µs Feedback Internal Feedback Error Voltage Reference VFB(REF) TJ = 25 °C 3.82 3.85 3.88 V Feedback Error-Amplifier Transconductance Gain Gm 3.75 V < VFB < 3.95 V 0 ºC < TJ < 100 °C C = 4 V 75 90 105 µA/V Soft shutdown Time tSHUTDWN See Note A 1.00 1.16 ms FEEDBACK Pin Start-Up/ Fault Threshold VFB(OFF) 0 ºC < TJ < 100 °C 0.64 0.71 V FEEDBACK Pin Undervoltage Assertion Threshold VFB(UV) 0 ºC < TJ < 100 °C 2.09 2.25 2.36 V FEEDBACK Pin Overvoltage Assertion Threshold VFB(OV+) 0 ºC < TJ < 100 °C 4.00 4.10 4.20 V FEEDBACK Pin Overvoltage Deassertion Relative Threshold VFB(OV+REL_FB) 0 ºC < TJ < 100 °C VFB(REF) +0.245 V FEEDBACK Pin Overvoltage Deassertion Threshold VFB(OV-) 0 ºC < TJ < 100 °C 4.00 4.10 V FEEDBACK Pin Overvoltage Deassertion Relative Threshold VFB(OV-REL_FB) 0 ºC < TJ < 100 °C VFB(REF) +0.16 V FEEDBACK Pin Overvoltage Hysteresis VFB(OVHYST) 0 ºC < TJ < 100 °C 0.085 V Voltage on C Pin That Triggers Switching During a Burst-Mode Recovery, or When Commencing Soft-Start (COMPENSATION Pin Burst Disable Threshold) VERR(MIN+) 0 ºC < TJ < 100 °C 0.2 V Voltage on C Pin That Suppresses Switching, Causing the Device to Enter Burst-Mode (Burst Enable Threshold) VERR(MIN-) 0 ºC < TJ ≤ 100 °C 0.1 V Hysteresis of VERR_MIN (COMPENSATION Pin Burst Threshold Hysteresis) VERR(HYST) VERR_MIN+ - VERR_MIN- 0 ºC < TJ < 100 °C 0.09 V
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units Line Sense / Peak Detector Line Sense and Peak detector input voltage (Line-Sense Input Voltage Range) VV(RANGE) The voltage on V may exceed the upper specification, however the line sense function is saturated at its full scale. Not tested. 4 V Brown-In Threshold Voltage VBR+ 0 ºC < TJ < 100 °C 1.12 V Brown-In Threshold Voltage VBR- 0 ºC < TJ < 100 °C 0.97 V Brown-Out Threshold for Square Wave (Brown-Out Threshold for High Duty Cycle Square Wave) VBR(SQ) 0 ºC < TJ < 100 °C 0.86 V Soft-Start Brown-Out Threshold Voltage (Start-Up Brown-Out Threshold Voltage (During NTC Warm-Up Time)) VBR(NTC) 0 ºC < TJ < 100 °C 0.74 V Brown-In/Out Hysteresis (VBR+ - VBR-) (Brown-In / Out Hysteresis (After NTC Warm-Up Time) VBR(HYST) 0 ºC < TJ < 100 °C 130 145 160 mV Brown-Out Debounce Timer tBrown-Out See Note A 54 66 ms Brown-Out Debounce Timer During Start-Up with VBR_NTC Threshold tBrown-Out(NTC) Triggered during startup (while tSTARTUP is active) if the peak of the V pin is lower than VBR-NTC. 1000 1160 ms Start-Up Timer for Using Lower Brown-Out Threshold (VBR-NTC) tSTART-UP The timer is triggered when switching starts. The timer aborts when a peak < V BR-NTC. The timer restarts at zero when a peak > V BR-NTC. When timer expires, the higher brown-out threshold VBR- is applied 1000 1160 ms V Pin High-Line Threshold VV(HIGH+) (170 VAC) 2.42 V V Pin High-Line Deassertion Threshold VV(HIGH-) (140 VAC) 2.00 V
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units Current Limit / Circuit Protection Over-Current Protection Limit1 IOCP TJI = 0 °C to 100 °C Full Power A di/dt = 293 mA/µs PFS5x73F VV < 2 V 3.1 VV > 2.42 V 2.1 di/dt = 437 mA/µs PFS5x74F VV < 2 V 4.4 VV > 2.42 V 3.0 di/dt = 494 mA/µs PFS5x75F VV < 2 V 5.2 VV > 2.42 V 3.6 di/dt = 627 mA/µs PFS5x76F VV < 2 V 6.6 VV > 2.42 V 4.7 di/dt = 703 mA/µs PFS5x77F VV < 2 V 7.4 VV > 2.42 V 5.2 di/dt = 836 mA/µs PFS5x78F VV < 2 V 9.3 VV > 2.42 V 7.3 Over-Current Protection Limit1 IOCP TJI = 0 °C to 100 °C 90% Full Power A di/dt = 263 mA/µs PFS5x73F VV < 2 V 2.8 VV > 2.42 V 1.9 di/dt = 393 mA/µs PFS5x74F VV < 2 V 4.0 VV > 2.42 V 2.8 di/dt = 445 mA/µs PFS5x75F VV < 2 V 4.7 VV > 2.42 V 3.3 di/dt = 564 mA/µs PFS5x76F VV < 2 V 6.0 VV > 2.42 V 4.2 di/dt = 633 mA/µs PFS5x77F VV < 2 V 6.7 VV > 2.42 V 4.7 di/dt = 752 mA/µs PFS5x78F VV < 2 V 8.4 VV > 2.42 V 6.6
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units Current Limit / Circuit Protection (cont.) Over-Current Protection Limit1 IOCP TJI = 0 °C to 100 °C 80% Full Power A di/dt = 234 mA/µs PFS5x73F VV < 2 V 2.5 VV > 2.42 V 1.7 di/dt = 350 mA/µs PFS5x74F VV < 2 V 3.5 VV > 2.42 V 2.5 di/dt = 395 mA/µs PFS5x75F VV < 2 V 4.2 VV > 2.42 V 2.9 di/dt = 500 mA/µs PFS5x76F VV < 2 V 5.3 VV > 2.42 V 3.7 di/dt = 562 mA/µs PFS5x77F VV < 2 V 6.0 VV > 2.42 V 4.2 di/dt = 669 mA/µs PFS5x78F VV < 2 V 7.4 VV > 2.42 V 5.8 Over-Current Protection Limit1 IOCP TJI = 0 °C to 100 °C 70% Full Power A di/dt = 205 mA/µs PFS5x73F VV < 2 V 2.2 VV > 2.42 V 1.5 di/dt = 306 mA/µs PFS5x74F VV < 2 V 3.1 VV > 2.42 V 2.2 di/dt = 346 mA/µs PFS5x75F VV < 2 V 3.7 VV > 2.42 V 2.6 di/dt = 439 mA/µs PFS5x76F VV < 2 V 4.7 VV > 2.42 V 3.3 di/dt = 492 mA/µs PFS5x77F VV < 2 V 5.3 VV > 2.42 V 3.7 di/dt = 585 mA/µs PFS5x78F VV < 2 V 6.5 VV > 2.42 V 5.1 SOA Protection Fixed Off-Time tOFF(SOA) TJ = 25 °C See Note A 200 250 300 µs Leading Edge Blanking (LEB) Time Period tLEB TJ = 25 °C See Note A 750 ns Minimum On-Time in IOCP tON_OCP(MIN) TJ = 25 °C 800 ns
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units VCC parameters PFS527xF Parts (Parts without high voltage start-up power supply circuit) VCC Operating Range VCC 0 °C < TJ < 100 °C 7.0 12.0 35.0 V Series Regulator PFS527XF Parts REFERENCE Pin Voltage VDR Pin Voltage VREF VVDR VCC > 6.3 V 0°C < TJ < 100 °C No external load applied on REF and VDR 5.25 V VDR Pin Start-Up Threshold VVDR(UV+) 0 °C < TJ < 100 °C 5.0 V VDR UVLO Hysteresis VVDR(UV)(HYST) 50 mV VCC Parameters PFS517xF Parts (Parts with high voltage start-up power supply circuit) VCC Operating Range VCC 0 °C < TJ < 100 °C 7.0 12.0 35.0 V VCC Takes Over VDR and Reference Supply From High-Voltage Regulator From the D Pin VCCTO+ VD > 20 V, VCC rising from 0 V TJ = 25 °C 6.3 V Series Regulator PFS517xF Parts REFERENCE Pin Voltage VDR Pin Voltage (VDR and REFERENCE pin Supplied From VCC Pin VREF(VCC) VVDR(VCC) VCC > 6.3 V, VD = 0 V to 400 V 0 °C < TJ < 100 °C 5.25 V REFERENCE Pin Voltage VDR Pin Voltage (VDR and REFERENCE Pin Supplied Through High-Voltage Regulator from the D pin) VREF(VD) VVDR(VD) VCC = 0 V, VD > 20 V 0 °C < TJ < 100 °C 5.15 V VDR Pin Start-up Threshold VVDR(UV+) 0 °C < TJ < 100°C See Note A 5.0 V Reference VDR UVLO hysteresis VVDR(VH)(HYST) See Note A 50 mV Time from VREF > VREFUV+ Until Device Commences Switching tRESET Assumes V pin is above brown-in threshold. See Note A 1.6 3 ms Valley Sensing Valley Sensing Positive Threshold VVS1 Voltage on the VS pin rising TJ = 25 °C 0.88 V Valley Sensing Negative Threshold VVS2 Voltage on the VS pin falling TJ = 25 °C 0.48 V
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units Power Good PFS517x Parts Power Good Threshold Set Reference Current (Power Good Deassertion Threshold Output Reference Current) IPG(T) 0 °C < TJ < 100 °C; VPGT = 3.0 V -10 µA Power Good Delay Time (From FB > VPG+ to PG < 1 V) tPG 0 °C < TJ < 100 °C; PG = 20 kΩ pull-up to
12 V from FB > VPG+ to PG < 1 V
<15 µs Power Good State Change Deglitch Time tPG(D) TJ = 25 °C; Applies to rising and falling transitions on the power good comparator and detection of an open PGT pin. See Note A 81 µs Power Good Internal Reference Threshold (Start-up Threshold) (Power Good Internal Assertion Threshold) VPG+ 0 °C < TJ < 100 °C 3.55 3.65 3.75 V Power Good Relative Threshold VPG+REL(FB) 0 °C < TJ < 100 °C VFBREF -0.2 V Power Good Deassertion Threshold VPG(VOL) V (PGT) = 3 V 0 °C < TJ < 100 °C V (PGT) ±30 mV V Power Good Pin Leakage Current in Off-State IPG(OFF) FB < VPG(-) 0 °C < TJ < 100 °C 100 nA Power Good On-State Voltage VPG- 0 °C < TJ < 100 °C IPG = 1.0 mA; FB = 3.85 V 2 V Thermal Protection (OTP) Controller Junction Temperature for Shutdown TOTP+ Soft-shutdown is triggered when the silicon exceeds this temperature See Note A 138 °C Controller Junction Temperature for Restart TOTP- Restart occurs if OTP hysteresis is enabled when the silicon drops below this temperature See Note A 81 °C Over-Temperature Hysteresis TOTP(HYST) V > VBR+ See Note A 57 °C
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +125 °C (See Note C) Min Typ Max Units PowiGaN Cascode On-State Resistance RDS(ON) ID = 0.5 X IOCP See Note 1 PFS5x73F TJ(M) = 25 °C 0.51 Ω PFS5x74F TJ(M) = 25 °C 0.30 PFS5x75F TJ(M) = 25 °C 0.23 PFS5x76F TJ(M) = 25 °C 0.17 PFS5x77F TJ(M) = 25 °C 0.14 PFS5x78F TJ(M) = 25 °C 0.11 Charge Effective Output Capacitance COSS(CH) TJ = 25 °C VGS = 0 V, VDS = 0 to 400 V PFS5x73F 26.1 pF PFS5x74F 39.5 PFS5x75F 51.3 PFS5x76F 67.1 PFS5x77F 89.5 PFS5x78F 123 Energy Effective Output Capacitance COSS(EN) TJ = 25 °C VGS = 0 V, VDS = 0 to 400 V PFS517xF 18.1 pF PFS5x74F 26.4 PFS5x75F 35.6 PFS5x76F 46.4 PFS5x77F 62.4 PFS5x78F 92.5 Off-State Drain Current Leakage IDSS TJ = 1 00 °C VDS = 80% VCC = 12 V VFB = VV = VC = 0 PFS517xF PFS527xF 100 µA
Rev. C 03/22 PFS5173-5178/5274 www.power.com Parameter Symbol Conditions SOURCE = 0 V, VCC = 12 V, TJ = -40 to +105 °C (See Note C) Min Typ Max Units X Capacitor Discharge D1/D2 Function Supply Current ISUPPLY TJ = 25 °C 21.7 µA Saturation Current A, D IDSAT 2.5 mA AC Removal Detection Time tDET Line Cycle Frequency 47-63 Hz 22 31.4 ms NOTES: A. Not Tested Parameter. Guaranteed by Design. B. Tested in Typical Boost PFC Application Circuit C. Normally limited by internal circuitry D. Saturation current specifications ensure a natural RC discharge characteristic at all voltages up to 265 VAC peak with the external resistor values specified in component selection table.
Rev. C 03/22 PFS5173-5178/5274 www.power.com InSOP-T28F TOP VIEW BOTTOM VIEW 0° – 8° Notes: 1. Dimensioning and Tolerancing per ASME Y14.5M – 1994. 2. Dimensions in millimeters. 3. Dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. Maximum mold protrusion is 0.18 per side. 4. Dimensions noted include plating thickness. 5. Dimensions noted do not include inter-lead flash or protrusions. 6. Lead #21 centerline does not coincide with package body centerline. 7. Exposed pad dimensions are centered about the plastic body centerlines as shown. 8. Creepage dimension includes package body side-contour dimensions as shown in Detail A. Minimum creepage is 3.20 mm. 9. This dimension is the nominal dimension between lead tips, not including plating, and not including metal protrusions. Minimum metal-to-metal distance (creepage) is 3.20 mm. POD_inSOP-T28F_Rev A_032922 PI-9480-032922 SIDE VIEW END VIEW DETAIL A 0.53 Ref. 0.28 Ref. 0.37 Ref. Gauge Plane Seating Plane Exposed Pad 3.41 Ref. 0.83 0.53 0.85 0.75 0.15 0.00 Standoff 1.315 Ref. 2.16 Max. Total Mounting Height 2.01 1.81 Body Thickness Detail A 0.30 0.18
20 Leads
8.90 Ref. 28 21 19 18 16 15 0.55 0.45 0.30 0.20 7.64 Ref. 9.40 14 1 B 4 5 4 5 13.43 0.63 1.535 Leads 15–16 and 18–19 Leads 1–19 10.80 0.04 3.36 Ref. 0.63 0.315 141 0.25 4 5 1.26 4.01 0.15 C
6 Lead Tips
0.15 C 0.10 C
0.10 C A
0.10 C B
14 Lead Tips
0.25 M C A B 0.25 M C A B
0.25 M C A B
Coplanarity: 20 Leads Pin #1 I.D. C H A
Rev. C 03/22 PFS5173-5178/5274 www.power.com PI-9436-092421 InSOP-T28F A. Power Integrations Registered Trademark B. Assembly Date Code (last two digits of year (YY) followed by 2-digit work week (WW)), and Supply Chain Flow (Foundry / Assembly Location (X)) C. Product Identification (Part #/Package Type) D. Lot Identification Code PACKAGE MARKING A B C D 1531 PFS5178F 004D842A1
Rev. C 03/22 PFS5173-5178/5274 www.power.com Part Ordering Information
- HiperPFS Product Family
- HiperPFS-5 Series Number
- Package Identifier F InSOP-T28F
- Tape & Reel and Other Options TL Tape & Reel, 2 k pcs per reel.PFS 5178 F - TL Part Ordering Table Part Number Option Quantity PFS5173F-TL Reel 2000 PFS5x74F-TL Reel 2000 PFS5x75F-TL Reel 2000 PFS5x76F-TL Reel 2000 PFS5177F-TL Reel 2000 PFS5178F-TL Reel 2000 MSL Table Part Number MSL Rating PFS5173F-TL 3 PFS5x74F-TL 3 PFS5x75F-TL 3 PFS5x76F-TL 3 PFS5177F-TL 3 PFS5178F-TL 3 PFS5274F-TL 3 PFS5275F-TL 3 PFS5276F-TL 3
C Code L release. 03/22 For the latest updates, visit our website: www.power.com Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS. Patent Information The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set forth at www.power.com/ip.htm. Life Support Policy POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein: A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in significant injury or death to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Power Integrations, the Power Integrations logo, CAPZero, ChiPhy, CHY, DPA-Switch, EcoSmart, E-Shield, eSIP, eSOP, HiperLCS, HiperPLC, HiperPFS, HiperTFS, InnoSwitch, Innovation in Power Conversion, InSOP, LinkSwitch, LinkZero, LYTSwitch, SENZero, TinySwitch, TOPSwitch, PI, PI Expert, PowiGaN, SCALE, SCALE-1, SCALE-2, SCALE-3 and SCALE-iDriver, are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies. ©2022, Power Integrations, Inc. World Headquarters
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Phone: +39-024-550-8701 e-mail: eurosales@power.com Japan Yusen Shin-Yokohama 1-chome Bldg. 1-7-9, Shin-Yokohama, Kohoku-ku Yokohama-shi, Kanagawa 222-0033 Japan Phone: +81-45-471-1021 e-mail: japansales@power.com Korea RM 602, 6FL Korea City Air Terminal B/D, 159-6 Samsung-Dong, Kangnam-Gu, Seoul, 135-728, Korea Phone: +82-2-2016-6610 e-mail: koreasales@power.com Singapore
51 Newton Road
#19-01/05 Goldhill Plaza Singapore, 308900 Phone: +65-6358-2160 e-mail: singaporesales@power.com Taiwan 5F, No. 318, Nei Hu Rd., Sec. 1 Nei Hu Dist. Taipei 11493, Taiwan R.O.C. Phone: +886-2-2659-4570 e-mail: taiwansales@power.com UK Building 5, Suite 21 The Westbrook Centre Milton Road Cambridge CB4 1YG Phone: +44 (0) 7823-557484 e-mail: eurosales@power.com Power Integrations Worldwide Sales Support Locations Germany (AC-DC/LED/Motor Contorl Sales) Einsteinring 24
85609 Dornach/Aschheim
Tel: +49-89-5527-39100 e-mail: eurosales@power.com Germany (Gate Driver Sales) HellwegForum 3
59469 Ense
Tel: +49-2938-64-39990 e-mail: igbt-driver.sales@power.com India #1, 14th Main Road Vasanthanagar Bangalore-560052 India Phone: +91-80-4113-8020 e-mail: indiasales@power.com