PE9763

PE9763 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

• 3.2 GHz operation
• ÷10/11 dual modulus prescaler
• Selectable phase detector or charge pump output
• Serial or Direct mode access
• Frequency selectivity: Comparison frequency / 218
• Low power —- 25 - 30 mA at 3V (phase detector / charge pump)
• Rad-Hard
• Ultra-low phase noise
• 68-lead CQFJ or Die Auxilia- ry 20-bit Latch Fin Fin Prescaler Main Counter Secon- dary 20-bit Latch Primary 21-bit Latch R Counter fr Phase Detector Sdata PD_U PD_D DSM Charge Pump CP K17:0 M8:0 A3:0 R5:0 Pre_en Direct

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions Figure 2. Pin Configuration Table 1. Pin Descriptions

Description

R Counter bit0 (LSB). Direct Input R Counter bit1. Direct Input R Counter bit2. Direct Input R Counter bit3. Direct Input R Counter bit4. Direct Input R Counter bit5 (MSB). Direct Input K Counter bit0 (LSB). Direct Input K Counter bit1. GND Downbond Digital core ground. GND Downbond ESD ground. VDD (Note 1) ESD VDD. VDD (Note 1) Digital core VDD. Direct Input K Counter bit2. Direct Input K Counter bit3. Direct Input K Counter bit4. Direct Input K Counter bit5. Direct Input K Counter bit6.

Document No. 70-0140-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Pin No. Pin Name Valid Mode Type K Counter bit7. Direct Input K Counter bit8. Direct Input K Counter bit9. K10 Direct Input K Counter bit10. K11 Direct Input K Counter bit11. K12 Direct Input K Counter bit12. K13 Direct Input K Counter bit13. K14 Direct Input K Counter bit14. K15 Direct Input K Counter bit15. K16 Direct Input K Counter bit16. K17 Direct Input K Counter bit17 (MSB). VDD (Note 1) Digital core VDD. VDD (Note 1) ESD VDD. GND Downbond Digital core ground. GND Downbond ESD ground. Direct Input M Counter bit0 (LSB). Direct Input M Counter bit1. Direct Input M Counter bit2 Direct Input M Counter bit3. Direct Input M Counter bit4. S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. Direct Input M Counter bit5. SDATA Serial Input Binary serial data input. Input data entered MSB first. Direct Input M Counter bit6. SCLK Serial Input Serial clock input. SDATA is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Direct Input M Counter bit7. Direct Input M Counter bit8 (MSB). Direct Input A Counter bit0 (LSB). Direct Input A Counter bit1. E_WR Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Direct Input A Counter bit2. Direct Input A Counter bit3 (MSB). DIRECT Both Input Direct mode select. “High” enables direct mode. “Low” enables serial mode. Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. VDD (Note 1) Digital core VDD. GND Downbond Digital core ground. GND Downbond ESD ground.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions Pin No. Pin Name Valid Mode Type Prescaler input from the VCO. 3.2 GHz max frequency. Fin Both Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 W resistor directly to the ground plane. GND Downbond Prescaler ground. GND Downbond Prescaler ground. GND Downbond Output driver/charge pump ground. CEXT Both Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kW series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. LD Both Output Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). DOUT Both Output Data out function, enabled in enhancement mode. VDD (Note 1) Output driver/charge pump VDD. GND Downbond Output driver/charge pump ground. PD_D Both Output PD_D pulses down when fp leads fc. PD_U is driven to GND when CPSEL = “High”. CP Both Output Charge pump output. Selected when CPSEL = “1”. Tristate when CPSEL = “Low”. PD_U Both Output PD_U pulses down when fc leads fp. PD_D is driven to GND when CPSEL = “High”. GND Downbond Output driver/charge pump ground. VDD (Note 1) Output driver/charge pump VDD. GND Downbond Phase detector GND. VDD (Note 1) Phase detector VDD. VDD (Note 1) ESD VDD. GND Downbond ESD ground. GND Downbond Reference ground. fr Both Input Reference frequency input. VDD (Note 1) Reference VDD. VDD (Note 1) Digital core VDD. GND Downbond Digital core ground. ENH Both Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. CPSEL Both Input Charge pump select. “High” enables the charge pump and disables pins PD_U and PD_D by forcing them “low”. A “low” Tri-states the CP and enables PD_U and PD_D. MS2_SEL Both Input MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode. RND_SEL Both Input K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having an additional bit for the LSB of K register. The frequency offset as a result of enabling this bit is the phase detector comparison frequency / 219. Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground. VDD (Note 1) ESD VDD. VDD (Note 1) Prescaler VDD.

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings exceeding the rating specified in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 4. ESD Ratings

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 5. DC Characteristics

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Parameter is guaranteed through characterization only and is not tested. Parameter below are not tested for die sales. These parameters are verified during the element evaluation per the die flow.

©2005 Peregrine Semiconductor Corp. All rights reserved. counter (“A”) is used in the modulus select logic. order to achieve the desired fractional step. be configured to drive a tri-state charge pump. Figure 3. Functional Block Diagram

©2005 Peregrine Semiconductor Corp. All rights reserved. bit in the DSM that acts like an extra bit (19th bit). counter divide ratio of “2”. “high” allows Fin to bypass the ÷10/11 prescaler. Figure 4. When “1”, data is transferred to the register is used to program the DSM.

©2005 Peregrine Semiconductor Corp. All rights reserved. cording to the timing diagram shown in Figure 4. shown in Table 7 and Table 8. Table 7. Secondary Register Programming Table 8. Auxiliary Register Programming Table 9. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

Document No. 70-0140-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Enhancement Register Figure 4. Serial Interface Mode Timing Diagram The functions of the enhancement register bits are shown below with all bits active “high”. Table 10. Enhancement Register Bit Functionality Reserve Reserved. Bit 1 Reserve Reserved. Bit 2 fp output Drives the M counter output onto the Dout output. Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 fc output Drives the reference counter output onto the Dout output. Bit 7 LD Disable Disables the LD pin for quieter operation. ** Program to 0

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 5. Typical Phase Noise two input signals, fp and fc. VCO frequency, for a positive Kv VCO. charge pump will drive a fixed 2 mA of current. verting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. A typical phase noise plot is shown below. Phase noise results for “Trace 2” is the average values.

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 6. Typical Spurious Plot Fcomparison = 20 MHz, MASH 1-1, VDD = 3 V, Temp = 25 C.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0140-01 │ UltraCMOS™ RFIC Solutions Figure 7. Package Drawing Table 11. Ordering Information

Document No. 70-0140-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation

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San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Peregrine Semiconductor, Korea #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor, China Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific:

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