PE43501 PEREGRINE | Alldatasheet
Document overview
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Technical content
Features
- HaRP™-enhanced UltraCMOS™ device
- Attenuation: 0.25 dB steps to 7.75 dB
- High Linearity: Typical +58 dBm IP3
- Excellent low-frequency performance
- 3.3 V or 5.0 V Power Supply Voltage
- Fast switch settling time
- Programming Modes:
- Direct Parallel
- Latched Parallel
- Serial-Addressable: Program up to eight addresses 000 - 111
- High-attenuation state @ power-up (PUP)
- CMOS Compatible
- No DC blocking capacitors required
- Packaged in a 32-lead 5x5x0.85 mm QFN
Figure 1. Package Type
200 MHz 900 MHz 1800 MHz 2200 MHZ
3000 MHz 4000 MHz 6000 MHz
200 M Hz 900 M Hz 1800 M Hz
2200 M Hz 3000 M Hz 5400 M Hz
900 MHz
1800 MHz
2200 MHz
3000 MHz
5400 MHz
5800 MHz
Table 1. Electrical Specifications @ +25°C, VDD = 3.3 V or 5.0 V
4 GHz ≤ 6 GHz
Figure 3. 0.25 dB Step Error vs. Frequency* Figure 5. 0.25 dB Major State Bit Error Figure 4. 0.25dB Attenuation vs. Attenuation *Monotonicity is held so long as step-error does not cross zero. Figure 6. 0.25 dB Attenuation Error vs. Frequency
3000 MHz @ T= +25C 3000 M Hz @ T= -40C 3000 MHz @ T= +85C
1800 MHz @ T= +25C 1800 MHz @ T= -40C 1800 MHz @ T= +85C
900 MHz @ T=+25 C 900 MHz @ T= -40C 900 MHz @ T= +85C
900 M Hz 1800 MHz 3000 MHz
Figure 15. Attenuation Error vs. Attenuation Figure 13. Relative Phase vs. Temperature: Figure 14. Attenuation Error vs. Attenuation Figure 16. Attenuation Error vs. Attenuation Figure 17. Input IP3 vs. Frequency
Figure 18. Pin Configuration (Top View) Table 2. Pin Descriptions must be grounded for proper device operation.
1 N/C No Connect
2 V DD Power supply pin
3 P/S Serial/Parallel mode select
4 A0 A0 connection
7 RF1 RF1 port
18 RF2 RF2 port
21 A2 A2 connection
22 A1 A1 connection
23 LE Latch Enable input
24 CLK Serial interface clock input
25 SI Serial Interface input
28 C4 Attenuation control bit, 4 dB
29 C2 Attenuation control bit, 2 dB
30 C1 Attenuation control bit, 1 dB
The PE43501 has a maximum 25 kHz switching rate. DSA can be toggled across attenuation states. devices are immune to latch-up. the 32-lead 5x5 QFN package is MSL1.
Table 3. Operating Ranges Table 4. Absolute Maximum Ratings maximum for extended periods may reduce reliability.
1 Hz ≤ 20 MHz
20 MHz ≤ 4 GHz
Figure 19. Maximum Power Handling Capability: Z0 = 50 Ω
Table 5. Control Voltage Table 6. Latch and Clock Specifications Table 9. Serial Attenuation Word Truth Table Table 8. Address Word Truth Table Table 10. Serial-Addressable Register Map Table 7. Parallel Truth Table X L L L L L L L Reference I.L.
©2008-2009 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0251-03 │ UltraCMOS™ RFIC Solutions Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE43501. The P/S bit provides this selection, with P/S=LOW selecting the parallel interface and P/S=HIGH selecting the serial interface. Parallel Mode Interface The parallel interface consists of five CMOS- compatible control lines that select the desired attenuation state, as shown in Table 7. The parallel interface timing requirements are defined by Fig. 21 (Parallel Interface Timing Diagram), Table 12 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched-parallel programming the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Fig. 21) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Serial-Addressable Interface The serial interface is a 16-bit serial-in, parallel- out shift register buffered by a transparent latch. The 16-bits make up two words comprised of 8- bits each. The first word is the Attenuation Word, which controls the state of the DSA. The second word is the Address Word, which is compared to the static (or programmed) logical states of the A0, A1 and A2 digital inputs. If there is an address match, the DSA changes state; otherwise its current state will remain unchanged. Fig. 20 illustrates a example timing diagram for programming a state. It is recommended that all parallel control inputs be grounded when the DSA is used in serial mode. The serial-addressable interface is controlled using three CMOS-compatible signals: Serial-In (SI), Clock (CLK), and Latch Enable (LE). The SI and CLK inputs allow data to be serially entered into the shift register. Serial data is clocked in LSB first, beginning with the attenuation word. The shift register must be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data into the DSA. Address word and attenuation word truth tables are listed in Table 8 & Table 9, respectively. A programming example of the Serial-Addressable register is illustrated in Table 10. The serial-addressable timing diagram is illustrated in Fig. 20. Power-up Control Settings The PE43501 will always initialize to the maximum attenuation setting (7.75 dB) on power-up for both the serial-addressable and latched-parallel modes of operation and will remain in this setting until the user latches in the next programming word. In direct-parallel mode, the DSA can be preset to any state within the 7.75 dB range by pre-setting the parallel control pins prior to power-up. In this mode, there is a 400-µs delay between the time the DSA is powered-up to the time the desired state is set. During this power-up delay, the device attenuates to the maximum attenuation setting (7.75 dB) before defaulting to the user defined state. If the control pins are left floating in this mode during power-up, the device will default to the minimum attenuation setting (insertion loss state).
PE43501 Digital Step Attenuator. software is set to program in Direct-Parallel mode. attenuation state is enabled or disabled. Parallel is selected in the software. Figure 22. Evaluation Board Layout time an attenuation state is enabled or disabled.
0 OHM
1 GND
2 VDD
5 GND
6 GND
7 RF1
8 GND
10 GND
11 GND
12 GND
13 GND
14 GND
15 GND
16 GND
1 CLOCK
4 GND
Figure 24. Package Drawing Figure 23. Evaluation Board Schematic Note: Capacitors C1-C8, C13, & C14 may be omitted. Pin 26 & 27 are ground.
Peregrine Semiconductor Corporation
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