PE97022 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • Low Power - 45 mA at 3.3V
  • 3500 MHz operation
  • ÷10/11 dual modulus prescaler
  • Internal phase detector
  • Serial, parallel or hardwired programmable
  • Ultra-Low Phase Noise: -216 dBc/Hz
  • SEU < 10-9 errors / bit-day
  • 100 Krad (Si) total dose
  • Pin compatible with the PE9702, packaged in a 44-lead CQFJ (reference application note AN22 at www.psemi.com)

Figure 1. Block Diagram

Table 1. Pin Descriptions (continued) Sdata Serial Input Binary serial data input. Input data entered MSB first. D 5 Parallel Input Parallel data bus bit5. M 5 Direct Input M Counter bit5. “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. D 6 Parallel Input Parallel data bus bit6. M 6 Direct Input M Counter bit6. programming of internal counters while in Serial Interface Mode. D 7 Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. programming of internal counters while in Parallel Interface Mode. A0 Direct Input A Counter bit0 (LSB). clocked into the enhancement register on the rising edge of Sclk. A1 Direct Input A Counter bit1. A2 Direct Input A Counter bit2. A3 Direct Input A Counter bit3 (MSB). 22 Bmode ALL Input Selects direct interface mode (Bmode=1). 23 VDD ALL (Note 1) Same as pin 1. register on the rising edge of Hop_WR. 27 Fin ALL Input Prescaler input from the VCO. 3.5 GHz max frequency.

28 Fin ALL Input

enhancement register programming or by floating or grounding VDD pin 31.

Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. V DD pins 31 and 38 are used to enable test modes and should be left floating. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground. 31 VDD -fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output. through enhancement register programming. 33 VDD ALL (Note 1) Same as pin 1.

34 Cext ALL Output

inverting amplifier used for driving LD. 35 VDD ALL (Note 1) Same as pin 1. 36 PD_D ¯ ALL Output PD_D ¯ is pulse down when fp leads fc. 37 PD_ Ū ALL PD_ Ū is pulse down when fc leads fp. 38 VDD -fc ALL (Note 1) VDD for fc. Can be left floating or connected to GND to disable the fc output. enhancement register programming or by floating or grounding VDD pin 38. 42 fr ALL Input Reference frequency input.

43 LD ALL Output,

is high impedance, otherwise LD is a logic low (“0”).

Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: Counter and phase detector outputs: fc, fp.

Table 6. AC Characteristics: VDD = 3.3 V, -40° C < TA < 85° C, unless otherwise specified Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Note 3: Parameter is guaranteed through characterization only and is not tested. Note 4: Parameters below are not tested for die sales. These parameters are verified during the element evaluation.

275 MHz ≤ Freq ≤ 3200MHz -5 5 dBm

generates up and down frequency control signals. parallel bus, or hardwired directly to the pins. Figure 6. Functional Block Diagram

and powers down the prescaler. a minimum M Counter divide ratio of “2”. M value is limited to 1 ≤ M ≤ 127. M value is limited to 1 ≤ M ≤ 127. detector comparison frequency, fc. mode, the R value is limited to 0 ≤ R ≤ 15. Bmode input “low” and the Smode input “low”.

  1. Data is transferred to the counters as shown

the secondary register contents are utilized. Figure 6. This data provides control bits as

Bmode input “low” and the Smode input “high”. the counters as shown in Table 7. secondary register contents are utilized. register on the rising edge of Sclk, MSB (B0) first. Figure 6. After the falling edge of E_WR, the data R 4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality loop filter which controls the VCO tune voltage. Bit 3 Power down Power down of all functions except programming interface. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output (fmain) onto the Dout output. Bit 7 f p, fc OE f p, fc outputs disabled.

Figure 9. Package Drawing Table 10. Ordering Information

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