PE9601EK | DigiCamel IC Datasheet

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PE9601 PEREGRINE | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 14

Technical content

Features

2200 MHz operation
10/11 prescaler
Internal phase detector with charge pump
Serial, parallel or hardwired programmable
Low power – 25 mA at 3 V
Targeted at Q3236 PLL replacement
100 Krad total dose
44-lead CQFJ PE9601

Figure 2. Package Type

Description

(Note 1) Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. Direct Input R Counter bit0 (LSB). Direct Input R Counter bit1. Direct Input R Counter bit2. Direct Input R Counter bit3. GND ALL (Note 1) Ground. Parallel Input Parallel data bus bit0 (LSB). Direct Input M Counter bit0 (LSB). Parallel Input Parallel data bus bit1. Direct Input M Counter bit1. Parallel Input Parallel data bus bit2. Direct Input M Counter bit2. Parallel Input Parallel data bus bit3. Direct Input M Counter bit3. VDD ALL (Note 1) Same as pin 1. VDD ALL (Note 1) Same as pin 1.

Document No. 70-0025-05 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel Input Parallel data bus bit4 Direct Input M Counter bit4 Sdata Serial Input Binary serial data input. Input data entered MSB first. Parallel Input Parallel data bus bit5. Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Parallel Input Parallel data bus bit6. Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL Ground. FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. Direct Input A Counter bit0 (LSB). E_WR Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). Direct Input A Counter bit3 (MSB). Bmode ALL Input Selects direct interface mode (Bmode=1). VDD ALL (Note 1) Same as pin 1. M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Fin ALL Input Prescaler input from the VCO. Input voltage = 223 mV RMS for guaranteed operation. Fin ALL Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected directly to the ground plane. GND ALL Ground. Pin No. Pin Name Interface Mode Type Table 1. Pin Descriptions (continued)

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions fp ALL Output Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31. VDD-fp ALL (Note 2) VDD for fp. Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. VDD ALL (Note 1) Same as pin 1. Cext ALL Output Logical “OR” of PD_U and PD_D terminated through an on chip, 2 kW series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. VDD ALL (Note 1) Same as pin 1. CP ALL Output Charge pump current is sourced for “up” when fc leads fp and sinked for “down” when fc lags fp. NC ALL No connection. VDD-fc ALL (Note 2) VDD for fc fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. GND ALL Ground. GND ALL Ground. fr ALL Input Reference frequency input. See Figure 4. LD ALL Output, OD Lock detect and open drain logical inversion of Cext. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Pin No. Pin Name Interface Mode Type Note 1: VDD pins 1, 11, 12, 23, 33, and 35 are connected by diodes and must be supplied with the same positive voltage level. VDD pins 31 and 38 are used to enable test modes and should be left floating. All digital input pins have 70k ohm pull-down resistors to ground. Figure 4. Looking into the device PIN 42 - fr

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings devices are immune to latch-up. exceeding the rating specified in Table 4. may cause permanent device damage. limits in the DC Electrical Specifications table. extended periods may affect device reliability. Table 3. Operating Ratings Table 4. ESD Ratings

1.0 V < VCP < VDD –

1.0 V TA = 25° C

©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics Note 2: CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5Vp-p. Parameter is guaranteed through characterization only and is not tested.

Document No. 70-0025-05 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9 bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] (1) where A ≤ M + 1, M ¹ 0 When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2) where A ≤ M + 1, M ¹ 0 A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6 bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) (3) where R > 0 Note that programming R equal to “0” will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low (“0”). Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input “low” and the Smode input “low”. Parallel input data, D[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 6. Data are transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for “ping-pong” counter control is programmed via the FSELP input. When FSELP is “high”, the primary register contents set the counter inputs. When FSELP is “low”, the secondary register contents are utilized. The FSELP input is synchronized with the loading of the counters in order to minimize glitches in the “ping-pong” case. Due to this attribute, applications using a single register should use the secondary register (i.e. tie FSELP “low”) to avoid problems with the prescaler powering up in the disabled state. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 6. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input “low”. Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input “high”. Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low (“0”) Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input “low” and the Smode input “high”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figure 6 and Figure 7. Data are transferred to the counters as shown in Table 7 on page 10.

After the falling edge of E_WR, the data

Table 7. Primary Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0025-05 │ UltraCMOS™ RFIC Solutions Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality Reserved Bit 1 Reserved Bit 2 Reserved Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output (fmain) onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled. Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, namely PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “high”. If the divided reference leads the divided VCO in phase or frequency (fr leads fp), PD_U pulses “high”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The signals from the phase detector couple di- rectly to a charge pump. PD_U controls a current source at pin CP with constant amplitude and pulse duration approximately the same as PD_U. PD_D similarly drives a current sink at pin CP. The current pulses from pin CP are low pass fil- tered externally and then connected to the VCO tune voltage. PD_U pulses result in a current source, which increases the VCO frequency and PD_D results in a current sink, which decreases VCO frequency. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “OR” of PD_U and PD_D waveforms, which is driven through a series 2 k ohm resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “NOR” function of PD_U and PD_D.

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Tel: +33(0) 4 4239 3361 Fax: +33(0) 4 4239 7227 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652

Product Information

PE9601EK specifications and overview.

Summary

2200 MHz UltraCMOS??Integer-N PLL for Rad Hard Applications

Description

2200 MHz UltraCMOS??Integer-N PLL for Rad Hard Applications

Source title PE9601EK Datasheet(PDF) - Peregrine Semiconductor Corp.

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