PE926C31 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • High-speed operation: < 10 nS typical
  • Low power: < 150 uA typical (unloaded)
  • 3.3 V operation
  • Standard packaging: 16-lead flat pack
  • SEL Immune UTSi CMOS-on-sapphire
  • SEU <10-10 errors / bit-day
  • 300 Krad Total Dose Quad RS-422 Differential Line Driver Radiation Hardened

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions Table 1. Pin Descriptions Table 2. Recommended Operating Conditions exceeding the rating specified in Table 2. devices are immune to latch-up. Table 3. Truth Table with a bypass capacitor to ground (pin 8). Figure 2. Pin Configuration (Top View)

Description

A Channel A Input AQ+ Channel A Noninverting Ouput AQ- Channel A Inverting Output Enable, active high BQ- Channel B Inverting Output BQ+ Channel B Noninverting Output B Channel B Input Ground Pin C Channel C Input CQ+ Channel C Noninverting Output CQ- Channel C Inverting Ouput Enable, active low DQ- Channel D Inverting Output DQ+ Channel D Noninverting Output D Channel D Input Supply Pin Symbol Parameter/Conditions Min Max Units Supply voltage 3.0 3.6 V TOP Operating temperature range -55 125 VIN Maximum input voltage Vdd V VOUT Maximum output voltage Vdd V IOUT Maximum output current -50 mA Data L H X Z Z H X L L H X L H X H H L X L

Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Table 4. Electrical Specifications

  1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs
  2. “Digital Input” or “Enable” pins refer to E+, E-
  3. “Digital Input” pins refer to A, B, C, D

Pin(s) Min Typ Max Units VD1 Output Differential Voltage No load AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- (V+) -0.3 (V+) (V+) +0.6 V VD2 Output Differential Voltage RL=100 Ω, Fig DC1 1.9 2.3 V DVD2 Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1 -0.4 0.4 V VCM Common Mode Voltage RL=100 Ω, Fig DC1 1.5 2.0 V DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 -0.4 0.4 V IOZH Tristate Output Leakage (H) VOUT = V+, disabled -0.1 uA IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled 0.1 uA IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H -30 -70 -100 mA IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs = 0.0V 100 uA IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all inputs = 0.0V -100 uA VOH Output High Voltage Iout=-20mA 2.0 2.4 V VOL Output Low Voltage Iout=20mA 0.1 0.5 V VIH Input threshold H Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E- 2.5 V VIL Input Threshold L Vdd=3.0V (VILMAX=0.3*VDD) A, B, C, D, E+, E- 0.9 V IIH Input Lkg Current A, B, C, D, E+, E- uA IIL Input Lkg Current A, B, C, D, E+, E- uA VIKL Input Clamp Diode Voltage IIN=-20 mA A, B, C, D, E+, E- -1.5 VIKH Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- (V+) + 1.5 V µ ICC Supply Current No load, Inputs = 0 V or V+ 120 uA 150 uA -55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified

©2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0157-01 │ UltraCMOS™ RFIC Solutions Table 5. Post-Irradiation DC Electrical Specifications

  1. “Line” pins refer to AQ-, AQ+, BQ-, BQ+, CQ-, CQ+, DQ-, DQ+, differential outputs
  2. “Digital Input” or “Enable” pins refer to E+, E-
  3. “Digital Input” pins refer to A, B, C, D
  4. Output Short Circuit not intended to imply continuous operation

Pin(s) Min Typ Max Units VD1 Output Differential Voltage No load AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- (V+) -0.3 (V+) (V+) +0.6 V VD2 Output Differential Voltage RL=100 Ω, Fig DC1 1.9 2.3 V DVD2 Output Differential Voltage Change IOUT 0 – 20mA, Fig DC1 -0.4 0.4 V VCM Common Mode Voltage RL=100 Ω, Fig DC1 1.5 2.0 V DVCM Common Mode Voltage Change RL=100 Ω, Fig DC1 -0.4 0.4 V IOZH Tristate Output Leakage (H) VOUT = V+, disabled -0.1 uA IOZL Tristate Output Leakage (L) VOUT = 0.0 V, disabled 0.1 uA IOSC Output Short Circuit Current VOUT = 0.0 V, Enabled Q=H -30 -70 -100 mA IOFFH Output Leakage Current (H) VOUT=6.0V,V+ and all inputs = 0.0V 100 uA IOFFL Output Leakage Current (L) VOUT=-0.25V,V+ and all inputs = 0.0V -100 uA VOH Output High Voltage Iout=-20mA 2.0 2.4 V VOL Output Low Voltage Iout=20mA 0.1 0.5 V VIH Input threshold H Vdd=3.6V (VIHMIN=0.7*VDD) A, B, C, D, E+, E- 2.5 V VIL Input Threshold L Vdd=3.0V (VILMAX=0.3*VDD) A, B, C, D, E+, E- 0.9 V IIH Input Lkg Current A, B, C, D, E+, E- uA IIL Input Lkg Current A, B, C, D, E+, E- uA VIKL Input Clamp Diode Voltage IIN=-20 mA A, B, C, D, E+, E- -1.5 VIKH Input Clamp Diode Voltage IIN=20 mA A, B, C, D, E+, E- (V+) + 1.5 V ICC Supply Current No load, Inputs = 0 V or V+ 120 uA 150 uA

Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. Pre-irradiation Electrical Specifications Pin(s) Min Typ Max Units TPHL Prop Delay H-L RL=100 CL=50 pF AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- nS TPLH Prop Delay H-L nS TSK1 Prop Delay Q+/Q- nS TSK2* Prop Delay Skew Ch/Ch nS TRISE* Rise Time 20%/80% nS TFALL* Fall Time 20%/80% nS TPHZ Prop Delay H-Z nS TPZH Prop Delay Z-H nS TPLZ Prop Delay L-Z nS TPZL Prop Delay Z-L nS -55° C < Tcase < 125° C, 3.0 V < V+ < 3.6 V, PreRad, unless otherwise specified Table 7. Post-irradiation Electrical Specifications Pin(s) Min Typ Max Units TPHL Prop Delay H-L RL=100 CL=50 pF AQ+, AQ-, BQ+, BQ-, CQ+, CQ-, DQ+, DQ- nS TPLH Prop Delay H-L nS TSK1 Prop Delay Q+/Q- nS TSK2* Prop Delay Skew Ch/Ch nS TRISE* Rise Time 20%/80% nS TFALL* Fall Time 20%/80% nS TPHZ Prop Delay H-Z nS TPZH Prop Delay Z-H nS TPLZ Prop Delay L-Z nS TPZL Prop Delay Z-L nS *Note: Guaranteed by design, not tested

Document No. 70-0157-01 │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices United States Peregrine Semiconductor Corp.

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San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 Japan Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France China Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652 The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp.