PE83336EK

PE83336 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

• 3.0 GHz operation
• ÷10/11 dual modulus prescaler
• Internal phase detector
• Serial, parallel or hardwired programmable
• Ultra-low phase noise
• Available in 44-lead CQFJ Peregrine’s PE83336 is a high performance integer-N PLL capable of frequency synthesis up to 3.0 GHz. The superior phase noise performance of the PE83336 makes it ideal for rugged military environments including: radio handsets, radar, avionics, missiles, etc. The PE83336 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. Fabricated in Peregrine’s patented UTSi® (Ultra Thin Silicon) CMOS technology, the PE83336, while optimized for stringent military environments, offers excellent RF performance together with the economy and integration of conventional CMOS. Fin Fin Prescaler Main Counter Secon- dary 20-bit Latch Primary 20-bit Latch Pre_en M(6:0) A(3:0) R(3:0) R Counter fr Phase Detector fc fp D(7:0) Sdata PD_U PD_D

Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS Page 2 of 14 44 43 42 D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_WR, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND GND fp VDD_fp Dout VDD Cext VDD PD_D PD_U VDD_fc fc Fin Fin Hop_WR A_WR M1_WR VDD Bmode Smode, A3 M2_WR, A2 E_WR, A1 FSELP, A0 GND VDD Enh LD fr GND GND Figure 2. Pin Configuration Table 1. Pin Descriptions

Description

(Note 1) Direct Input R Counter bit0 (LSB). Direct Input R Counter bit1. Direct Input R Counter bit2. Direct Input R Counter bit3. GND ALL (Note 1) Ground. Parallel Input Parallel data bus bit0 (LSB). Direct Input M Counter bit0 (LSB). Parallel Input Parallel data bus bit1. Direct Input M Counter bit1. Parallel Input Parallel data bus bit2. Direct Input M Counter bit2. Parallel Input Parallel data bus bit3. Direct Input M Counter bit3. VDD ALL (Note 1) Same as pin 1. VDD ALL (Note 1) Same as pin 1. S_WR Serial Input Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 3 of 14 Pin No. (44-lead CQFJ) Pin Name Interface Mode Type register data are transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel Input Parallel data bus bit4 Direct Input M Counter bit4 Sdata Serial Input Binary serial data input. Input data entered MSB first. Parallel Input Parallel data bus bit5. Direct Input M Counter bit5. Sclk Serial Input Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. Parallel Input Parallel data bus bit6. Direct Input M Counter bit6. FSELS Serial Input Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel Input Parallel data bus bit7 (MSB). Pre_en Direct Input Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. GND ALL Ground. FSELP Parallel Input Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. Direct Input A Counter bit0 (LSB). Serial Input Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. E_WR Parallel Input Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. Direct Input A Counter bit1. M2_WR Parallel Input M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the rising edge of M2_WR. Direct Input A Counter bit2. Smode Serial, Parallel Input Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). Direct Input A Counter bit3 (MSB). Bmode ALL Input Selects direct interface mode (Bmode=1). VDD ALL (Note 1) Same as pin 1. M1_WR Parallel Input M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A_WR Parallel Input A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the rising edge of A_WR. Hop_WR Serial, Parallel Input Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Fin ALL Input Prescaler input from the VCO. 3.0 GHz max frequency. Fin ALL Input Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 Ω resistor directly to the ground plane. GND ALL Ground.

Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS Page 4 of 14 Pin No. (44-lead CQFJ) Pin Name Interface Mode Type Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 31. VDD-fp ALL (Note 1) VDD for fp. Can be left floating or connected to GND to disable the fp output. Dout Serial, Parallel Output Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. VDD ALL (Note 1) Same as pin 1. Cext ALL Output Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. VDD ALL (Note 1) Same as pin 1. PD_D ALL Output PD_D is pulse down when fp leads fc. PD_U ALL PD_U is pulse down when fc leads fp. VDD-fc ALL (Note 1) VDD for fc can be left floating or connected to GND to disable the fc output. fc ALL Output Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. GND ALL Ground. GND ALL Ground. fr ALL Input Reference frequency input. LD ALL Output Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low (“0”). Enh Serial, Parallel Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional. N/A NC ALL No connection. Note 1: All VDD pins are connected by diodes and must be supplied with the same positive voltage level. VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc outputs. Note 2: All digital input pins have 70 kΩ pull-down resistors to ground.

Table 2. Absolute Maximum Ratings Table 3. Operating Ratings Table 4. ESD Ratings exceeding the rating specified in Table 4. devices are immune to latch-up.

Table 5. DC Characteristics

Table 6. AC Characteristics

100 Hz Offset: VDD

1000 Hz Offset: VDD

Parameter is guaranteed through characterization only and is not tested. noise amplifier to square up the edges is recommended at lower input frequencies. of qualification testing. These parameters are also exempt from PDA requirements. Note 5: Parameter is tested using 100pF load capacitance and is guaranteed through characterization only. Typical test delay is 12nS.

Table 7. Phase Noise Test

100 Hz Offset

1000 Hz Offset

11, depending on the value of the modulus select. Figure 3. Functional Block Diagram

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 9 of 14 Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user defined values in the “M” and “A” counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit M counter. Setting Pre_en “low” enables the 10/11 prescaler. Setting Pre_en “high” allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation: fp = Fin / [10 x (M + 1) + A] (1) where A ≤ M + 1, 1 ≤ M ≤ 511 When the loop is locked, Fin is related to the reference frequency, fr, by the following equation: Fin = [10 x (M + 1) + A] x (fr / (R+1)) (2) where A ≤ M + 1, 1 ≤ M ≤ 511 A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of “1” will result in a minimum M Counter divide ratio of “2”. When the prescaler is bypassed, the equation becomes: Fin = (M + 1) x (fr / (R+1)) (3) where 1 ≤ M ≤ 511 In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation: fc = fr / (R + 1) (4) where 0 ≤ R ≤ 63 Note that programming R equal to “0” will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low (“0”). Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input “low” and the Smode input “low”. Parallel input data, D[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 4. Data are transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for “ping-pong” counter control is programmed via the FSELP input. When FSELP is “high”, the primary register contents set the counter inputs. When FSELP is “low”, the secondary register contents are utilized. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 4. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input “low”. Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input “low” and the Smode input “high”. While the E_WR input is “low” and the S_WR input is “low”, serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figures 4-5. Data are transferred to the counters as shown in Table 7 on page 10. The double buffering provided by the primary and secondary registers allows for “ping-pong” counter control using the FSELS input. When FSELS is “high”, the primary register contents set the counter inputs. When FSELS is “low”, the secondary register contents are utilized. While the E_WR input is “high” and the S_WR input is “low”, serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent

asserting the Enh input “low”. and R5 are internally forced low (“0”). Table 8. Primary Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Table 9. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.

Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS Page 12 of 14 Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 10. Enhancement Register Bit Functionality Reserved Bit 1 Reserved Bit 2 Reserved Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled. Program to 0 Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses “low”. If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses “low”. The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is equal to 2.7 V / 2 π, which numerically yields 0.43 V / radian. PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency; PD_D pulses result in a decrease in VCO frequency (for a positive Kv VCO). A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D.

PEREGRINE SEMICONDUCTOR CORP.  | http://www.peregrine-semi.com Copyright  Peregrine Semiconductor Corp. 2003 Page 13 of 14 Figure 6. Package Drawing Table 11. Ordering Information 500 units / T&R 83336-00 PE83336EK CQFJ Evaluation Board with Software 44-lead CQFJ 1 / Box

Copyright  Peregrine Semiconductor Corp. 2003 File No. 70/0137~01A | UTSi CMOS RFIC SOLUTIONS Page 14 of 14 Sales Offices United States Peregrine Semiconductor Corp.

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For a list of representatives in your area, please refer to our Web site at: http://www.peregrine-semi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a PCN (Product Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. Peregrine products are protected under one or more of the following 5,416,043. Other patents are pending. Peregrine, the Peregrine logotype, Peregrine Semiconductor Corp., and UTSi are registered trademarks of Peregrine Semiconductor Corporation. Copyright © 2003 Peregrine Semiconductor Corp. All rights reserved.