PE4305 PEREGRINE | Alldatasheet

Document overview

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Technical content

Features

  • Attenuation: 0.5 dB steps to 15.5 dB
  • Flexible parallel and serial programming interfaces
  • Latched or direct mode
  • Unique power-up state selection
  • Positive CMOS control logic
  • High attenuation accuracy and linearity over temperature and frequency
  • Very low power consumption
  • Single-supply operation
  • 50 Ω impedance
  • Pin compatible with PE430x series
  • Packaged in a 20 Lead 4x4 mm QFN Control Logic Interface Parallel Control Power-Up Control Serial Control RF Input RF Output Switched Attenuator Array

Figure 2. Package Type Table 1. Electrical Specifications @ +25°C, VDD = 3.0 V

  1. See Max input rating in Table 2 & Figures on Pages 2 to 4 for data across frequency.
  2. Note Absolute Maximum in Table 3.

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 8. Attenuation Error Vs. Attenuation Figure 10. Attenuation Error Vs. Attenuation Figure 9. Attenuation Error Vs. Attenuation Figure 7. Attenuation Error Vs. Frequency

10 MHz @ 25 C

510 MHz @ 25 C

10 MHz @ -40 C

510 MHz @ -40 C

10 MHz @ 85 C

510 MHz @ 85 C

1010 MHz @ 25 C

1010 MHz @ -40 C

1010 MHz @ 85 C

1210 MHZ @ 25 C

1210 MHz @ -40 C

1210 MHz @ 85 C

1510 MHz @ 25 C

1510 MHz @ -40 C

1510 MHz @ 85 C

2010 MHz @ 25 C

2010 MHz @ -40 C

2010 MHz @ 85 C

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 12. 1 dB Compression vs. Frequency Figure 13. Input IP3 vs. Frequency Figure 11. Attenuation Error vs. Attenuation

2510 MHz @ 25 C

2510 MHz @ -40 C

2510 MHz @ 85 C

Document No. 70/0159~02C │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Table 2. Pin Descriptions Table 3. Absolute Maximum Ratings exceeding the rate specified in Table 3. Table 4. DC Electrical Specifications 2: Latch Enable (LE) has an internal 100 kΩ resistor to VDD. internal negative voltage generator.

  1. Place a 10 kΩ resistor in series, as close to pin as possible to

avoid frequency resonance. See “Resistor on Pin 3” paragraph. Figure 14. Pin Configuration (Top View) devices are immune to latch-up. dependent upon this condition.

Description

No connect. Can be connected to any bias. RF1 RF port (Note 1). Data Serial interface data input (Note 4). Clock Serial interface clock input. LE Latch Enable input (Note 2). VDD Power supply pin. N/C No connect. Can be connected to any bias. PUP2 Power-up selection bit. VDD Power supply pin. GND Ground connection. GND Ground connection. Vss/GND Negative supply voltage or GND connection(Note 3) P/S Parallel/Serial mode select. RF2 RF port (Note 1). Attenuation control bit, 8 dB. Attenuation control bit, 4 dB. Attenuation control bit, 2 dB. GND Ground connection. Attenuation control bit, 1 dB. C0.5 Attenuation control bit, 0.5 dB. Paddle GND Ground for proper operation Symbol Parameter/Conditions Min Max Units VDD Power supply voltage -0.3 4.0 V VI Voltage on any input -0.3 VDD+ 0.3 V TST Storage temperature range -65 150 TOP Operating temperature range -40 PIN Input power (50 Ω) dBm VESD ESD voltage (Human Body Model) 500 V Parameter Min Typ Max Units VDD Power Supply Voltage 2.7 3.0 3.3 V IDD Power Supply Current 100 µA Digital Input High 0.7xVDD V Digital Input Low 0.3xVDD V Digital Input Leakage µA

©2005 Peregrine Semiconductor Corp. All rights reserved. attenuation state, as shown in Table 5. Characteristics), and switching speed (Table 1). of the device (using hardwire, switches, or jumpers). Table 5. Truth Table is independent of the state of the LE input. brought LOW, data in the shift register is latched. Table 8 (Serial Interface AC Characteristics). present on the five parallel data inputs (C0.5 to C8). be specified as the power-up state. Table 6. Power-Up Truth Table, Parallel

©2005 Peregrine Semiconductor Corp. All rights reserved. Figure 19. Package Drawing

0.20 REF

  1. Dimension applies to metallized terminal and is measured

between 0.25 and 0.30 from terminal tip.

  1. Coplanarity applies to the exposed heat sink slug as well as
  2. Dimensions are in millimeters.

Document No. 70/0159~02C │www.psemi.com ©2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices United States Peregrine Semiconductor Corp.

9450 Carroll Park Drive

San Diego, CA 92121 Tel 1-858-731-9400 Fax 1-858-731-9499 Japan Peregrine Semiconductor K.K. 5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: 011-81-3-3502-5211 Fax: 011-81-3-3502-5213 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F- 92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS is a trademark of Peregrine Semiconductor Corp. China Peregrine Semiconductor 28G, Times Square, No. 500 Zhangyang Road, Shanghai, 200122, P.R. China Tel: 011-86-21-5836-8276 Fax: 011-86-21-5836-7652