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Technical content
Features
- Ultra-high linearity Quad MOSFET array with integrated LO amplifier
- Ideal for mobile radio and Up/down conversion applications
- Low conversion loss
- High LO Isolation
- Packaged in small 4x4x0.85mm 20-lead QFN
Figure 2. Package Type
Table 1. AC and DC Electrical Specifications (VDD = 2.9 to 3.1 V, Temperature = -40 to +85 ° C unless specified otherwise) Notes: 1. The RF to IF Isolation is measured with an input frequency equal with IF.
- IIP3 is measured with two tones at 0 dBm, 100kHz spacing
700 MHz
800 MHz
900 MHz
©2010 Peregrine Semiconductor Corp. All rights reserved. Table 2. Pin Descriptions Table 4. Absolute Maximum Ratings exceeding the specified rating. devices are immune to latch-up. Figure 3. Pin Configuration (Top View) to the limits in the Operating Ranges table. infrastructure equipment, and STB/CATV systems. matching structures enabling three-port operation. Peregrine’s UltraCMOS™ process. passive mixer. The LO input can be differential or single-ended.
1 GND Ground
2 INB Negative LO Input
3 INA Positive LO Input
4 N/C No Connect
5 N/C No Connect
6 EN Enable Pin (active low)
7 VDD VDD
8 IF_P Positive IF port
9 GND Ground
10 IF_M Negative IF port
11 GND Ground
12 RF_P Positive RF Input
13 RF_M Negative LO Input
14 GND Ground
15 MixBias External Mixer Bias
16 N/C No Connect
17 N/C No Connect
18 V DD VDD
19 V DD VDD
20 GND Ground
Table 3. Operating Ranges in the 4x4x0.85 mm 20-lead QFN package is MSL3.
©2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0242-06 │ UltraCMOS™ RFIC Solutions Evaluation Kit Figure 4. Evaluation Board Layout Peregrine Specification 101-0201-00A The Mixer Evaluation Kit board was designed to ease customer evaluation of the PE4150 Quad MOSFET Mixer with integrated LO amplifier. The RF and IF ports are connected through 50ohm transmission lines and 1:4 transmission line transformers to J5 and J7, respectively. The LO ports are connected through 50 Ω transmission lines to J4 and J6, respectively, and can support either a single-ended or differential signal drive. With a single-ended input, no termination is needed on the un-used port. The board is constructed of a two metal layer FR4 with a total thickness of 0.062". The bottom layer provides ground for the RF transmission lines. The transmission lines were designed using a coplanar waveguide with ground plane model using a trace width of 0.037", trace gaps of 0.008", dielectric thickness of 0.059" and metal thickness of 0.0015". J3 provides an optional external DC bias that can be applied to the LO input, if there is DC component to the applied RF input. To use this option, transformers T2 and T3 must be carefully chosen to allow the use of a non-zero common- mode level. J9 can be used to enable or disable the part. The chip enable/EN is active low. De-coupling capacitors are provided on the V DD traces. These capacitors should be placed as close to the DV DD pin as possible. Not for new designs
©2010 Peregrine Semiconductor Corp. All rights reserved. Figure 5. Evaluation Board Schematic Place C1,C2,C4,C5 close to DVDD Pin.
0 OHM
1 GND
2 INB
3 INA
4 N/C
5 N/C
7 VDD_2
8 IF_P
9 GND
10 IF_N
51 Ohm
1 MTG4
1 MTG2
1 MTG1
1 MTG3
Figure 14. Package Drawing
©2010 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0242-06 │ UltraCMOS™ RFIC Solutions Sales Offices The Americas Peregrine Semiconductor Corporation
9380 Carroll Park Drive
San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France Tel: +33-1-4741-9173 Fax : +33-1-4741-9173 For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. High-Reliability and Defense Products Americas San Diego, CA, USA Phone: 858-731-9475 Fax: 848-731-9499 Europe/Asia-Pacific Parc Cezanne 1
380 Avenue Archimède
13857 Aix-En-Provence Cedex 3
Peregrine Semiconductor, Asia Pacific (APAC) Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Peregrine Semiconductor, Korea #B-2607, Kolon Tripolis, 210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-943 South Korea Tel: +82-31-728-3939 Fax: +82-31-728-3940 Peregrine Semiconductor K.K., Japan
601 Yaesu Kyodo Building
2-5-9 Yaesu, Chuo-ku Tokyo 104-0028 Japan Tel: +81-3-3527-9841 Fax: +81-3-3527-9848 Not for new designs