PE3236 PEREGRINE | Alldatasheet
Document overview
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Technical content
Features
- 2.2 GHz operation
- ÷10/11 dual modulus prescaler
- Internal phase detector
- Serial, parallel or hardwired programmable
- Low power— 22 mA at 3 V
- Q3236 PLL replacement
- Ultra-low phase noise
- Available in 44-lead PLCC package
Figure 1. Block Diagram
Document No. 70-0026-03 │www.psemi.com ©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Table 1. Pin Descriptions (continued) Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Binary serial data input. Input data entered MSB first. “low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of Sclk. programming of internal counters while in Serial Interface Mode. Parallel data bus bit7 (MSB). Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler. programming of internal counters while in Parallel Interface Mode. clocked into the enhancement register on the rising edge of Sclk. Selects direct interface mode (Bmode=1). register on the rising edge of Hop_WR. Prescaler input from the VCO. 2.2 GHz max frequency.
Description
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0026-03 │UltraCMOS™ RFIC Solutions Note 1: VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level. enhancement register programming or by floating or grounding VDD pin 31. through enhancement register programming. inverting amplifier used for driving LD. PD_D is pulse down when fp leads fc. PD_U is pulse down when fc leads fp. enhancement register programming or by floating or grounding VDD pin 38. high impedance, otherwise LD is a logic low (“0”).
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Table 2. Absolute Maximum Ratings Table 4. ESD Ratings exceeding the specified rating in Table 4. devices are immune to latch-up. Table 3. Operating Ratings Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Table 6. AC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified phase noise performance, the reference input falling edge rate should be faster than 80mV/ns. Parameter is guaranteed through characterization only and is not tested.
100 Hz Offset
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. generates up and down frequency control signals. Figure 4. Functional Block Diagram
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. and powers down the prescaler. a minimum M Counter divide ratio of “2”. and M8 are internally forced low. R5 are internally forced low (“0”). Bmode input “low” and the Smode input “low”. secondary register contents are utilized. Figure 5. This data provides control bits as enabled by asserting the Enh input “low”. Bmode input “low” and the Smode input “high”. as shown in Table 7 on page 9. secondary register contents are utilized.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. register on the rising edge of Sclk, MSB (B0) first.
- After the falling edge of E_WR, the data provide
R4 and R5 are internally forced low (“0”). Table 7. Primary Register Programming Table 8. Enhancement Register Programming *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge.
Document No. 70-0026-03 │www.psemi.com ©2003-2005 Peregrine Semiconductor Corp. All rights reserved. A lock detect output, LD is also provided, via the pin Cext. Cext is the logical “NAND” of PD_U and PD_D waveforms, which is driven through a series 2 kΩ resistor. Connecting Cext to an external shunt capacitor provides integration. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an “AND” function of PD_U and PD_D. Enhancement Register The functions of the enhancement register bits are shown below with all bits active “high”. Table 9. Enhancement Register Bit Functionality two input signals, fp and fc. results in a decrease in VCO frequency. Reserved Bit 1 Reserved Bit 2 Reserved** Bit 3 Power down Power down of all functions except programming interface. Bit 4 Counter load Immediate and continuous load of counter programming as directed by the Bmode and Smode inputs. Bit 5 MSEL output Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Bit 6 Prescaler output Drives the raw internal prescaler output onto the Dout output. Bit 7 fp, fc OE fp, fc outputs disabled.
Document No. 70-0026-03 │www.psemi.com ©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Handling Requirements All surface mount products which do not meet Level 1 moisture sensitivity requirements are processed through dry bake and pack procedure. The necessary data is recorded on the caution label of each shipment. The 44-lead PLCC package is moisture sensitivity Level 3. Level 3 Caution Label The caution label should contain the following information for Level 3 devices: 1. Calculated shelf life in sealed bag: 12 months at <40 °C and <90% relative humidity (RH) 2. Peak package body temperature is 225 °C. 3. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must a) Be mounted within 168 hours of factory conditions <30 °C/60% RH, or b) Be stored at <10% RH 4. Devices require bake, before mounting, if: a) Humidity Indicator Card is > 10% when read at 23 ± 5 °C b) 3a or 3b are not met 5. If baking is required, devices may be baked for 48 hours at 125 +5/-0 °C Note: If device containers cannot be subjected to high temperature or shorter bake times are desired, reference IPC/JEDEC-J-STD-033 for bake procedure. Level and Body temperature defined by: IPC/JEDEC-J-STD-020 For Dry Bake Procedures, see: IPC/JEDEC-J-STD-033 Operator must observe ESD precautions per ESD Control Procedure and Parts Handling and shipping Procedure.
©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0026-03 │UltraCMOS™ RFIC Solutions Figure 9. Package Drawing Table 10. Ordering Information
0.010 X 45°
0.045 X 45°
500 units / T&R 3236-00 PE3236EK PE3236-44PLCC-EVAL KIT 44-lead PLCC 1 / Box
Document No. 70-0026-03 │www.psemi.com ©2003-2005 Peregrine Semiconductor Corp. All rights reserved. Sales Offices The Americas Peregrine Semiconductor Corporation
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San Diego, CA 92121 Tel: 858-731-9400 Fax: 858-731-9499 North Asia Pacific Peregrine Semiconductor K.K. Teikoku Hotel Tower 10B-6 1-1-1 Uchisaiwai-cho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213 Peregrine Semiconductor, Korea #B-2402, Kolon Tripolis, #210 Geumgok-dong, Bundang-gu, Seongnam-si Gyeonggi-do, 463-480 S. Korea Tel: +82-31-728-4300 Fax: +82-31-728-4305 Europe Peregrine Semiconductor Europe Bâtiment Maine 13-15 rue des Quatre Vents F-92380 Garches, France For a list of representatives in your area, please refer to our Web site at: www.psemi.com Data Sheet Identification Advance Information The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice). The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user’s own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp. South Asia Pacific Peregrine Semiconductor, China Shanghai, 200040, P.R. China Tel: +86-21-5836-8276 Fax: +86-21-5836-7652 Space and Defense Products Americas: Tel: 858-731-9453 Europe, Asia Pacific:
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