NAU8223WG

NAU8223 NUVOTON | Alldatasheet

Document overview

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Technical content

NAU8223 Datasheet Rev 1.3 Page 1 of 23 July, 2012 NAU8223 3.1W Stereo Filter-Free Class-D Audio Amplifier

1 Description

The NAU8223 is a stereo high efficiency filter-free Class-D audio amplifier, which is capable of drivi ng a 4 Ω load with up to 3.1W output power. This device provides chip enable pin with extremely low standby current and f ast start-up time of 3.4ms. It has five selectable gain settings (i.e . 0dB, 6dB, 12dB, 18dB and 24dB), which can be cont rolled by a single gain pin. The NAU8223 is ideal for the portable applications of battery drive, as it has advanced features like 87dB PSRR, 91% ability to configure the inputs in either single-ended or differential mode. NAU8223 is available in Miniature QFN-20 package an d TSSOP-20 package. Key Features /square6 Low Quiescent Current:

• 2.1mA at 3.7V for 2 channels
• 3.2mA at 5V for 2 channels /square6 5 Selectable Gain Settings:
• 0dB / 6dB / 12dB / 18dB / 24dB /square6 Powerful Stereo Class-D Amplifier:
• 2ch x 3.1W (4 Ω @ 5V, 10% THD+N)
• 2ch x 1.26W (4 Ω @ 3.7V, 1% THD+N)
• 2ch x 1.76W (8 Ω @ 5V, 10% THD+N)
• 2ch x 0.76W (8 Ω @ 3.7V, 1% THD+N) /square6 Low Output Noise: 20 µV RMS @0dB gain /square6 87dB PSRR @217Hz /square6 Low Current Shutdown Mode /square6 Click-and Pop Suppression

Applications

/square6 Notebooks / Tablet PCs /square6 Personal Media Players / Portable TVs /square6 MP3 Players /square6 Portable Game Players /square6 Digital Camcorders Figure 1: NAU8223Block Diagram

NAU8223Datasheet Rev 1.4 Page 2 of 23 August, 2013

2 Pinout

2.1 NAU8223 QFN 20 (TOP VIEW)

NAU8223Datasheet Rev 1.4 Page 3 of 23 August, 2013

2.2 TSSOP 20 (TOP VIEW)

Part Number Dimension Package Package Material NAU8223YG 4mm x 4mm QFN-20 Pb-Free NAU8223WG 4.4mm x 6.5mm TSSOP-20 Pb-Free

NAU8223Datasheet Rev 1.4 Page 4 of 23 August, 2013

3 Pin Descriptions

QFN TSSOP Name Type Functionality 1 9 OUTRP Analog Output Right Channel Positive BTL Output 2 10 VDD Supply Power Supply 3 11 NC NC No Connect 4 12 EN Digital Input Chip Enable (High = Enable; L ow = PD) 5 13 INR Analog Input Right Channel Negative Input 6 14 IPR Analog Input Right Channel Positive Input 7 15 GS Analog Input 5 Selectable Gain Setting (0dB / 6dB / 12dB / 18dB / 24dB) 8 16 VDD Supply Power Supply 9 17 VSS Supply Ground 10 18 IPL Analog Input Left Channel Positive Input 11 19 INL Analog Input Left Channel Negative Input 12 20 NC NC No Connect 13 1 NC NC No Connect 14 2 VDD Supply Power Supply 15 3 OUTLP Analog Output Left Channel Positive BTL Output 16 4 VSS Supply Ground 17 5 OUTLN Analog Output Left Channel Negative BTL Output 18 6 VDD Supply Power Supply 19 7 OUTRN Analog Output Right Channel Negative BTL Output 20 8 VSS Supply Ground 21 - Ex-Pad Analog Input Thermal Tab (must be conne cted to VSS, QFN-20 package, only) Notes 1. Pins designated as NC (Not Internally Connected) should be left as no-connection Table 1: NAU8223 Pin description

NAU8223Datasheet Rev 1.4 Page 5 of 23 August, 2013

4 Electrical Characteristics

Conditions: EN = VDD = 5V, VSS = 0V, Av = 12dB Z L = ∞, Bandwidth = 20Hz to 22kHz, T A = 25 oC Parameter Symbol Comments/Conditions Min Typ Max Units Power Delivered Output Power (per channel) P out ZL = 4 Ω + 33µH THD + N = 10% VDD = 5.0V 3.1 W VDD = 3.7V 1.57 ZL = 4 Ω + 33µH THD + N = 1% VDD = 5.0V 2.46 VDD = 3.7V 1.26 ZL = 8 Ω + 68µH THD + N = 10% VDD = 5.0V 1.76 VDD = 3.7V 0.95 ZL = 8 Ω + 68µH THD + N = 1% VDD = 5.0V 1.41 VDD = 3.7V 0.76 Parameter Symbol Comments/Conditions Min Typ Max Units Chip Enable (EN) Voltage Enable High V EN_H VDD = 2.5V to 5.5V 1.4 V Voltage Enable Low V EN_L VDD = 2.5V to 5.5V 0.4 V Input Leakage Current -1 +1 µA Thermal and Current Protection Thermal Shutdown Temperature 130 oC Thermal Shutdown Hysteresis 15 oC Short circuit Threshold I LIMIT 2.1 A Gain Setting Voltage Gain A V Tie GS to VSS 24 dB GS Connect VSS through 100k ± 5% Tie GS pin to VDD 12 GS Connect VDD through 100k ± 5% Floating Node 0 Differential Input Resistance R IN AV = 24dB 35 kΩ AV = 18dB 70 AV = 12dB 140 AV = 6dB 280 AV = 0dB 558

NAU8223Datasheet Rev 1.4 Page 6 of 23 August, 2013 Electrical Characteristics (continued) Conditions: EN = VDD = 5V, VSS = 0V, Av = 12dB, Z L = ∞, Bandwidth = 20Hz to 22kHz, T A = 25 oC Parameter Symbol Comments/Conditions Min Typ Max Units Normal Operation Quiescent Current Consumption I QUI VDD = 3.7V 2.1 mA VDD = 5V 3.17 mA Shut Down Current I OFF EN = 0 0.1 µA Oscillator Frequency f OSC 300 kHz Efficiency η 91 % Start Up Time T start 3.4 msec Output Offset Voltage V OS ±1 ±4 mV Common Mode Rejection Ratio CMRR f IN = 1kHz 80 dB Click-and-Pop Suppression Into Shutdown (Z L=8 Ω) A Weighted -72 dBV Power Supply Rejection Ratio DC PSRR VDD = 2.5V to 5.5V 98 dB AC PSRR* VRIPPLE = 0.2Vpp@217Hz** V RIPPLE = 0.2Vpp@1KHz VRIPPLE = 0.2Vpp@10KHz dB Channel Crosstalk f IN = 1kHz, ZL = 8 Ω + 68µH -101 dB *Measured with 0.1uF capacitor on V DD and Battery supply ** Measured with 2.2uF input capacitor. Parameter Symbol Comments/Conditions Min Typ Max Units Noise Performance Av = 0dB (A-weighted) 20 µV RMS Av = 6dB (A-weighted) 21 Av = 12dB (A-weighted) 27 Av = 18dB (A-weighted) 36 Av = 24dB (A-weighted) 52 The following setup is used to measure the above parameters

NAU8223Datasheet Rev 1.4 Page 7 of 23 August, 2013 Absolute Maximum Ratings Condition Min Max Units Analog supply -0.50 +5.50 V Industrial operating temperature -40 +85 °C Storage temperature range -65 +150 °C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. Operating Conditions Condition Symbol Min Typical Max Units Analog supply range VDD 2.50 3.7 5.50 V Ground VSS 0 V

NAU8223Datasheet Rev 1.4 Page 8 of 23 August, 2013

6 Special Feature Description

The NAU8223 offers excellent quantity performance as high efficiency, high output power and low quiescent current. It also provides the following special features.

6.1 Gain Setting

The NAU8223 has a GS pin, which can control five se lectable gain settings (i.e. 0dB / 6dB / 12dB / 18d B / 24dB). GS Pin Configuration Internal Gain (dB) GS tie to VSS 24 GS connect to VSS through 100k Ω ± 5% resistor GS tie to VDD 12 GS connect to VDD through 100k Ω ± 5% resistor Floating (open node) 0

6.2 Device Protection

The NAU8223 includes device protection for three op erating scenarios. They are 1. Thermal Overload 2. Short circuit 3. Supply under voltage

6.2.1 Thermal Overload Protection

When the device internal junction temperature reaches 130°C, the NAU8223 will disable the output drive rs. When the device cools down and a safe operating temperature of 115°C has been reached for at least about 47mSec, the output drivers will be enabled again.

6.2.2 Short Circuit Protection

If a short circuit is detected on any of the pull-up or pull-down devices on the output drivers for at least 14uSec, the output drivers will be disabled for 47mSec. The output drivers will then be enabled again and check for the short circuit. If the short circuit is still present, the output drivers are disabled after 14uSec. This cycle will continue until the short circuit is removed. The short circuit threshold is set at 2.1A.

6.2.3 Supply under Voltage Protection

If the supply voltage drops under 2.1V, the output drivers will be disabled while the NAU8223 control circuitry still operates. This will avoid the battery supply to drag down too low before the host processor can safely shut down the devices on the system. If the supply drops further below 1.0v the internal power on reset activated and puts the entire device in power down state.

NAU8223Datasheet Rev 1.4 Page 9 of 23 August, 2013

6.3 Power up and Power down Control

When the supply voltage ramps up, the internal power on reset circuit gets triggered. At this time all internal circuits will be set to power down state. The device can be enabled by setting the EN pin high. Upon setting the EN pin high, the device will go through an internal power up sequence in order to minimize ‘pops’ on the speaker output . The complete power up sequence will take about 3.4mSec. The device will power down in about 30uSec, when the EN pin is set low. It is important to keep the input signal at zero amplitude or enable the mute condition in order to minimize the ‘pops’ when the EN pin is toggled.

NAU8223Datasheet Rev 1.4 Page 10 of 23 August, 2013

7 Typical Operating Characteristics

Conditions: EN = V DD = 5V, VSS = 0V, Av = 12dB, Z L = ∞, Bandwidth = 20Hz to 22kHz, T A = 25 oC, unless otherwise noted 100 0 1 2 3 4 Efficiency(%) Output Power(W) Efficiency Vs Output Power (V DD = 5.0V) ZL=4Ω+33uH ZL=8Ω+68uH 100 0 0.5 1 1.5 2 Efficiency(%) Output Power(W) Efficiency Vs Output Power (V DD = 3.7V) ZL=4Ω+ 33uH ZL=8Ω +68uH 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) THD+N vs Frequency (V DD = 3.7V, ZL= 8Ω+ 68uH) Pout 0.2W Pout 0.4W 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) THD+N vs Frequency (V DD = 4.2V, ZL= 8Ω+ 68uH) Pout 0.2W Pout 0.6W

NAU8223Datasheet Rev 1.4 Page 11 of 23 August, 2013 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) THD+N vs Frequency (V DD = 5V, ZL= 8Ω+ 68uH) Pout 0.2W Pout 1.2W 0.001 0.01 0.1 100 0 0.5 1 1.5 THD+N (%) Pout (W) THD+N vs Pout (V DD = 3.7V, ZL = 8Ω+ 68uH) f 100Hz f 1kHz f 6kHz 0.001 0.01 0.1 100 0 0.5 1 1.5 2 THD+N (%) Pout (W) THD+N vs Pout (V DD = 4.2V, ZL= 8Ω+ 68uH) f 100Hz f 1kHz f 6kHz 0.001 0.01 0.1 100 0 1 2 3 THD+N (%) Pout (W) THD+N vs Pout (V DD = 5V, ZL=8Ω + 68uH) f 100Hz f 1kHz f 6kHz

NAU8223Datasheet Rev 1.4 Page 12 of 23 August, 2013 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) THD+N vs Frequency (V DD = 3.7V, ZL= 4Ω+ 33uH) Pout 0.2W Pout 0.8W 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency(Hz) THD+N vs Frequency (V DD = 4.2V, ZL= 4Ω+ 33uH) Pout 0.2W Pout 1W 0.001 0.01 0.1 20 200 2000 20000 THD+N(%) Frequency (Hz) THD+N vs Frequency (V DD = 5V, ZL= 4Ω+ 33uH ) Pout 1.5W Pout 2W 0.001 0.01 0.1 100 0 1 2 3 THD+N (%) Pout (W) THD+N vs Pout (V DD = 3.7V, ZL= 4Ω+ 33uH) f = 100Hz f = 1kHz f = 6kHz

NAU8223Datasheet Rev 1.4 Page 13 of 23 August, 2013 0.001 0.01 0.1 100 0 1 2 3 THD+N (%) Pout (W) THD+N vs Pout (V DD = 4.2V, ZL= 4Ω+ 33uH) f = 100Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 100 0 1 2 3 4 THD+N (%) Pout (W) THD+N vs Pout (V DD = 5V, ZL= 4Ω+ 33uH) f = 100Hz f = 1kHz f = 6kHz -10 20 200 2000 20000 Gain (dB) Frequency (Hz) Gain vs Frequency Gain 0dB Gain 6dB Gain 12dB Gain 18dB Gain 24dB -120 -100 -80 -60 -40 -20 20 200 2000 20000 Level (dB) Frequency (Hz) Crosstalk vs Frequency Left to Right Right to Left

NAU8223Datasheet Rev 1.4 Page 14 of 23 August, 2013 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 PSRR (dB) Supply Voltage (V) AC PSRR vs Supply Voltage PSRR @Gain 0dB, 1KHz -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 20 200 2000 20000 PSRR (dB) Frequency (Hz) AC PSRR vs Frequency PSRR @ Gain 0dB

NAU8223Datasheet Rev 1.4 Page 15 of 23 August, 2013 0.5 1.5 2.5 3.5 2.5 3.5 4.5 5.5 Supply Current(mA) Supply Voltage (V) SupplyVoltage vs SupplyCurrent

NAU8223Datasheet Rev 1.4 Page 16 of 23 August, 2013

8 Application Information

8.1 Application diagram

P.S. GS Pin – The 100k Ω resistors are optional. GS can be floating for internal gain setting = 0dB. Please refer Section 2.1 (Gain Setting) for the detailed explanation.

NAU8223Datasheet Rev 1.4 Page 17 of 23 August, 2013

8.2 Component selection

An ac coupling capacitor (Cin) is used to block the dc content from the input source. The input resistance of the amplifier (Rin) together with the Cin will act as a high pass filter. So depending on the required cut off frequency the Cin can be calculated by using the following formula Where is the desired cut off frequency of the Hi gh pass filter. Input Output Cin Rin(Input Resistance) Amplifier Bypass Capacitors Bypass capacitors are required to remove the ac ripple on the VDD pins. The value of these capacitors depends on the length of the VDD trace. In most cases, 10uF and 0.1uF are enough to get the good performance.

8.3 Layout considerations

The NAU8223 QFN package uses an exposed pad on the bottom side of the package to dissipate excess power from the output drivers. This pad must be soldered carefully to the PCB for proper operation of the NAU8223. Th is pad is internally connected to Vss. A typical layout is shown below.

NAU8223Datasheet Rev 1.4 Page 18 of 23 August, 2013 The PCB has to be designed in such a manner that it should have nine vias in 3x3 grid under NAU8223. T he vias should have hole size of 12mil and a spacing of 30mils. The pad size of the vias is 24mils. The vias on the top side of the board should be connected with a copper pour that has an area of 2mm x 2mm, centered underneath the NAU8223. The nine vias should connect to copper pour area on the bottom of the PCB. It is preferred to pour the complete bottom side of the board with Vss. Also good PCB layout and grounding techniques are essential to get the good audio performance. It is better to use low resistance traces as these devices are driving low impedance loads. The resistance of the traces has a significant effect on the output power delivered to the load. In order to dissipate more heat, use wide traces for the power and ground lines.

8.4 Class D without filter

The NAU8223 is designed for use without any filter on the output line. That means the outputs can be directly connected to the speaker in the simplest configuration. This type of filter less design is suitable for portable applications where the speaker is very close to the amplifier. In other words, this is preferable in applications where the l ength of the traces between the speaker and amplifier is short. The following diagram shows this simple configuration. NAU8223 outputs connected to speaker without filter circuit

8.5 Class D with filter

In some applications, the shorter trace lengths are not possible because of speaker size limitations a nd other layout reasons. In these applications, the long traces will cause EMI issues. There are two types of filter circuits available to reduce the EMI effects. These are ferrite bead and LC filters. Ferrite Bead filter The ferrite bead filters are used to reduce the high frequency emissions. The typical circuit diagram is shown in the figure. NAU8223 outputs connected to speaker with Ferrite Bead filter

NAU8223Datasheet Rev 1.4 Page 19 of 23 August, 2013 The characteristic of ferrite bead is such that it offers higher impedance at high frequencies. For be tter EMI performance select ferrite bead which offers highest impedance at high frequencies, so that it will attenuate the signals at higher frequencies. Usually the ferrite beads have low impedance in the audio range, so it will act as a pass through filter in the audio frequency range. LC filter The LC filter is used to suppress the low frequency emissions. The following diagram shows the NAU8223 outputs connected to the speaker with LC filter circuit. R L is the resistance of the speaker coil. NAU8223 outputs connected to speaker with LC filter Standard Low pass LCR filter The following are the equations for the critically damped ( ζ = 0.707) standard low pass LCR filter /uni0032/g2024/g1858/g1855/uni0009/uni0009 /g3404 /g2869 /uni221A/g4666/g3013/g3004 /g4667 /g1858/g1855 is the cutoff frequency /g2014 /g3404 /uni0030/uni002E/uni0037/uni0030/uni0037 /g3404/uni0031 /uni0032/g1844/uni2217 /uni221A/g1838 /g1829 The L and C values for differential configuration can be calculated by duplicating the single ended co nfiguration values and substituting R L = 2R.

NAU8223Datasheet Rev 1.4 Page 20 of 23 August, 2013

8.6 NAU8223 EMI performance

The NAU8223 includes a spread spectrum oscillator f or reduced EMI. The PWM oscillator frequency typica lly sweeps in a range of 300 kHz +/- 15 kHz in order to spread the energy of the PWM pulses over a larger frequency band. In addition, slew rate control on the output drivers allows the application of ‘filter less’ loads, while suppressing EMI at high frequencies. The below graph shows the EMI per formance of NAU8223 with ferrite beads and speaker cable length of 30cm.

NAU8223Datasheet Rev 1.4 Page 21 of 23 August, 2013

9 Package Dimensions

9.1 QFN20L 4X4 MM^2, Pitch:0.50 MM T O P V I E W B O T T O M V I E W 1 1 2 0 1 0 1 5 1 6 1 6 1 5 1 1 1 0 2 0

NAU8223Datasheet Rev 1.4 Page 22 of 23 August, 2013 9.2 TSSOP20L 4.4X6.5 MM^2, Pitch:0.65 MM

NAU8223Datasheet Rev 1.4 Page 23 of 23 August, 2013 Nuvoton Part Number Description Version History VERSION DATE PAGE DESCRIPTION Rev1.0 March, 2012 P.8, P.9 Preliminary Revision Updated typical characteristics Rev1.1 March, 2012 P.2, P.10 Updated Pin No. Added application diagrams Rev1.2 May, 2012 NA Updated Electrical Characteristics Rev1.3 July, 2012 P.4, P.5, P.10-P.18 Added Application information section Added/Modified Typical operating Characteristics Updated Electrical Characteristics Rev1.4 August, 2013 P.4, P.5, P.22,P.23 Added TSSOP20 Package information section Table 1: Version History Important Notice Nuvoton products are not designed, intended, author ized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nuvoton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. Package Type: Y = 20-Pin QFN Package NAU8223 _G Package Material: G = Pb-free Package W = 20-Pin TSSOP Package