MINI55TDE

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Apr 18, 2017 Page 1 of 74 Rev.1.00 MINI55 SERIES DATASHEET ARM® Cortex® -M0 32-bit Microcontroller NuMicro® Family Mini55 Series Datasheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com

Apr 18, 2017 Page 2 of 74 Rev.1.00 MINI55 SERIES DATASHEET Table of Contents

Apr 18, 2017 Page 3 of 74 Rev.1.00 MINI55 SERIES DATASHEET

Apr 18, 2017 Page 4 of 74 Rev.1.00 MINI55 SERIES DATASHEET

Apr 18, 2017 Page 6 of 74 Rev.1.00 MINI55 SERIES DATASHEET List of Tables

Apr 18, 2017 Page 7 of 74 Rev.1.00 MINI55 SERIES DATASHEET

1 GENERAL DESCRIPTION

The NuMicro® Mini55 series 32-bit microcontroller is embedded with ARM® Cortex® -M0 core for industrial control and applications which require high performance, high integration, and low cost. The Cortex® -M0 is the newest ARM® embedded processor with 32-bit performance at a cost equivalent to the traditional 8-bit microcontroller. The Mini55 series can run up to 48 MHz and operate at 2.1V ~ 5.5V, -40℃ ~ 105℃, and thus can afford to support a variety of industrial control and applications which need high CPU performance. The Mini55 series offers 17.5K-bytes embedded program flash, size configurable Data Flash (shared with program flash), 2K-byte flash for the ISP, and 2K-byte SRAM. Many system level peripheral functions, such as I/O Port, Timer, UART, SPI, I2C, PWM, ADC, Watchdog Timer, Analog Comparator and Brown-out Detector, have been incorporated into the Mini55 series in order to reduce component count, board space and system cost. These useful functions make the Mini55 series powerful for a wide range of applications. Additionally, the Mini55 series is equipped with ISP (In-System Programming) and ICP (In-Circuit Programming) functions, which allow the user to update the program memory without removing the chip from the actual end product. The Mini55 series also supports In-Application-Programming (IAP) function, user switches the code executing without the chip reset after the embedded flash updated.

Apr 18, 2017 Page 8 of 74 Rev.1.00 MINI55 SERIES DATASHEET

2 FEATURES

 Core  ARM® Cortex® -M0 core running up to 48 MHz  One 24-bit system timer  Supports low power Idle mode  A single-cycle 32-bit hardware multiplier  NVIC for the 32 interrupt inputs, each with 4-level of priority  Supports Serial Wire Debug (SWD) interface and two watchpoints/four breakpoints  Built-in LDO for wide operating voltage: 2.1V to 5.5V  Memory  17.5 KB Flash memory for program memory (APROM)  Configurable Flash memory for data memory (Data Flash)  2 KB Flash for loader (LDROM)  2 KB SRAM for internal scratch-pad RAM (SRAM)  Clock Control  Programmable system clock source  Switch clock sources on-the-fly  Support 4 ~ 24 MHz external high speed crystal oscillator (HXT) for precise timing operation  Support 32.768 kHz external low speed crystal oscillator (LXT) for idle wake-up and system operation clock  Built-in 48 MHz internal high speed RC oscillator (HIRC) for system operation (1% accuracy at 250C, 5V)  Dynamically calibrating the HIRC OSC to 48 MHz ±2% from -40℃ to 105℃ by external 32.768K crystal oscillator (LXT)  Built-in 10 kHz internal low speed RC oscillator (LIRC) for Watchdog Timer and wake-up operation  I/O Port  Up to 33 general-purpose I/O (GPIO) pins for LQFP-48 package  Four I/O modes:  Quasi-bidirectional input/output  Push-Pull output  Open-Drain output  Input only with high impendence  Optional Schmitt trigger input  Timer  Provides two channel 32-bit Timers; one 8-bit pre-scaler counter with 24-bit up- timer for each timer  Supports Event Counter mode

Apr 18, 2017 Page 9 of 74 Rev.1.00 MINI55 SERIES DATASHEET  Supports Toggle Output mode  Supports external trigger in Pulse Width Measurement mode  Supports external trigger in Pulse Width Capture mode  Support Continuous Capture function can continuous capture 4 edge on one signal  WDT (Watchdog Timer)  Programmable clock source and time-out period  Supports wake-up function in Power-down mode and Idle mode  Interrupt or reset selectable on watchdog time-out  PWM  Up to three built-in 16-bit PWM generators, providing six PWM outputs or three complementary paired PWM outputs  Individual clock source, clock divider, 8-bit pre-scalar and dead-time generator for each PWM generator  PWM interrupt synchronized to PWM period  Supports edge-alignment or center-alignment  Supports fault detection  UART (Universal Asynchronous Receiver/Transmitters)  Two UART devices  Buffered receiver and transmitter, 16-byte FIFO for first UART (UART0), and 4- byte FIFO for second UART (UART1)  Optional flow control function (CTSn and RTSn) in first UART 0 only  Supports IrDA (SIR) function  Programmable baud-rate generator up to 1/16 system clock  Supports RS-485 function  SPI (Serial Peripheral Interface)  One SPI device  Master up to 25 MHz, and Slave up to 10 MHz  Supports Master/Slave mode  Full-duplex synchronous serial data transfer  Variable length of transfer data from 8 to 32 bits  MSB or LSB first data transfer  RX latching data can be either at rising edge or at falling edge of serial clock  TX sending data can be either at rising edge or at falling edge of serial clock  Supports Byte Suspend mode in 32-bit transmission  I2C  Supports Master/Slave mode  Bidirectional data transfer between masters and slaves  Multi-master bus (no central master)

Apr 18, 2017 Page 10 of 74 Rev.1.00 MINI55 SERIES DATASHEET  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer  Programmable clocks allow for versatile rate control  Supports multiple address recognition (four slave addresses with mask option)  ADC (Analog-to-Digital Converter)  10-bit SAR ADC with 500 kSPS  Up to 12-ch single-end input and one internal input from band-gap  Conversion started either by software trigger or external pin trigger  Analog Comparator  Two analog comparators with programmable 16-level internal voltage reference  Built-in CRV (comparator reference voltage)  Hardware Divider  Signed (two’s complement) integer calculation  32-bit dividend with 16-bit divisor calculation capacity  32-bit quotient and 32 -bit remainder outputs (16 -bit remainder with sign extends to 32-bit)  Divided by zero warning flag  6 HCLK clocks taken for one cycle calculation  Waiting for calculation ready automatically when reading quotient and remainder  ISP (In-System Programming), ICP (In-Circuit Programming), and IAP (In-Application- Programming) update  BOD (Brown-out Detector)  With 8 programmable threshold levels:  Supports Brown-out interrupt and reset option  96-bit unique ID  LVR (Low Voltage Reset)  Threshold voltage level: 2.0V  Operating Temperature: -40℃~105℃  Reliability: EFT > ± 3KV, ESD HBM pass 6KV  Packages:  Green package (RoHS)  48-pin LQFP (7x7), 33-pin QFN (4x4)

Apr 18, 2017 Page 11 of 74 Rev.1.00 MINI55 SERIES DATASHEET

3 ABBREVIATIONS

ACMP Analog Comparator Controller ADC Analog-to-Digital Converter AHB Advanced High-Performance Bus APB Advanced Peripheral Bus BOD Brown-out Detection DAP Debug Access Port FIFO First In, First Out FMC Flash Memory Controller GPIO General-Purpose Input/Output HCLK The Clock of Advanced High-Performance Bus HIRC 48 MHz Internal High Speed RC Oscillator HXT 4~24 MHz External High Speed Crystal Oscillator ICP In Circuit Programming ISP In System Programming ISR Interrupt Service Routine LDO Low Dropout Regulator LIRC 10 kHz internal low speed RC oscillator (LIRC) LXT 32.768 kHz External Low Speed Crystal Oscillator NVIC Nested Vectored Interrupt Controller PCLK The Clock of Advanced Peripheral Bus PLL Phase-Locked Loop PWM Pulse Width Modulation SPI Serial Peripheral Interface SPS Samples per Second TMR Timer Controller UART Universal Asynchronous Receiver/Transmitter UCID Unique Customer ID WDT Watchdog Timer Table 3-1 List of Abbreviations

Apr 18, 2017 Page 12 of 74 Rev.1.00 MINI55 SERIES DATASHEET

4 PARTS INFORMATION LIST AND PIN CONFIGURATION

NuMicro® Mini55 Series Naming Rule 4.1 Mini55-X X X ARM–Based 32-bit Microcontroller CPU Core Corte® -M0 Flash ROM 55 : 17.5 KB Flash ROM Temperature Reserved Package Type L: LQFP 48 7x7mm T: QFN 33 4x4mm E: -40oC ~ +105oC Figure 4.1-1 NuMicro® Mini55 Series Selection Code

Apr 18, 2017 Page 13 of 74 Rev.1.00 MINI55 SERIES DATASHEET NuMicro® Mini55 Series Product Selection Guide 4.2 Part Number APROM RAM Data Flash ISP Loader ROM I/O Timer (32-bit) Connectivity Comp. PWM ADC (10-bit) ISP ICP IAP IRC 48MHz Package UART SPI I2C MINI55LDE 17.5 KB 2 KB Configurable 2 KB 33 2 2 1 1 2 6 12 v v LQFP48 MINI55TDE 17.5 KB 2 KB Configurable 2 KB 29 2 2 1 1 2 6 12 v v QFN33(4x4) Table 4.2-1 NuMicro® Mini55 Series Product Selection Guide

Apr 18, 2017 Page 14 of 74 Rev.1.00 MINI55 SERIES DATASHEET PIN CONFIGURATION 4.3

4.3.1 LQFP 48-pin

P1.6 TX1, CPP0, AIN5, P1.5 nRESET AVSS AIN8, P5.4 CPP1, AIN7, P3.1 AIN9, CPP1, SDA, T0, P3.4 AIN10, CPP1, SCL, T1, P3.5 CPP1, T0EX, STADC, INT0, P3.2 P5.1, XT_OUT P5.0, XT_IN VSS P5.2, INT1 LDO_CAP P2.2, PWM0 P2.3, PWM1 P2.4, PWM2, RX1 P5.5 P3.6, CKO,T1EX,CPO0, AIN11 P0.7, SPICLK P4.6, ICE_CLK P0.6, MISO P0.5, MOSI P0.4, SPISS,PWM5 P2.5, PWM3, TX1 P2.6, PWM4, CPO1 NC P4.7, ICE_DAT NC INT0, CPP0, TX0 ,AIN3,P1.3 CPP0, RX0 ,AIN2, P1.2 RX1, CPN0,AIN4,P1.4 CPP0, AIN1,P1.0 ADC_VREF,AIN0,P5.3 NC AVDD NC TX0, CTSn0, P0.0 SPISS, RX0, RTSn0, P0.1 VDD NC CPN1, AIN6, P3.0 NC NC P2.7 NC P3.7 NC Figure 4.3-1 NuMicro® Mini55 Series LQFP 48-pin Diagram

Apr 18, 2017 Page 15 of 74 Rev.1.00 MINI55 SERIES DATASHEET

4.3.2 QFN 33-pin

TX1, CPP0,AIN5, P1.5 AIN8, P5.4 CPN1,AIN6, P3.0 CPP1,AIN7, P3.1 AIN9, CPP1, SDA, T0, P3.4 AIN10, CPP1, SCL, T1, P3.5 P5.1,XT_OUT P5.0,XT_IN VSS P5.2,INT1 P2.2, PWM0 P2.3, PWM1 P2.4, PWM2, RX1 P3.6, CKO,T1EX,CPO0, AIN11 P0.7, SPICLK P4.6, ICE_CLK P0.6, MISO P0.5, MOSI P0.4, SPISS,PWM5 P2.5, PWM3, TX1 P2.6, PWM4,CPO1 P4.7, ICE_DAT INT0, CPP0,TX0, AIN3, P1.3 CPP0,RX0, AIN2, P1.2 RX1, CPN0,AIN4, P1.4 CPP0,AIN1, P1.0 TX,CTSn, P0.0 VDD SPISS,RX,RTSn, P0.1 ADC_VREF, AIN0,P5.3

33 VSS

CPP1, T0EX,STADC,INT0, P3.2 nRESET Figure 4.3-2 NuMicro® Mini55 Series QFN 33-pin Diagram

Apr 18, 2017 Page 16 of 74 Rev.1.00 MINI55 SERIES DATASHEET Pin Description 4.4 Pin Number Pin Name Pin Type Description LQFP 48-pin QFN 33-pin

1 NC Not connected

P1.5 I/O General purpose digital I/O pin AIN5 AI ADC analog input pin ACMP0_P AI Analog comparator positive input pin TX1 O UART1 transmitter output pin 3 2 nRESET I(ST) The Schmitt trigger input pin for hardware device reset. A “Low” on this pin for 768 clock counter of Internal RC 48 MHz while the system clock is running will reset the device. nRESET pin has an internal pull-up resistor allowing power-on reset by simply connecting an external capacitor to GND. 4 3 P3.0 I/O General purpose digital I/O pin AIN6 AI ADC analog input pin ACMP1_N AI Analog comparator negative input pin 5 33 AVSS AP Ground pin for analog circuit 6 4 P5.4 I/O General purpose digital I/O pin AIN8 AI ADC analog input pin 7 5 P3.1 I/O General purpose digital I/O pin AIN7 AI ADC analog input pin ACMP1_P AI Analog comparator positive input pin 8 6 P3.2 I/O General purpose digital I/O pin INT0 I External interrupt 0 input pin STADC I ADC external trigger input pin T0EX I Timer 0 external capture/reset trigger input pin ACMP1_P AI Analog comparator positive input pin 9 7 P3.4 I/O General purpose digital I/O pin T0 I/O Timer 0 external event counter input pin SDA I/O I2C data I/O pin

Apr 18, 2017 Page 17 of 74 Rev.1.00 MINI55 SERIES DATASHEET ACMP1_P AI Analog comparator positive input pin AIN9 AI ADC analog input pin 10 8 P3.5 I/O General purpose digital I/O pin T1 I/O Timer 1 external event counter input pin SCL I/O I2C clock I/O pin ACMP1_P AI Analog comparator positive input pin AIN10 AI ADC analog input pin 11 P3.7 I/O General purpose digital I/O pin

12 NC Not connected

13 NC Not connected

P3.6 I/O General purpose digital I/O pin ACMP0_O O Analog comparator output pin CKO O Frequency divider output pin T1EX I Timer 1 external capture/reset trigger input pin AIN11 AI ADC analog input pin 15 10 P5.1 I/O General purpose digital I/O pin XT_OUT O The output pin from the internal inverting amplifier. It emits the inverted signal of XT_IN. 16 11 P5.0 I/O General purpose digital I/O pin XT_IN I The input pin to the internal inverting amplifier. The system clock could be from external crystal or resonator. VSS P Ground pin for digital circuit

18 LDO_CAP P LDO output pin

19 P5.5 I/O General purpose digital I/O pin User program must enable pull-up resistor in the QFN-33 package. 20 13 P5.2 I/O General purpose digital I/O pin INT1 I External interrupt 1 input pin

21 NC Not connected

22 14 P2.2 I/O General purpose digital I/O pin

Apr 18, 2017 Page 18 of 74 Rev.1.00 MINI55 SERIES DATASHEET PWM0 O PWM0 output of PWM unit 23 15 P2.3 I/O General purpose digital I/O pin PWM1 O PWM1 output of PWM unit 24 16 P2.4 I/O General purpose input/output digital pin PWM2 O PWM2 output of PWM unit RX1 I UART1 data receiver input pin 25 17 P2.5 I/O General purpose digital I/O pin PWM3 O PWM3 output of PWM unit TX1 O UART1 transmitter output pin 26 18 P2.6 I/O General purpose digital I/O pin PWM4 O PWM4 output of PWM unit ACMP1_O O Analog comparator output pin 27 P2.7 I/O General purpose digital I/O pin

28 NC Not connected

P4.6 I/O General purpose digital I/O pin ICE_CLK I Serial wired debugger clock pin 30 20 P4.7 I/O General purpose digital I/O pin ICE_DAT I/O Serial wired debugger data pin

31 NC Not connected

P0.7 I/O General purpose digital I/O pin SPICLK I/O SPI serial clock pin 33 22 P0.6 I/O General purpose digital I/O pin MISO I/O SPI MISO (master in/slave out) pin 34 23 P0.5 I/O General purpose digital I/O pin MOSI O SPI MOSI (master out/slave in) pin 35 24 P0.4 I/O General purpose digital I/O pin SPISS I/O SPI slave select pin PWM5 O PWM5 output of PWM unit 36 NC Not connected 37 25 P0.1 I/O General purpose digital I/O pin RTSn O UART0 RTS pin

Apr 18, 2017 Page 19 of 74 Rev.1.00 MINI55 SERIES DATASHEET RX0 I UART0 data receiver input pin SPISS I/O SPI slave select pin 38 26 P0.0 I/O General purpose digital I/O pin CTSn I UART0 CTS pin TX0 O UART0 transmitter output pin

39 NC Not connected

40 NC Not connected

P5.3 I/O General purpose digital I/O pin AIN0 AI ADC analog input pin ADC VREF AI External voltage reference of ADC VDD P Power supply for digital circuit

43 AVDD P Power supply for analog circuit

P1.0 I/O General purpose digital I/O pin AIN1 AI ADC analog input pin ACMP0_P AI Analog comparator positive input pin 45 30 P1.2 I/O General purpose digital I/O pin AIN2 AI ADC analog input pin RX I UART data receiver input pin ACMP0_P AI Analog comparator positive input pin 46 31 P1.3 I/O General purpose digital I/O pin AIN3 AI ADC analog input pin TX O UART transmitter output pin ACMP0_P AI Analog comparator positive input pin INT0 I External interrupt 0 input pin 47 32 P1.4 I/O General purpose digital I/O pin AIN4 I/O PWM5: PWM output/Capture input ACMP0_N AI Analog comparator negative input pin RX1 I UART1 data receiver input pin 48 P1.6 I/O General purpose digital I/O pin Table 4.4-1 NuMicro® Mini55 Series Pin Description [1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pin, ST: Schmitt trigger, A: Analog input.

Apr 18, 2017 Page 20 of 74 Rev.1.00 MINI55 SERIES DATASHEET

5 BLOCK DIAGRAM

NuMicro® Mini55 Block Diagram 5.1 Figure 5.1-1 NuMicro® Mini55 Series Block Diagram

Apr 18, 2017 Page 21 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6 FUNCTIONAL DESCRIPTION

ARM® Cortex® -M0 Core 6.1

6.1.1 Overview

The Cortex® -M0 processor, a configurable, multistage, 32-bit RISC processor, has an AMBA AHB-Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The processor can execute Thumb code and is compatible with other Cortex ® -M profile processors. The profile supports two modes - Thread mode and Handler mode. Handler mode is entered as a result of an exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset and can be entered as a result of an exception return. Figure 6.1-1 shows the functional controller of the processor. Cortex-M0 Processor core Nested Vectored Interrupt Controller (NVIC) Breakpoint and Watchpoint unit Debugger interface Bus matrix Debug Access Port (DAP) DebugCortex-M0 processor Cortex-M0 components Wakeup Interrupt Controller (WIC) Interrupts Serial Wire or JTAG debug port AHB-Lite interface Figure 6.1-1 Functional Block Diagram

6.1.2 Features

 A low gate count processor  ARMv6-M Thumb® instruction set  Thumb-2 technology  ARMv6-M compliant 24-bit SysTick timer  A 32-bit hardware multiplier  System interface supported with little-endian data accesses  Ability to have deterministic, fixed-latency, interrupt handling  Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to facilitate rapid interrupt handling  C Application Binary Interface compliant exception model: This is the ARMv6-M, C Application Binary Interface (C-ABI) compliant exception model that enables the use of pure C functions as interrupt handlers  Low power Idle mode entry using the Wait For Interrupt (WFI), Wait For Event (WFE) instructions, or return from interrupt sleep-on-exit feature

Apr 18, 2017 Page 22 of 74 Rev.1.00 MINI55 SERIES DATASHEET  NVIC  32 external interrupt inputs, each with four levels of priority  Dedicated Non-maskable Interrupt (NMI) input  Supports for both level-sensitive and pulse-sensitive interrupt lines  Supports Wake-up Interrupt Controller (WIC) and, providing Ultra-low Power Idle mode  Debug support  Four hardware breakpoints  Two watch points  Program Counter Sampling Register (PCSR) for non-intrusive code profiling  Single step and vector catch capabilities  Bus interfaces  Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all system peripherals and memory  Single 32-bit slave port that supports the DAP (Debug Access Port)

Apr 18, 2017 Page 23 of 74 Rev.1.00 MINI55 SERIES DATASHEET System Manager 6.2

6.2.1 Overview

System management includes the following sections:  System Reset  System Power Architecture  System Memory Map  System management registers for Part Number ID, chip reset and on-chip controllers reset, and multi-functional pin control  System Timer (SysTick)  Nested Vectored Interrupt Controller (NVIC)  System Control registers

6.2.2 System Reset

The system reset can be issued by one of the following listed events. For these reset events flags can be read by SYS_RSTSTS register.  Hardware Reset  Power-on Reset (POR)  Low level on the nRESET pin  Watchdog Time-out Reset (WDT)  Low Voltage Reset (LVR)  Brown-out Detector Reset (BOD)  Software Reset  CPU Reset  Write 1 to CPURST (SYS_IPRST0[1])  Whole Chip Reset  Write 1 to SYSRESETREQ (SYS_AIRCR[2])  Write 1 to CHIPRST (SYS_IPRST0[0])

Apr 18, 2017 Page 24 of 74 Rev.1.00 MINI55 SERIES DATASHEET Glitch Filter 36 us Low Voltage Reset Power On Reset Brown Out Reset Reset Pulse Width 3.2ms WDT/WWDT Reset Reset Pulse Width

64 WDT clocks

~50k ohm @5v Reset Pulse Width 2 system clocks nRESET VDD AVDD CHIP_RST Reset SYS_IPRST0[0] SYSRSTREQ Reset AIRCR[2] CPU Reset SYS_IPRST0[1] BODRSTEN(SYS_BODCTL[3]) Figure 6.2-1 System Rese Resources There are a total of 8 reset sources in the NuMicro® family. In general, CPU reset is used to reset Cortex-M0 only; the other reset sources will reset Cortex-M0 and all peripherals. However, there are small differences between each reset source and they are listed in Table 6.2-1. Reset Sources Register POR nRESET WDT LVR BOD CHIP MCU CPU SYS_RSTSTS 0x001 Bit 1 = 1 Bit 2 = 1 0x001 Bit 4 = 1 Bit 0 = 1 Bit 5 = 1 Bit 7 = 1 CHIPRST (SYS_IPRST0[0]) 0x0 - - - - - - - BODEN (SYS_BODCTL[0]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - Reload from CONFIG0 Reload from CONFIG0 BODVL (SYS_BODCTL[2:1]) BODRSTEN (SYS_BODCTL[3]) XTLEN (CLK_PWRCTL[1:0]) 0x0 0x0 0x0 0x0 0x0 0x0 0x0 WDTCKEN (CLK_APBCLK0[0]) 0x1 - 0x1 - - 0x1 - - HCLKSEL (CLK_CLKSEL0[2:0]) 0x8 0x8 0x8 0x8 0x8 0x8 0x8 - WDTSEL 0x3 0x3 - - - - - -

Apr 18, 2017 Page 25 of 74 Rev.1.00 MINI55 SERIES DATASHEET (CLK_CLKSEL1[1:0]) XLTSTB (CLK_STATUS[0]) 0x0 - - - - - - - LIRCSTB (CLK_STATUS[3]) 0x0 HIRCSTB (CLK_STATUS[4]) 0x0 - - - - - - - CLKSFAIL (CLK_STATUS[7]) WDT_CTL 0x0700 0x0700 0x0700 0x0700 0x0700 0x0700 - - BS (FMC_ISPCTL[1]) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - - ISPEN (FMC_ISPCTL[16]) FMC_DFBA Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 Reload from CONFIG1 - - CBS (FMC_ISPSTS[2:1)) Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 Reload from CONFIG0 - - VECMAP  (FMC_ISPSTS[20:9]) Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 Reload base on CONFIG0 - - Other Peripheral Registers Reset Value FMC Registers Reset Value Note: ‘-‘ means that the value of register keeps original setting. Table 6.2-1 Reset Value of Registers nRESET Reset 6.2.2.1 The nRESET reset means to generate a reset signal by pulling low nRESET pin, which is an asynchronous reset input pin and can be used to reset system at any time. When the nRESET voltage is lower than 0.2 V DD and the state keeps longer than 32 us (glitch filter), chip will be reset. The nRESET reset will control the chip in reset state until the nRESET voltage rises above 0.7 VDD and the state keeps longer than 32 us (glitch filter). The PINRF(SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-2 shows the nRESET reset waveform.

Apr 18, 2017 Page 26 of 74 Rev.1.00 MINI55 SERIES DATASHEET nRESET

0.2 VDD

0.7 VDD

Figure 6.2-2 nRESET Reset Waveform Power-on Reset (POR) 6.2.2.2 The Power -on reset (POR) is used to generate a stable system reset signal and fo rces the system to be reset when power -on to avoid unexpected behavior of MCU. When applying the power to MCU, the POR module will detect the rising voltage and generate reset signal to system until the voltage is ready for MCU operation. At POR reset, the PORF(SYS_RSTSTS[0]) will be set to 1 to indicate there is a POR reset event. The PORF(SYS_RSTSTS[0]) bit can be cleared by writing 1 to it. Figure 6.2-3 shows the power-on reset waveform. VDD VPOR Power-on Reset 0.1V Figure 6.2-3 Power-on Reset (POR) Waveform Low Voltage Reset (LVR) 6.2.2.3 Low Voltage Reset detects AV DD during system operation. When the AV DD voltage is lower than VLVR and the state keeps longer than De-glitch time (16*HCLK cycles), chip will be reset. The LVR reset will control the chip in reset state until the AV DD voltage rises above V LVR and the state keeps longer than De -glitch time. The PINRF (SYS_RSTSTS[1]) will be set to 1 if the previous reset source is nRESET reset. Figure 6.2-4 shows the Low Voltage Reset waveform.

Apr 18, 2017 Page 27 of 74 Rev.1.00 MINI55 SERIES DATASHEET AVDD VLVR Low Voltage Reset ( < de-glitch time) ( = de-glitch time) ( = de-glitch time) Figure 6.2-4 Low Voltage Reset (LVR) Waveform Brown-out Detector Reset (BOD Reset) 6.2.2.4 If the Brown-out Detector (BOD) function is enabled by setting the Brown -out Detector Threshold Voltage Selection BODVL[1:0] (SYS_BODCTL[2:1]), BODVL[2] (SYS_BODCTL[7]) and Brown - Out Detector Selection Extension BODVLEXT (SYS_BODCTL[0]). Brown -Out Detector function will detect AVDD during system operation. When the AVDD voltage is lower than VBOD and the state keeps longer than De -glitch time ( Max(20*HCLK cycles, 1*LIRC cycle) ), chip will be reset if BODRSTEN (SYS_BODCTL[3]) is enabled. The BOD reset will control the chip in reset state until the AVDD voltage rises above VBOD and the state keeps longer than De -glitch time. The default value of BODVL[1:0] (SYS_BODCTL[2:1]), BODVL[2] (SYS_BODCTL[7]), BODVLEXT (SYS_BODCTL[0]) and BODRSTEN (SYS_BODCT L[3]) is set by flash controller user configuration register CBOVEXT (CONFIG0 [23]), CBOV[1:0] (CONFIG0 [22:21]), CBOV[2] (CONFIG0 [19]) and CBORST(CONFIG0[20]) respectively. User can determine the initial BOD setting by setting the CONFIG0 register. Figure 6.2-5 shows the Brown-Out Detector waveform.

Apr 18, 2017 Page 28 of 74 Rev.1.00 MINI55 SERIES DATASHEET AVDD VBODL BODOUT BODRSTEN Brown-out Reset (< de-glitch time) (= de-glitch time) (= de-glitch time) Hysteresis VBODH Figure 6.2-5 Brown-out Detector (BOD) Waveform Watchdog Timer Reset (WDT) 6.2.2.5 In most industrial applications, system reliability is very important. To automatically recover the MCU from failure status is one way to improve system reliability. The watchdog timer (WDT) is widely used to check if the system works fine. If the MCU is crashed or out of control, it may cause the watchdog time -out. User may decide to enable system reset during watchdog time -out to recover the system and take action for the system crash/out-of-control after reset. Software can check if the reset is caused by watchdog time -out to indicate the previous reset is a watchdog reset and handle the failure of MCU after watchdog time -out reset by checking WDTRF (SYS_RSTSTS[2]). CPU Reset, CHIP Reset and MCU Reset 6.2.2.6 The CPU Reset means only Cortex ® -M0 core is reset and all other peripherals remain the same status after CPU reset. User can set the CPURST (SYS_IPRST0[1]) to 1 to assert the CPU Reset signal. The CHIP Reset is same with Power -On Reset. The CPU and all peripherals are reset and BS(FMC_ISPCTL[1]) bit is automatically reloaded from CONFIG0 setting. User can set the CHIPRST (SYS_IPRST0[1]) to 1 to assert the CHIP Reset signal. The MCU Reset is similar with CHIP Reset. The difference is that BS (FMC_ ISPCTL[1]) will not be reloaded from CONFIG0 setting and keep its original software setting for booting from APROM or LDROM. User can set the SYSRESETREQ (AIRCR[2]) to 1 to assert the MCU Reset.

Apr 18, 2017 Page 29 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.2.3 Power Modes and Wake-up Sources

There are several wake -up sources in Idle mode and Power -down mode. Table 6.2-2 lists the available clocks for each power mode. Power Mode Normal Mode Idle Mode Power-down Mode Definition CPU is in active state CPU is in sleep state CPU is in sleep state and all clocks stop except LXT and LIRC. SRAM content retended. Entry Condition Chip is in normal mode after system reset released CPU executes WFI instruction. CPU sets sleep mode enable and power down enable and executes WFI instruction. Wake-up Sources N/A All interrupts WDT, I² C, Timer, UART, BOD and GPIO Available Clocks All All except CPU clock LXT and LIRC After Wake-up N/A CPU back to normal mode CPU back to normal mode Table 6.2-2 Power Mode Difference Table Normal Mode CPU Clock ON HXT, HIRC, LXT, LIRC, HCLK, PCLK ON Flash ON Power-down Mode CPU Clock OFF HXT, HIRC, HCLK, PCLK OFF Flash Halt System reset released CPU executes WFI Interrupts occur Idle Mode CPU Clock OFF HXT, HIRC, LXT, LIRC, HCLK, PCLK ON Flash Halt 1. SLEEPDEEP (SCS_SCR[2]) = 1 2. PDEN (CLK_PWRCTL[7]) = 1 and PDWKIF (CLK_PWRCTL[8]) = 1 3. CPU executes WFI Wake-up events occur LXT, LIRC ON Figure 6.2-6 Power Mode State Machine 1. LXT (32768 Hz XTL) ON or OFF depends on SW setting in run mode. 2. LIRC (10 kHz OSC) ON or OFF depends on S/W setting in run mode. 3. If TIMER clock source is selected as LIRC/LXT and LIRC/LXT is on. 4. If WDT clock source is selected as LIRC and LIRC is on.

Apr 18, 2017 Page 30 of 74 Rev.1.00 MINI55 SERIES DATASHEET Normal Mode Idle Mode Power-down Mode HXT (4~20 MHz XTL) ON ON Halt HIRC (12/16 MHz OSC) ON ON Halt LXT (32768 Hz XTL) ON ON ON/OFF1 LIRC (10 kHz OSC) ON ON ON/OFF2 PLL ON ON Halt LDO ON ON ON CPU ON Halt Halt HCLK/PCLK ON ON Halt SRAM retention ON ON ON FLASH ON ON Halt GPIO ON ON Halt TIMER ON ON ON/OFF3 PWM ON ON Halt WDT ON ON ON/OFF4 UART ON ON Halt I2C ON ON Halt SPI ON ON Halt ADC ON ON Halt ACMP ON ON Halt Table 6.2-3 Clocks in Power Modes Wake-up sources in Power-down mode: WDT, I² C, Timer, UART, BOD and GPIO After chip enters power down, the following wake -up sources can wake chip up to normal mode. Table 6.2-4 lists the condition about how to enter Power-down mode again for each peripheral. *User needs to wait this condition before setting PDEN (CLK_PWRCTL[7]) and execute WFI to enter Power-down mode. Wake-up Source Wake-up condition System can enter Power-down mode again condition* BOD Brown-Out Detector Interrupt After software writes 1 to clear SYS_BODCTL[BODIF]. GPIO GPIO Interrupt After software write 1 to clear the Px_INTSRC[n] bit. TIMER Timer Interrupt After software writes 1 to clear TWKF (TIMERx_INTSTS[1]) and TIF (TIMERx_INTSTS[0]). WDT WDT Interrupt After software writes 1 to clear WKF (WDT_CTL[5]) (Write Protect).

Apr 18, 2017 Page 31 of 74 Rev.1.00 MINI55 SERIES DATASHEET UART nCTS wake-up After software writes 1 to clear CTSWKIF (UARTx_INTSTS[16]). I2C Falling edge in the I2C_SDA or I2C_CLK After software writes 1 to clear WKIF ( I2C_STATUS1[0]). Table 6.2-4 Condition of Entering Power-down Mode Again

6.2.4 System Power Architecture

In this chip, the power distribution is divided into three segments.  Analog power from AV DD and AV SS provides the power for analog components operation. AVDD must be equal to VDD to avoid leakage current.  Digital power from V DD and VSS supplies power to the I/O pins and internal regulator which provides a fixed 1.8V power for digital operation.  Built-in a capacitor for internal voltage regulator The output of internal voltage regulator, LDO_CAP, require s an external capacitor which should be located close to the corresponding pin. Analog power (AVDD) should be the same voltage level as the digital power (VDD). Figure 6.2-7 shows the power distribution of the Mini55 series. 2.1~5.5V to 1.8V LDO 10-bit SAR-ADC Brown Out Detector POR18 Analog Comparator FLASH Digital Logic 1.8V 10 kHz LIRC Oscillator AVDD AVSS VDD VSS LDO_CAP IO cell GPIO Pins XT_OUT XT_IN 4~24 MHz or 32.768 kHz crystal oscillator Low Voltage Reset SRAM

48 MHz

Figure 6.2-7 NuMicro® Mini55 Series Power Architecture Diagram

Apr 18, 2017 Page 32 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.2.5 System Memory Mapping

Table 6.2-5 Memory Mapping Table

6.2.6 Memory Organization

Overview 6.2.6.1 The NuMicro® Mini55 series provides 4G-byte addressing space. The addressing space assigned to each on -chip controllers is shown in Table 6.2-6. The detailed register definition, addressing space, and programmin g details will be described in the following sections for each on-chip peripheral. The Mini55 series only supports little-endian data format. Mini55 System Control

4 GB 0xFFFF_FFFF System Control 0xE000_ED00 SCS_BA

| External Interrupt Control 0xE000_E100 SCS_BA 0xE000_F000 System Timer Control 0xE000_E010 SCS_BA 0xE000_EFFF 0xE000_E000 0xE000_E00F 0x6002_0000 0x6001_FFFF 0x6000_0000 0x5FFF_FFFF | AHB peripherals 0x5020_0000 HDIV 0x5001_4000 FMC_BA 0x501F_FFFF FMC 0x5000_C000 FMC_BA 0x5000_0000 GPIO Control 0x5000_4000 GP_BA 0x4FFF_FFFF Interrupt Multiplexer Control 0x5000_0300 INT_BA Clock Control 0x5000_0200 CLK_BA System Global Control 0x5000_0000 SYS_BA 0x4020_0000 0x401F_FFFF

1 GB 0x4000_0000

0x3FFF_FFFF APB peripherals UART1 Control 0x4015_0000 UART1_BA ADC Control 0x400E_0000 ADC_BA ACMP Control 0x400D_0000 CMP_BA UART0 Control 0x4005_0000 UART0_BA 0x2000_0800 PWM Control 0x4004_0000 PWM_BA 0x2000_07FF SPI Control 0x4003_0000 SPI_BA

0.5 GB 0x2000_0000 I2C0 Control 0x4002_0000 I2C0_BA

0x1FFF_FFFF Timer0/Timer1 Control 0x4001_0000 TMR_BA WDT Control 0x4000_4000 WDT_BA 0x0000_4600 0x0000_45FF

0 GB 0x0000_0000

17.5 KB on-chip Flash (Mini55)

2 KB SRAM

Apr 18, 2017 Page 33 of 74 Rev.1.00 MINI55 SERIES DATASHEET System Memory Map 6.2.6.2 The memory locations assigned to each on-chip controllers are shown in Table 6.2-6. Addressing Space Token Modules Flash and SRAM Memory Space 0x0000_0000 – 0x0000_7FFF FLASH_BA Flash Memory Space (32 KB) 0x2000_0000 – 0x2000_07FF SRAM_BA SRAM Memory Space (4 KB) AHB Modules Space (0x5000_0000 – 0x501F_FFFF) 0x5000_0000 – 0x5000_01FF SYS_BA System Global Control Registers 0x5000_0200 – 0x5000_02FF CLK_BA Clock Control Registers 0x5000_0300 – 0x5000_03FF INT_BA Interrupt Multiplexer Control Registers 0x5000_4000 – 0x5000_7FFF GP_BA GPIO (P0~P5) Control Registers 0x5000_C000 – 0x5000_FFFF FMC_BA Flash Memory Control Registers 0x5001_4000 – 0x5001_7FFF HDIV_BA Hardware Divider Control Register APB Modules Space (0x4000_0000 – 0x401F_FFFF) 0x4000_4000 – 0x4000_00FF WDT_BA Watchdog Timer Control Registers 0x4001_0000 – 0x4001_3FFF TMR_BA Timer0/Timer1 Control Registers 0x4002_0000 – 0x4002_3FFF I2C0_BA I2C0 Interface Control Registers 0x4003_0000 – 0x4003_3FFF SPI_BA SPI with Master/slave Function Control Registers 0x4004_0000 – 0x4004_3FFF PWM_BA PWM Control Registers 0x4005_0000 – 0x4005_3FFF UART0_BA UART0 Control Registers 0x400D_0000 – 0x400D_3FFF ACMP_BA Analog Comparator Control Registers 0x400E_0000 – 0x400E_3FFF ADC_BA Analog-Digital-Converter (ADC) Control Registers 0x4015_0000 – 0x4015_3FFF UART1_BA UART1 Control Registers System Control Space (0xE000_E000 – 0xE000_EFFF) 0xE000_E010 – 0xE000_E0FF SCS_BA System Timer Control Registers 0xE000_E100 – 0xE000_ECFF SCS_BA Nested Vectored Interrupt Control Registers 0xE000_ED00 – 0xE000_ED8F SCS_BA System Control Block Registers Table 6.2-6 Address Space Assignments for On-Chip Modules

Apr 18, 2017 Page 34 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.2.7 System Timer (SysTick)

The Cortex® -M0 includes an integrated system timer, SysTick , which provides a simple, 24 -bit clear-on-write, decrementing, wrap -on-zero counter with a flexible control mechanism. The counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter. When system timer is enabled, it will count down from the value in the SysTick Current Value Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value Register (SYST_RVR) on the next clock edge, and then decrement on subsequent clocks. When the counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on reads. The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to zero before enabling the featu re. This ensures the timer to count from the SYST_RVR value rather than an arbitrary value when it is enabled. If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is reloaded with this value. This mechanism can be used to disable the feature independently from the timer enable bit. For more detailed information, please refer to the “ARM ® Cortex® -M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”.

Apr 18, 2017 Page 35 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.2.8 Nested Vectored Interrupt Controller (NVIC)

Overview 6.2.8.1 The Cortex® -M0 CPU provides an interrupt controller as an integral part of the exception mode, named as “Nested Vectored Interrupt Controller (NVIC)” , which is closely coupled to the processor core and provides following features. Features 6.2.8.2  Nested and Vectored interrupt support  Automatic processor state saving and restoration  Dynamic priority change  Reduced and deterministic interrupt latency The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority. All of the interrupts and most of the system exceptions can be configured to different priority levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the current running one’s priority. If the priority of the new interrupt is higher than the current one, the new interrupt handler will override the current handler. When an interrupt is accepted, the starting address of t he Interrupt Service Routine (ISR) is fetched from a vector table in memory. There is no need to determine which interrupt is accepted and branch to the starting address of the correlated ISR by software. While the starting address is fetched, NVIC will al so automatically save processor state including the registers “PC, PSR, LR, R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers from stack and resume the normal execution. Thus it will take less and deterministic time to process the interrupt request. The NVIC supports “Tail Chaining” which handles back -to-back interrupts efficiently without the overhead of states saving and restoration and therefore reduces delay time in switching to pending ISR at the end of cur rent ISR. The NVIC also supports “Late Arrival” which improves the efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current ISR starts to execute (at the stage of state saving and starting address fetching), the NVI C will give priority to the higher one without delay penalty. Thus it advances the real-time capability. For more detailed information, please refer to the “ARM ® Cortex® -M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”. Exception Model and System Interrupt Map 6.2.8.3 Table 6.2-7 lists the exception model supported by NuMicro® Mini55 series. Software can set four levels of priority on some o f these exceptions as well as on all interrupts. The highest user - configurable priority is denoted as 0 and the lowest priority is denoted as 3. The default priority of all the user -configurable interrupts is 0. Note that the priority 0 is treated as the f ourth priority on the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.

Apr 18, 2017 Page 36 of 74 Rev.1.00 MINI55 SERIES DATASHEET Exception Name Vector Number Priority Reset 1 -3 NMI 2 -2 Hard Fault 3 -1 Reserved 4 ~ 10 Reserved SVCall 11 Configurable Reserved 12 ~ 13 Reserved PendSV 14 Configurable SysTick 15 Configurable Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable Table 6.2-7 Exception Model Exception Number Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module Interrupt Description Power-down Wake-up 1 ~ 15 - - - System exceptions - 16 0 BODOUT Brown-out Brown-out low voltage detected interrupt Yes 17 1 WDT_INT WDT Watchdog Timer interrupt Yes 18 2 EINT0 GPIO External signal interrupt from P3.2 pin Yes 19 3 EINT1 GPIO External signal interrupt from P5.2 pin Yes 20 4 GP0/1_INT GPIO External signal interrupt from GPIO group P0~P1 Yes 21 5 GP2/3/4_INT GPIO External signal interrupt from GPIO group P2~P4 except P3.2 Yes 22 6 PWM_INT PWM PWM interrupt No 23 7 BRAKE_INT PWM PWM Brake interrupt No 24 8 TMR0_INT TMR0 Timer 0 interrupt Yes 25 9 TMR1_INT TMR1 Timer 1 interrupt Yes 26 ~ 27 10 ~ 11 - - - 28 12 UART0_INT UART0 UART0 interrupt Yes 29 13 UART1_INT UART1 UART1 interrupt Yes 30 14 SPI_INT SPI SPI interrupt No 31 15 - - - 32 16 GP5_INT GPIO External signal interrupt from GPIO group P5 except P5.2 Yes 33 17 HIRC_TRIM_IN T HIRC HIRC trim interrupt No 34 18 I2C0_INT I2C0 I C0 interrupt Yes

Apr 18, 2017 Page 37 of 74 Rev.1.00 MINI55 SERIES DATASHEET Exception Number Interrupt Number (Bit In Interrupt Registers) Interrupt Name Source Module Interrupt Description Power-down Wake-up 35 ~ 40 19 ~ 24 - - - 41 25 ACMP_INT ACMP Analog Comparator 0 or Comparator 1 interrupt Yes 42 ~ 43 26 ~ 27 - - - 44 28 PWRWU_INT CLKC Clock controller interrupt for chip wake- up from Power-down state Yes 45 29 ADC_INT ADC ADC interrupt No 46 ~ 47 30 ~ 31 - - - Table 6.2-8 System Interrupt Map Vector Table Vector Table 6.2.8.4 When an interrupt is accepted, the processor will automatically fetch the starting address of the interrupt service routine (ISR) from a vector table in memory. For ARMv6 -M, the vector table based address is fixed at 0x00000000. The vector table contains the initialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. The vector number on previous page defines the order of entries in the vector table associated with the exception handler entry as illustrated in previous section. Vector Table Word Offset (Bytes) Description 0x00 Initial Stack Pointer Value Exception Number * 0x04 Exception Entry Pointer using that Exception Number Table 6.2-9 Vector Table Format Operation Description 6.2.8.5 NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set - Enable or Interrupt Clear-Enable register bit-field. The registers use a write -1-to-enable and write- 1-to-clear policy, both registers reading back the current enabled state of the corresponding interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become Pending; however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it remains in its Active state until cleared by reset or an exception return. Clearing the enable bit prevents new activations of the associated interrupt. NVIC interrupts can be pended/un -pended using a complementary pair of registers to those used to enable/disable the interrupts, named the Set -Pending Register and Clear -Pending Register respectively. The registers use a write -1-to-enable and write -1-to-clear policy, both registers reading back the current pended state of the corresponding interrupts. The Clear -Pending Register has no effect on the execution status of an Active interrupt. NVIC interrupts are prioritized by updating an 8 -bit field within a 32 -bit register (each register supporting four interrupts). The general registers associated with the NVIC are all accessible from a block of memory in the System Control Space and will be described in next section.

Apr 18, 2017 Page 38 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.2.9 System Control Registers (SCB)

The Cortex® -M0 status and operating mode control are managed System Control Registers. Including CPUID, Cortex® -M0 interrupt priority and Cortex® -M0 power management can be controlled through these system control registers. For more detailed information, please refer to the “ARM ® Cortex® -M0 Technical Reference Manual” and “ARM® v6-M Architecture Reference Manual”.

Apr 18, 2017 Page 39 of 74 Rev.1.00 MINI55 SERIES DATASHEET Clock Controller 6.3

6.3.1 Overview

The clock controller generates clocks for the whole chip, including system clocks and all peripheral clocks. The clock controller also implements the power control function with the individually clock ON/OFF control, clock source selection and clock divider. The chip enters Power-down mode when Cortex ® -M0 core executes the WFI instruction only if the PDEN (CLK_PWRCTL[7]) bit is set to 1. After that, chip enters Power -down mode and waits for wake -up interrupt source triggered to exit Power -down mode. In Power -down mode, the clock control ler turns off the 4~24 MHz external high speed crystal (HXT) and 48 MHz internal high speed RC oscillator (HIRC) to reduce the overall system power consumption. Figure 6.3-1 and Figure 6.3-2 show the clock generator and the overview of the clock source control. The clock generator consists of 3 sources as listed below:  4~24 MHz external high speed crystal oscillator (HXT) or 32.768 kHz (LXT) external low speed crystal oscillator  48 MHz internal high speed RC oscillator (HIRC)  10 kHz internal low speed RC oscillator (LIRC) XT1_OUT 4~24 MHz HXT or 32.768 kHz LXT XTLEN (CLK_PWRCTL[1:0]) XT1_IN HIRCEN (CLK_PWRCTL[2]) 10 kHz LIRC LIRCEN (CLK_PWRCTL[3]) HXT or LXT LIRC Legend: HXT = 4~24 MHz external high speed crystal oscillator LXT = 32.768 kHz external low speed crystal oscillator HIRC = 48 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator HIRC Figure 6.3-1 Clock Generator Block Diagram

Apr 18, 2017 Page 40 of 74 Rev.1.00 MINI55 SERIES DATASHEET 4~24 MHz or 32.768k Hz 111 011 010 001 4~24 MHz or 32.768kHz Reserved 4~24 MHz or 32.768kHz HCLK HIRC 000 CLKSEL0[5:3] SysTick ADC UART 1 ISP WDT PWMCH23 TMR 1 TMR 0 CPU FMC 10 kHz 011 010 001 000 HCLK 10 kHz 4~24 MHz or 32.768kHz 111 011 010 001 Reserved Reserved 4~24 MHz or 32.768kHz 10 kHz HIRC 000 CLKSEL0[2:0] SYST_CSR[2] CPUCLK 1/(HCLKDIV+1) PCLK CPUCLK HCLK Reserved 4~24 MHz or 32.768kHz HCLK CLKSEL1[3:2] External trigger CLKSEL1[14:12] CLKSEL1[10:8] HIRC 10 kHz 1/(ADC_DIV+1) CLKSEL1[1:0] HCLK 1/2048 1/(UART1DIV+1) 10, 11 Reserved 4~24 MHz or 32.768kHz HIRC CLKSEL1[27:26] HIRC HIRC 111 SPI HCLK 4~24 MHz or 32.768kHz HIRC Reserved CLKSEL2[3:2] FREQDIV BOD10 kHz I2C 0 ACMP PWMCH01 PWMCH45 04~24 MHz or 32.768kHz HCLK CLKSEL1[4] 004~24 MHz or 32.768kHz Note: Before clock switching, both the pre- selected and newly selected clock sources must be turned on and stable. UART 01/(UART0DIV+1) CLKSEL1[25:24] HCLK HCLK HCLK Figure 6.3-2 Clock Generator Global View Diagram

Apr 18, 2017 Page 41 of 74 Rev.1.00 MINI55 SERIES DATASHEET

6.3.2 Auto-trim

This chip supports auto -trim function: the HIRC trim ( 48 MHz internal RC oscillator), according to the accurate LXT (32.768 kHz crystal oscillator), automatically gets accurate HIRC output frequency, 1 % deviation within all temperat ure ranges. For instance, the system needs an accurate 48 MHz clock. In such case, if users do not want to use 48 MHz HXT as the system clock source, they need to solder 32.768 kHz crystal in system, and set FREQSEL (SYS_IRCTCTL[0] trim frequency selection ) to “1”, and the auto -trim function will be enabled. Interrupt status bit FREQLOCK (SYS_IRCTISTS[0] HIRC frequency lock status) high indicates the HIRC output frequency is accurate within 1% deviation. To get better results, it is recommended to set both LOOPSEL (SYS_IRCTCTL[5:4] trim calculation loop) and RETRYCNT (SYS_IRCTCTL[7:6] trim value update limitation count) to “11”.

6.3.3 System Clock and SysTick Clock

The system clock has 4 clock sources which were generated from clock generator block. The clock source switch depends on the register HCLKSEL (CLK_CLKSEL0[2:0]). The block diagram is shown in Figure 6.3-3. 111 011 010 001 Reserved Reserved 4~24 MHz HXT or 32.768 kHz LXT 10 kHz LIRC HCLKSEL (CLK_CLKSEL0[2:0]) HIRC 000 1/(HCLK_N+1) HCLKDIV (CLK_CLKDIV[3:0]) CPU in Power Down Mode CPU AHB APB CPUCLK HCLK PCLK Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 48 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Note: Before clock switching, both the pre- selected and newly selected clock sources must be turned on and stable. Figure 6.3-3 System Clock Block Diagram The source of PCLK is equal to HCLK in system clock architecture. The clock source of SysTick in Cortex® -M0 core can use CPU clock or external clock CLKSRC(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The clock source switch depends on the setting of the register STCLKSEL (CLK_CLKSEL0[5:3]). The block diagram is shown in Figure 6.3-4.

Apr 18, 2017 Page 42 of 74 Rev.1.00 MINI55 SERIES DATASHEET 111 010 HCLK 4~24 MHz HXT or 32.768 kHz LXT STCLKSEL (CLK_CLKSEL0[5:3]) STCLK HIRC 001 4~24 MHz HXT or 32.768 kHz LXT 000 Reserved Legend: HXT = 4~24 MHz external high speed crystal oscillator HIRC = 48 MHz internal high speed RC oscillator LIRC = 10 kHz internal low speed RC oscillator Note: Before clock switching, both the pre- selected and newly selected clock sources must be turned on and stable. SYST_CSR[2] CPUCLK Figure 6.3-4 SysTick Clock Control Block Diagram

6.3.4 Peripherals Clock Source Selection

The peripheral clock has different clock source switch settings depending on different peripherals. Please refer to the CLK_CLKSEL1 and CLK_APBCLK register description in NuMicro® Mini55 Series Technical Reference Manual section 6.3.8. Please to note that, while switching clock source from one to another, user must wait until both clock sources are running stabled. Timer1 Timer0TMR0CKEN (CLK_APBCLK[2]) TMR1CKEN (CLK_APBCLK[3]) CLKOCKEN (CLK_APBCLK[6]) SPIEN (CLK_APBCLK[12]) UART0CKEN (CLK_APBCLK[16]) PWMCH01CKEN (CLK_APBCLK[20]) PWMCH23CKEN (CLK_APBCLK[21]) PWMCH45CKEN (CLK_APBCLK[22]) ACMPCKEN (CLK_APBCLK[30]) ADCCKEN (CLK_APBCLK[28]) Frequency Divider SPI UART0 PWM01 PWM23 PWM45 ACMP ADC WDTCKEN (CLK_APBCLK[0]) PCLK Watch Dog Timer I2C0I2C0CKEN (CLK_APBCLK[8]) UART1CKEN (CLK_APBCLK[17]) UART1 Figure 6.3-5 Peripherals Bus Clock Source Selection for PCLK

Apr 18, 2017 Page 43 of 74 Rev.1.00 MINI55 SERIES DATASHEET Peripheral Clok Selectable Ext. CLK (HXT Or LXT) HIRC LIRC HCLK WDT Yes Yes No Yes Yes Timer0 Yes Yes Yes Yes Yes Timer1 Yes Yes Yes Yes Yes I2C0 No - - - - SPI Yes Yes No No Yes UART0 Yes Yes Yes No No UART1 Yes Yes Yes No No PWM No - - - - ADC Yes Yes Yes No Yes ACMP No - - - - Table 6.3-1 Peripheral Clock Source Selection Table Note: For the peripherals those peripheral clock are not selectable, its clock source is fixed to PCLK.

6.3.5 Power-down Mode Clock

When chip enters Power-down mode, system clocks, some clock sources, and some peripheral clocks will be disabled. Some clock sources and peripheral clocks are still active in Power-down mode. The clocks still kept active are listed below:  Clock Generator  10 kHz internal low speed oscillator (LIRC) clock  32.768 kHz external low speed crystal oscillator (LXT) clock (If PDLXT = 1 and XTLEN[1:0] = 10)  Peripherals Clock (When 10 kHz low speed oscillator is adopted as clock source)  Watchdog Clock  Timer 0/1 Clock

6.3.6 Frequency Divider Output

This device is equipped with a power-of-2 frequency divider which is composed of 16 chained divide-by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is reflected to the CLKO pin. Therefore there are 16 options of power-of-2 divided clocks with the frequency from Fin/21 to Fin/216 where Fin is input clock frequency to the clock divider. The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock divider output frequency and N is the 4-bit value in FREQSEL (CLK_CLKOCTL[3:0]).

Apr 18, 2017 Page 45 of 74 Rev.1.00 MINI55 SERIES DATASHEET Flash Memory Controller (FMC) 6.4

6.4.1 Overview

The NuMicro® Mini55 series is equipped with 17.5 Kbytes on-chip embedded flash for application and Data Flash to store some application dependent data. A User Configuration block provides for system initialization. A 2 Kbytes loader ROM (LDROM) is used for In-System-Programming (ISP) function. This chip also supports In-Application-Programming (IAP) function, user switches the code executing without the chip reset after the embedded flash updated.

6.4.2 Features

 Supports 17.5 Kbytes application ROM (APROM).  Supports 2 Kbytes loader ROM (LDROM).  Supports configurable Data Flash size to share with APROM.  Supports User Configuration block to control system initialization.  Supports 512 bytes page erase for all embedded flash.  Supports In-System-Programming (ISP) / In-Application-Programming (IAP) to update embedded flash memory.

Apr 18, 2017 Page 46 of 74 Rev.1.00 MINI55 SERIES DATASHEET General Purpose I/O (GPIO) 6.5

6.5.1 Overview

The NuMicro® Mini55 series has up to 33 General Purpose I/O pins to be shared with other function pins depending on the chip configuration. These 33 pins are arranged in 6 ports named as P0, P1, P2, P3, P4 and P5. Each of the 33 pins is independent and has the corresponding register bits to control the pin mode function and data. The I/O type of each pin can be configured by software individually as Input, Push-pull output, Open-drain output, or Quasi-bidirectional mode. After the chip is reset, the I/O mode of all pins is stay in input mode and each port data register Px_DOUT[n] resets to 1. For Quasi-bidirectional mode, each I/O pin is equipped with a very weak individual pull-up resistor about 110 k ~ 300 k for VDD is from 5.0 V to 2.1 V.

6.5.2 Features

 Four I/O modes:  Quasi-bidirectional mode  Push-pull output  Open-drain output  Input-only with high impendence  Quasi-bidirectional TTL/Schmitt trigger input mode selected by SYS_Px_MFP[23:16]  I/O pin configured as interrupt source with edge/level setting  I/O pin internal pull-up resistor enabled only in Quasi-bidirectional I/O mode  Enabling the pin interrupt function will also enable the pin wake-up function  High driver and high sink I/O mode support  Configurable default I/O mode of all pins after reset by CIOINI (Config0[10]) setting  CIOINI = 0, all GPIO pins in Quasi-bidirectional mode after chip reset  CIOINI = 1, all GPIO pins in Input tri-state mode after chip reset

Apr 18, 2017 Page 47 of 74 Rev.1.00 MINI55 SERIES DATASHEET Timer Controller (TMR) 6.6

6.6.1 Overview

The Timer Controller includes two 32-bit timers, TMR0 and TMR1, allowing user to easily implement a timer control for applications. The timer can perform functions, such as frequency measurement, delay timing, clock generation, event counting by external input pins, and interval measurement by external capture pins.

6.6.2 Features

 Two sets of 32-bit timer with 24-bit up counter and one 8-bit prescale counter  Independent clock source for each timer  Provides one-shot, periodic, toggle-output and continuous counting operation modes  24-bit up counter value is readable through CNT (TIMRTx_CNT[23:0])  Supports event counting function  24-bit capture value is readable through CAPDAT (TIMERx_CAP[23:0])  Supports external capture pin event for interval measurement  Supports external capture pin event to reset 24-bit up counter  Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated  Supports internal capture triggered while internal ACMP output signal transition

Apr 18, 2017 Page 48 of 74 Rev.1.00 MINI55 SERIES DATASHEET Enhanced PWM Generator 6.7

6.7.1 Overview

The NuMicro® Mini55 series has built in one PWM unit (PWM0) which is specially designed for motor driving control applications. The PWM0 supports six PWM generators which can be configured as six independent PWM outputs, PWM0_CH0~PWM0_CH5, or as three complementary PWM pairs, (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5) with three programmable dead-time generators. Every complementary PWM pairs share one 8-bit prescaler. There are six clock dividers providing five divided frequencies (1, 1/2, 1/4, 1/8, 1/16) for each channel. Each PWM output has independent 16-bit counter for PWM period control, and 16-bit comparators for PWM duty control. The six PWM generators provide twelve independent PWM interrupt flags which are set by hardware when the corresponding PWM period counter comparison matched period and duty. Each PWM interrupt source with its corresponding enable bit can request PWM interrupt. The PWM generators can be configured as One-shot mode to produce only one PWM cycle signal or Auto-reload mode to output PWM waveform continuously. To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and 16-bit comparator are implemented with double buffer. When user writes data to counter/comparator buffer registers, the updated value will be loaded into the 16 -bit down counter/ comparator at the end of current period. The double buffering feature avoids glitch at PWM outputs. Besides PWM, Motor controlling also need Timer, ACMP and ADC to work together. In order to control motor more precisely, we provide some registers that not only configure PWM but also Timer, ADC and ACMP, by doing so, it can save more CPU time and control motor with ease especially in BLDC.

6.7.2 Features

The PWM0 supports the following features:  Six independent 16-bit PWM duty control units with maximum six port pins:  Six independent PWM outputs – PWM0_CH0, PWM0_CH1, PWM0_CH2, PWM0_CH3, PWM0_CH4, and PWM0_CH5  Three complementary PWM pairs, with each pin in a pair mutually complement to each other and capable of programmable dead-time insertion – (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)  Three synchronous PWM pairs, with each pin in a pair in-phase – (PWM0_CH0, PWM0_CH1), (PWM0_CH2, PWM0_CH3) and (PWM0_CH4, PWM0_CH5)  Group control bit – PWM0_CH2 and PWM0_CH4 are synchronized with PWM0_CH0, PWM0_CH3 and PWM0_CH5 are synchronized with PWM0_CH1  One-shot (only support edge-aligned type) or Auto-reload mode PWM  Up to 16-bit resolution  Supports edge-aligned and center-aligned mode  Supports asymmetric PWM generating in center-aligned mode  Supports center loading in center-aligned mode  Programmable dead-time insertion between complementary paired PWMs

Apr 18, 2017 Page 49 of 74 Rev.1.00 MINI55 SERIES DATASHEET  Each pin of PWM0_CH0 to PWM0_CH5 has independent polarity setting control  Hardware fault brake protections  Supports software trigger  Two Interrupt source types:  Synchronously requested at PWM frequency when down counter comparison matched (edge- and center-aligned type) or underflow (edge- aligned type)  Requested when external fault brake asserted  BKP0: EINT0 or CPO1  BKP1: EINT1 or CPO0  The PWM signals before polarity control stage are defined in the view of positive logic. The PWM ports is active high or active low are controlled by polarity control register  Supports mask aligned function  Supports independently rising CMP matching, PERIOD matching, falling CMP matching (in Center-aligned type), period matching to trigger ADC conversion  Timer comparing matching event trigger PWM to do phase change in BLDC application  Supports ACMP output event trigger PWM to force PWM output at most one period low, this feature is usually for step motor control  Provides interrupt accumulation function

Apr 18, 2017 Page 50 of 74 Rev.1.00 MINI55 SERIES DATASHEET Figure 6.7-1 Application Circuit Diagram ADC PWM0 UART Timer UART UART Interface 3-Phase Inverter (IPM, MOSFET, IGBT) Isolation circuit DC Bus + DC Bus - BLDC S N +5V AIN[7] +5V CH0 CH1 CH2 CH3 CH4 CH5 AIN[6] nINT0 Push Button +5V CPO0 +VDC Bus MINI58 Trapezoidal Commutation System Architecture Hyper Terminal AIN[0] AIN[1] AIN[2] AIN[3] +VDC Bus Option 1 Option 2 Sensorless circuit

Apr 18, 2017 Page 51 of 74 Rev.1.00 MINI55 SERIES DATASHEET Watchdog Timer (WDT) 6.8

6.8.1 Overview

The Watchdog Timer is used to perform a system reset when system runs into an unknown state. This prevents system from hanging for an infinite period of time. Besides, the Watchdog Timer supports the function to wake-up system from Idle/Power-down mode.

6.8.2 Features

 18-bit free running up counter for WDT time-out interval  Selectable time-out interval (24 ~ 218) WDT_CLK cycles and the time-out interval is 1.6 ms ~ 26.214s if WDT_CLK = 10 kHz  System kept in reset state for a period of (1 / WDT_CLK) * 63  Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT

Apr 18, 2017 Page 52 of 74 Rev.1.00 MINI55 SERIES DATASHEET UART Controller (UART) 6.9

6.9.1 Overview

The NuMicro® Mini55 series provides two channels of Universal Asynchronous Receiver/Transmitters (UART). The UART0 performs supports flow control function. The UART0 performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to- serial conversion on data transmitted from the CPU. The UART0 controller also supports IrDA SIR Function, and RS-485 function mode. The UART0 channel supports six types of interrupts. The UART1 channel supports five types of interrupts. The UART1 only performs a serial-to- parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART0 has 16 bytes Receiver/Transmitter FIFO. The UART1 has 4 bytes Receiver/Transmitter FIFO.

6.9.2 Features

 Full duplex, asynchronous communications  Separates receive/transmit 16/16 bytes entry FIFO for data payloads (Only Available in UART0)  Separates receive/transmit 4/4 byte buffer for data payloads (Only Available in UART1)  Supports hardware auto flow control/flow control function (CTS, RTS) and programmable RTS flow control trigger level (Only Available in UART0)  Programmable receiver buffer trigger level  Supports programmable baud-rate generator for each channel individually  Supports CTS wake-up function (Only Available in UART0)  Supports 8-bit receiver buffer time-out detection function  Programmable transmitting data delay time between the last stop and the next start bit by setting UART_TOUT[15:8] register  Supports break error, frame error, parity error and receive/transmit buffer overflow detection function  Fully programmable serial-interface characteristics  Programmable number of data bit, 5, 6, 7, 8 character  Programmable parity bit, even, odd, no parity or stick parity bit generation and detection  Programmable stop bit, 1, 1.5, or 2 stop bit generation  Supports IrDA SIR function mode (Only Available in UART0)  Supports 3/16-bit duration for normal mode  Supports RS-485 function mode (Only Available in UART0)  Supports RS-485 9-bit mode  Supports hardware or software enable to program RTS pin to control RS-485 transmission direction directly

Apr 18, 2017 Page 53 of 74 Rev.1.00 MINI55 SERIES DATASHEET I2C Serial Interface Controller (I2C) 6.10

6.10.1 Overview

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method for data exchange between devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously. There are two sets of I2C controller and only I2C0 supports Power-down wake-up function.

6.10.2 Features

The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. The main features of the bus include:  Master/Slave mode  Bi-directional data transfer between masters and slaves  Multi-master bus  Arbitration between simultaneously transmitting masters without corruption of serial data on the bus  Serial clock synchronization allowing devices with different bit rates to communicate via one serial bus  Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer  Built-in 14-bit time-out counter that requests the I2C interrupt if the I2C bus hangs up and timer-out counter overflows  Programmable clocks allowing for versatile rate control  Supports 7-bit addressing mode  Supports multiple address recognition (four slave address registers with mask option)  Supports Power-down wake-up function  Supports two-level buffer function

Apr 18, 2017 Page 54 of 74 Rev.1.00 MINI55 SERIES DATASHEET Serial Peripheral Interface (SPI) 6.11

6.11.1 Overview

The Serial Peripheral Interface (SPI) applies to synchronous serial data communication and allows full duplex transfer. Devices communicate in Master/Slave mode with 4-wire bi-direction interface. The SPI controller performing a serial-to-parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral device. SPI controller can be configured as a master or a slave device.

6.11.2 Features

 Supports Master or Slave mode operation  Configurable transfer bit length  Provides four 32-bit FIFO buffers  Supports MSB first or LSB first transfer  Supports byte reorder function  Supports byte or word suspend mode  Supports Slave 3-wire mode

Apr 18, 2017 Page 55 of 74 Rev.1.00 MINI55 SERIES DATASHEET Analog-to-Digital Converter (ADC) 6.12

6.12.1 Overview

The Mini55 series contains one 10-bit successive approximation analog-to-digital converters (SAR A/D converter) with 12 input channels. The A/D converters can be started by software, external pin (STADC/P3.2) or PWM trigger.

6.12.2 Features

 Analog input voltage range: 0 ~ Analog Supply Voltage from AVDD  10-bit resolution and 8-bit accuracy is guaranteed  Up to 12 single-end analog input channels  Maximum ADC clock frequency is 8 MHz, and 16 ADC clocks per sample  Two operating modes  Single mode: A/D conversion is performed one time on a specified channel  PWM sequence mode: When PWM trigger, two of three ADC channels from 0 to 2 will automatically convert analog data in the sequence of channel [0,1] or channel[1,2] or channel[0,2] defined by MODESEL (ADC_SEQCTL[3:2])  An A/D conversion can be started by:  Software write 1 to SWTRG bit  External pin STADC  PWM trigger with optional start delay period  Each Conversion result is held in data register with valid and overrun indicators  Conversion results can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting  Channel 0 supports 2 input sources: External analog voltage and ADC input internal fixed band-gap voltage  Channel 7 supports 2 input sources: internal fixed band-gap voltage and ADC input

Apr 18, 2017 Page 56 of 74 Rev.1.00 MINI55 SERIES DATASHEET Analog Comparator (ACMP) 6.13

6.13.1 Overview

The NuMicro® Mini55 series contains two comparators which can be used in a number of different configurations. The comparator output is logic 1 when positive input is greater than negative input, otherwise the output is 0. Each comparator can be configured to generate interrupt when the comparator output value changes.

6.13.2 Features

 Analog input voltage range: 0 ~ AVDD  Supports Hysteresis function  Optional internal reference voltage source for each comparator negative input  ACMP0 supports:  Four positive sources  Three negative sources  P1.4  Internal Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG)  ACMP1 supports:  Four positive sources  Three negative sources  P3.0  Internal Comparator Reference Voltage (CRV)  Internal band-gap voltage (VBG)

Apr 18, 2017 Page 57 of 74 Rev.1.00 MINI55 SERIES DATASHEET Hardware Divider (HDIV) 6.14

6.14.1 Overview

The hardware divider (HDIV) is useful to the high performance application. The hardware divider is a signed, integer divider with both quotient and remainder outputs.

6.14.2 Features

 Signed (two’s complement) integer calculation  32-bit dividend with 16-bit divisor calculation capacity  32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32- bit)  Divided by zero warning flag  6 HCLK clocks taken for one cycle calculation  Write divisor to trigger calculation  Waiting for calculation ready automatically when reading quotient and remainder

Apr 18, 2017 Page 58 of 74 Rev.1.00 MINI55 SERIES DATASHEET

7 APPLICATION CIRCUIT

4~24 MHz or 32.768 kHz crystal 0.1uF FB FB 20p 20p DVCC 10uF/25V 10K Power Crystal Reset Circuit nRESET XT1_OUT LDO_CAP Mini55LDE LQFP48 VDD VSS nRESET ICE_DAT ICE_CLK SWD Interface 1uF VDD VSS I2C Device CLK DIOI2Cx_SDA I2Cx_SCL 4.7K VDD VSS SPI Device CS CLK MISO SPI_SS MOSI SPI_CLK SPI_MISO SPI_MOSI LDO RS232 Transceiver ROUT TIN RIN TOUT PC COM Port XT1_IN 0.1uF DVCC 4.7K DVCC DVCC Note 1: For the SPI device, the Mini55 chip supply voltage must be equal to SPI device working voltage. For example, when the SPI Flash working voltage is 3.3 V, the Mini58 chip supply voltage must also be 3.3V. UART [1] UARTx_RXD UARTx_TXD Note 2: x denotes 0 or 1. [2] [2]

Apr 18, 2017 Page 59 of 74 Rev.1.00 MINI55 SERIES DATASHEET

8 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings 8.1 Symbol Parameter Min Max Unit VDD VSS DC Power Supply -0.3 +7.0 V VIN Input Voltage VSS -0.3 VDD +0.3 V 1/tCLCL Oscillator Frequency 4 24 MHz TA Operating Temperature -40 +105 ℃ TST Storage Temperature -55 +150 ℃ IDD Maximum Current into VDD - 120 mA ISS Maximum Current out of VSS - 120 mA IIO Maximum Current sunk by an I/O pin - 35 mA Maximum Current sourced by an I/O pin - 35 mA Maximum Current sunk by total I/O pins - 100 mA Maximum Current sourced by total I/O pins - 100 mA Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the life and reliability of the device.

Apr 18, 2017 Page 60 of 74 Rev.1.00 MINI55 SERIES DATASHEET (VDD - VSS = 2.1 ~ 5.5 V, TA = 25C) Symbol Parameter Min Typ Max Unit Test Conditions VDD Operation voltage 2.1 - 5.5 V VDD = 2.1V ~ 5.5V up to 48 MHz VSS / AVSS Power Ground -0.3 - - V VLDO LDO Output Voltage 1.62 1.8 1.98 V VDD ≥ 2.1 V VDD-AVDD Allowed Voltage Difference for VDD and AVDD -0.3 0 0.3 V - IDD1 Operating Current Normal Run Mode HCLK = 48 MHz while(1){} Executed from Flash - 16.8 - mA VDD HXT HIRC PLL All Didital Modules 5.5V X V X V IDD2 - 11.5 - mA 5.5V X V X X IDD3 - 16.1 - mA 3.3V X V X V IDD4 - 11.1 - mA 3.3V X V X X IDD5 Operating Current Normal Run Mode HCLK = 44.2368 MHz while(1){} Executed from Flash - 15.7 - mA VDD HXT HIRC PLL All Didital Modules 5.5V X V X V IDD6 - 10.8 - mA 5.5V X V X X IDD7 - 15.1 - mA 3.3V X V X V IDD8 - 10.4 - mA 3.3V X V X X IDD9 Operating Current Normal Run Mode HCLK = 24 MHz while(1){} Executed from Flash - 8.0 - mA VDD HXT HIRC PLL All Didital Modules 5.5V 24 MHz X X V IDD10 - 6.5 - mA 5.5V 24 MHz X X X IDD11 - 8.0 - mA 3.3V 24 MHz X X V IDD12 - 6.5 - mA 3.3V 24 MHz X X X IDD13 Operating Current Normal Run Mode HCLK = 24 MHz while(1){} Executed from Flash - 10.0 - mA VDD HXT HIRC PLL All Didital Modules 5.5V X V X V IDD14 - 7.1 - mA 5.5V X V X X IDD15 - 9.7 - mA 3.3V X V X V

Apr 18, 2017 Page 61 of 74 Rev.1.00 MINI55 SERIES DATASHEET IDD16 - 6.9 - mA 3.3V X V X X IDD17 Operating Current Normal Run Mode HCLK = 22.1184 MHz while(1){} Executed from Flash - 9.3 - mA VDD HXT HIRC PLL All Digital Modules 5.5V X V X V IDD18 - 6.7 - mA 5.5V X V X X IDD19 - 9.0 - mA 3.3V X V X V IDD20 - 6.5 - mA 3.3V X V X X IDD21 Operating Current Normal Run Mode HCLK = 12MHz while(1){} Executed from Flash - 4.5 - mA VDD HXT HIRC PLL All Digital Modules 5.5V 12 MHz X X V IDD22 - 3.5 - mA 5.5V 12 MHz X X X IDD23 - 4.5 - mA 3.3V 12 MHz X X V IDD24 - 3.5 - mA 3.3V 12 MHz X X X IDD25 Operating Current Normal Run Mode HCLK = 4 MHz while(1){} Executed from Flash - 2.0 - mA VDD HXT HIRC PLL All Digital Modules 5.5V 4 MHz X X V IDD26 - 1.6 - mA 5.5V 4 MHz X X X IDD27 - 2.0 - mA 3.3V 4 MHz X X V IDD28 - 1.6 - mA 3.3V 4 MHz X X X IDD29 Operating Current Normal Run Mode HCLK = 10 kHz while(1){} Executed from Flash - 100 - μA VDD HXT LIRC PLL All Digital Modules 5.5V X V X V[4] IDD30 - 100 - μA 5.5V X V X X IDD31 - 90 - μA 3.3V X V X V[4] IDD32 - 90 - μA 3.3V X V X X IIDLE1 Operating Current Idle Mode HCLK = 48 MHz - 10.0 - mA VDD HXT HIRC PLL All Digital Modules 5.5V X V X V IIDLE2 - 4.6 - mA 5.5V X V X X IIDLE3 - 9.6 - mA 3.3V X V X V IIDLE4 - 4.5 - mA 3.3V X V X X IIDLE5 Operating Current - 9.3 - mA VDD HXT HIRC PLL All Digital Modules

Apr 18, 2017 Page 62 of 74 Rev.1.00 MINI55 SERIES DATASHEET Idle Mode HCLK = 44.2368 MHz 5.5V X V X V IIDLE6 - 4.3 - mA 5.5V X V X X IIDLE7 - 9.0 - mA 3.3V X V X V IIDLE8 - 4.2 - mA 3.3V X V X X IIDLE9 Operating Current Idle Mode HCLK = 24MHz - 4.0 - mA VDD HXT HIRC PLL All Digital Modules 5.5V 24 MHz X X V IIDLE10 - 2.2 - mA 5.5V 24 MHz X X X IIDLE11 - 4.0 - mA 3.3V 24 MHz X X V IIDLE12 - 2.0 - mA 3.3V 24 MHz X X X IIDLE13 Operating Current Idle Mode HCLK = 24 MHz - 6.1 - mA VDD HXT HIRC PLL All Digital Modules 5.5V X V X V IIDLE14 - 3.2 - mA 5.5V X V X X IIDLE15 - 5.9 - mA 3.3V X V X V IIDLE16 - 3.2 - mA 3.3V X V X X IIDLE17 Operating Current Idle Mode HCLK=22.1184 MHz - 5.7 - mA VDD HXT HIRC PLL All Digital Modules 5.5V X V X V IIDLE18 - 3.0 - mA 5.5V X V X X IIDLE19 - 5.6 - mA 3.3V X V X V IIDLE20 - 3.0 - mA 3.3V X V X X IIDLE9 Operating Current Idle Mode HCLK =12 MHz - 2.5 - mA VDD HXT HIRC PLL All Digital Modules 5.5V V X X V IIDLE10 - 1.5 - mA 5.5V V X X X IIDLE11 - 2.5 - mA 3.3V V X X V IIDLE12 - 1.5 - mA 3.3V V X X X IIDLE13 Operating Current Idle Mode HCLK = 4 MHz - 1.5 - mA VDD HXT HIRC PLL All Digital Modules 5.5V V X X V IIDLE14 - 1.0 - mA 5.5V V X X X

Apr 18, 2017 Page 63 of 74 Rev.1.00 MINI55 SERIES DATASHEET IIDLE15 - 1.5 - mA 3.3V V X X V IIDLE16 - 1.0 - mA 3.3V V X X X IDD17 Operating Current Idle Mode HCLK = 10 kHz - 90 - μA VDD HXT LIRC PLL All Digital Modules 5.5V X V X V[4] IDD18 - 90 - μA 5.5V X V X X IDD19 - 80 - μA 3.3V X V X V[4] IDD20 - 80 - μA 3.3V X V X X IPWD1 Standby Current Power-down Mode (Deep Sleep Mode) - 1.5 - A VDD = 5.5 V, All oscillators and analog blocks turned off. IPWD2 - 1.4 - A VDD = 3.3 V, All oscillators and analog blocks turned off. IIL Logic 0 Input Current P0/1/2/3/4/5 (Quasi- bidirectional Mode) - -70 -75 A VDD = 5.5 V, VIN = 0V ITL Logic 1 to 0 Transition Current P0/1/2/3/4/5 (Quasi- bidirectional Mode) [*3] - -590 -750 A VDD = 5.5 V, VIN = 2.0V ILK Input Leakage Current P0/1/2/3/4 -1 - +1 A VDD = 5.5 V, 0 < VIN< VDD Open-drain or input only mode VIL1 Input Low Voltage P0/1/2/3/4 (TTL Input) -0.3 - 0.8 V VDD = 4.5 V VIH1 Input High Voltage P0/1/2/3/4 (TTL Input) 2.0 - VDD + 0.3 V VDD = 5.5 V 1.5 - VDD + 0.3 VDD = 3.0 V VIL3 Input Low Voltage XTAL1[*2] 0 - 0.8 V VDD = 4.5 V 0 - 0.4 VDD = 2.5 V VIH3 Input High Voltage XTAL1[*2] 3.5 - VDD + 0.3 V VDD = 5.5 V 2.4 - VDD + 0.3 VDD = 3.0 V VILS Negative-going Threshold (Schmitt Input), nRESET -0.3 - 0.2 VDD V - VIHS Positive-going Threshold (Schmitt Input), nRESET 0.7 VDD - VDD + 0.3 V - RRST Internal nRESETPin Pull-up Resistor 17.5 150 kΩ VDD = 2.1 V ~ 5.5V

Apr 18, 2017 Page 64 of 74 Rev.1.00 MINI55 SERIES DATASHEET VILS Negative-going Threshold (Schmitt input), P0/1/2/3/4/5 -0.3 - 0.3 VDD V - VIHS Positive-going Threshold (Schmitt input), P0/1/2/3/4/5 0.7 VDD - VDD + 0.3 V - ISR11 Source Current P0/1/2/3/4/5 (Quasi- bidirectional Mode) -300 -400 - A VDD = 4.5 V, VSS = 2.4 V ISR12 -50 -80 - A VDD = 2.7 V, VSS = 2.2 V ISR13 -40 -73 - A VDD = 2.5 V, VSS = 2.0 V ISR21 Source Current P0/1/2/3/4/5 (Push- pull Mode) -20 -26 - mA VDD = 4.5 V, VSS = 2.4 V ISR22 -3 -5 - mA VDD = 2.7 V, VSS = 2.2 V ISR23 -2.5 -5 - mA VDD = 2.5 V, VSS = 2.0 V ISK11 Sink Current P0/1/2/3/4/5 (Quasi- bidirectional, Open- Drain and Push-pull Mode) 10 15 - mA VDD = 4.5 V, VSS = 0.45 V ISK12 6 9 - mA VDD = 2.7 V, VSS = 0.45 V ISK13 5 8 - mA VDD = 2.5 V, VSS = 0.45 V Note1: nRST pin is a Schmitt trigger input. Note2: XT_IN is a CMOS input. Note3: Pins of P0, P1, P2, P3, P4 and P5 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, the transition current reaches its maximum value when VIN approximates to 2V. Note4: Only enable modules which support 10 kHz LIRC clock source

Apr 18, 2017 Page 65 of 74 Rev.1.00 MINI55 SERIES DATASHEET

8.3.1 External Input Clock

90% 10% tCLCH tCHCL tCLCX tCLCL

0.3 VDD

Note: Duty cycle is 50%. Symbol Parameter Min Typ Max Unit Test Conditions tCHCX Clock High Time 10 - - ns - tCLCX Clock Low Time 10 - - ns - tCLCH Clock Rise Time 2 - 15 ns - tCHCL Clock Fall Time 2 - 15 ns -

8.3.2 External 4~24 MHz High Speed Crystal (HXT)

Symbol Parameter Min. Typ. Max Unit Test Conditions VHXT Operation Voltage 2.1 - 5.5 V - TA Temperature -40 - 105 ℃ - IHXT Operating Current - 410 - uA 12 MHz, VDD = 5.5V fHXT Clock Frequency 4 - 24 MHz -

8.3.3 Typical Crystal Application Circuits

4 MHz ~ 24 MHz 10~20 pF 10~20 pF

Apr 18, 2017 Page 66 of 74 Rev.1.00 MINI55 SERIES DATASHEET XT_IN C1 C2 XT_OUT 4~24 MHz Crystal Vss Vss Figure 8-1 Mini55 Typical Crystal Application Circuit 8.3.4 48 MHz Internal High Speed RC Oscillator (HIRC) Symbol Parameter Min Typ Max Unit Test Conditions VHRC Supply Voltage 1.62 1.8 1.98 V - fHRC Center Frequency - 48 MHz - Calibrated Internal Oscillator Frequency VDD = 5 V VDD = 2.1 V~ 5.5 V IHRC Operating Current - 700 - μA TA = 25 ℃, VDD = 5 V Note: These parameters are characterized but not tested. 8.3.5 10 kHz Internal Low Speed RC Oscillator (LIRC) Symbol Parameter Min Typ Max Unit Test Conditions VLRC Supply Voltage 2.1 - 5.5 V - fLRC Center Frequency - 10 - kHz - Oscillator Frequency -50[1] - +50[1] % VDD = 2.1 V ~ 5.5 V TA = -40℃ ~ +105℃ Note: These parameters are characterized but not tested.

Apr 18, 2017 Page 67 of 74 Rev.1.00 MINI55 SERIES DATASHEET Analog Characteristics 8.4 8.4.1 10-bit SARADC Symbol Parameter Min Typ Max Unit Test Condition - Resolution - - 10 Bit - DNL Differential Nonlinearity Error - -1~1.5 -1~+3 LSB - INL Integral Nonlinearity Error - ±1 ±2 LSB - EO Offset Error - 1 2 LSB - EG Gain Error (Transfer Gain) - -1 -1.5 LSB - - Monotonic Guaranteed - - FADC ADC Clock Frequency - - 8 MHz AVDD = 4.5~5.5 V FS Sample Rate (FADC/TCONV) - - 500 kSPS AVDD = 4.5~5.5 V - - 300 kSPS AVDD = 2.1~5.5 V TACQ Acquisition Time (Sample Stage) N+1 1/FADC N is sampling counter, 128, 256,1024 TCONV Total Conversion Time N+14 1/FADC AVDD Supply Voltage 2.1 - 5.5 V - IDDA Supply Current (Avg.) - 200 - μA AVDD = 5.5 V VIN Analog Input Voltage 0 - AVDD V - CIN Input Capacitance - 12 - pF - RIN Input Load - 7 - kΩ - Note: ADC voltage reference is same with AVDD

Apr 18, 2017 Page 68 of 74 Rev.1.00 MINI55 SERIES DATASHEET 1023 1022 1021 1020 Ideal transfer curve Actual transfer curve Offset Error EO Analog input voltage (LSB) 1023 ADC output code Offset Error EO Gain Error EG EF (Full scale error) = EO + EG DNL

1 LSB

8.4.2 LDO & Power Management

Symbol Parameter Min Typ Max Unit Test Condition VDD DC Power Supply 2.1 - 5.5 V - VLDO Output Voltage 1.62 1.8 1.98 V - TA Temperature -40 25 105 ℃ Note: It is recommended a 0.1μF bypass capacitor is connected between VDD and the closest VSS pin of the device.

8.4.3 Brown-out Detector

Symbol Parameter Min Typ Max Unit Test Condition AVDD Supply Voltage 0 - 5.5 V - TA Temperature -40 25 105 ℃ -

Apr 18, 2017 Page 69 of 74 Rev.1.00 MINI55 SERIES DATASHEET IBOD Quiescent Current - 100 - μA AVDD =5.5V VBOD Brown-out Detector (Falling edge)

4.3 V BOV_VL [2:0] = 3

3.7 V BOV_VL [2:0] = 2

3.0 V BOV_VL [2:0] = 7

2.7 V BOV_VL [2:0] = 1

2.4 V BOV_VL [2:0] = 6

2.2 V BOV_VL [2:0] = 0

2.0 V BOV_VL [2:0] = 5

1.7 V BOV_VL [2:0] = 4

8.4.4 Power-on Reset

Symbol Parameter Min Typ Max Unit Test Condition TA Temperature -40 25 105 ℃ - VPOR Reset Voltage 1.25 V -

8.4.5 Comparator

Symbol Parameter Min Typ Max Unit Test Condition VCMP Supply Voltage 2.1 - 5.5 V TA Temperature -40 25 105 ℃ - ICMP Operation Current - 40 80 μA AVDD=5V VOFF Input Offset Voltage 10 20 mV - VSW Output Swing 0.1 - AVDD – 0.1 V - VCOM Input Common Mode Range 0.1 - AVDD – 0.1 V - - DC Gain - 60 - dB - TPGD Propagation Delay - 200 - ns VCOM=1.2 V, VDIFF=0.1 V VHYS Hysteresis - ±30 - mV VCOM=1.2 V TSTB Stable time - - 1.2 μs

Apr 18, 2017 Page 70 of 74 Rev.1.00 MINI55 SERIES DATASHEET Flash DC Electrical Characteristics 8.5 Symbol Parameter Min Typ Max Unit Test Condition VFLA [2] Supply Voltage 1.62 1.8 1.98 V NENDUR Endurance 20,000 - - cycles[1] TRET Data Retention 10 - - year TA =85℃ TERASE Sector Erase Time - 6 - ms TPROG Program Time - 7.5 - us IDD1 Read Current - 4 - mA IDD2 Program Current - 3.5 - mA IDD3 Erase Current - 2 - mA Note1: Number of program/erase cycles. Note2: VFLA is source from chip LDO output voltage. Note3: Guaranteed by design, not test in production.

Apr 18, 2017 Page 71 of 74 Rev.1.00 MINI55 SERIES DATASHEET

9 PACKAGE DIMENSIONS

48-pin LQFP (7 mm x 7 mm) 9.1

Apr 18, 2017 Page 72 of 74 Rev.1.00 MINI55 SERIES DATASHEET 33-pin QFN (4 mm x 4 mm) 9.3

Apr 18, 2017 Page 73 of 74 Rev.1.00 MINI55 SERIES DATASHEET

10 REVISION HISTORY

2017.04.18 1.00 Preliminary version.

Apr 18, 2017 Page 74 of 74 Rev.1.00 MINI55 SERIES DATASHEET Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic si gnal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure U sage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.