WPCN381U NUVOTON | Alldatasheet
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WPCN381U Legacy-Reduced SuperI/O with Fast Infrared Port, Two Serial Ports and GPIOs © 2009 Nuvoton Technology Corporation www.nuvoton.com April 2009 Revision 1.2 WPCN381U Legacy-Reduced SuperI/O with Fast Infrared Port, Two Serial Ports and GPIOs General Description The WPCN381U, a member of the Nuvoton LPC SuperI/O family, is targeted for legacy-reduced ultra-light portable ap- plications. The WPCN381U is PC2001 and ACPI compliant, and features a Fast Infrared port (FIR, IrDA 1.1 compliant), two Serial Ports and General-Purpose Input/Output (GPIO) support for a total of 11 ports. The WPCN381U is a “no-frills” solution for the new generation of notebook systems, providing just the essential functions. Outstanding Features ■ Pin and software compatible with the Nuvoton 87381 ■ Fast Infrared Port (FIR) ■ Two Serial Ports ■ LPC bus interface, based on Intel’s LPC Interface Specification Revision 1.1, August 2002 (supports CLKRUN and LPCPD signals) ■ PC2001 and ACPI Revision 3.0 compliant ■ 11 GPIO ports, including 6 with IRQ assertion capabil- ity ■ Two testability modes (XOR Tree and TRI-STATE ® device pins). ■ 5V tolerant and back-drive protected pins (except LPC bus pins) ■ 48-pin LQFP package LPC Bus South Bridge TPM Portable PlatformI/O Ports EC Serial Interface WPCN381U FIR/Serial Interface (WPC876xL)(WPCT200) System Block Diagram
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Features
■ Fast Infrared Port (FIR) — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — FIR IrDA 1.1 compliant — HP-SIR — ASK-IR option of SHARP-IR — DASK-IR option of SHARP-IR — Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80 — DMA support: one or two channels ■ Two Serial Ports (SP1 and SP2) — SP2 can be used only when FIR is not needed — Software compatible with the 16550A and the 16450 — Shadow register support for write-only bit monitoring — UART data rates up to 1.5 Mbaud ■ 11 General-Purpose I/O (GPIO) Ports — Supports IRQ assertion — Programmable drive type for each output pin (open- drain, push-pull or output disable) — Programmable option for internal pull-up resistor on each input pin — Output lock option — Input debounce mechanism ■ LPC System Interface — 8-bit I/O cycles — LPCPD and CLKRUN support — Implements PCI mobile design guide recommenda- tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998) ■ PC2001 and ACPI 3.0 Compliant — PnP Configuration Register structure — Flexible resource allocation for all logical devices ❏ Relocatable base address ❏ 15 IRQ routing options ❏ Optional 8-bit DMA channels (where applicable) selected from four possible DMA channels ■ Clock Sources — 14.318 MHz or 48 MHz clock input — LPC clock, 0 MHz, or 25 MHz to 33 MHz ■ Strap Configuration — Base Address (BADDR) strap to determine the base address of the Index-Data register pair — Strap Inputs to select testability mode ■ Power Supply — 3.3V supply operation — All pins are 5V tolerant, except LPC bus pins — All pins are back-drive protected, except LPC bus pins ■ Testability — XOR Tree — TRI-STATE device pins Internal Block Diagram FIR Port/ Serial Port Bus Interface LPC Interface I/O Serial Port Serial Interface GPIO Ports Ports
14.31818 MHz
48 MHz
Revision 1.2 3 www.nuvoton.com WPCN381U Revision Record Revision Date Status Comments September 2006 Draft 0. 92 Draft Datasheet. December 2006 Draft 0.95 Draft Datasheet. March 2007 Draft 0.96 Draft Datasheet. List of changes from Draft 0.95: 1. In DC Characteristics of Pins by I/O Buffer Types, changed:
1.1 In sections: Input, TTL Compatible, Input, TTL Compatible with Schmitt Trigger, Out-
put, Push-Pull Buffer and Output, Open-Drain Buffer, changed “TBD” to “±1 µA“. 1.2 Added new section: “Leakage Current”. 1.3 In Exceptions section, removed items 5 and 6. 2. In V DD Power-Up section, tLRST parameter, changed the Min. value, the Reference Conditions and the related footnote. May 2007 Draft 0.97 Draft Datasheet. Li st of changes from Draft 0.96: On pinout page and back cover: changed the order number from WPCN381U_0DG to WPCN381UA0DG and removed the comment in the parentheses. April 2008 1.0 Final Datasheet. Corrected the name of pin 7 in pin connection diagram ( page 8). November 2008 1.1 Nuvoton version (changed logo and company name). April 2009 1.2 Changed LPC clock frequency values to 0 MHz, or 25 MHz to 33 MHz (in Features, in Section 2.3 and Section 7.4.4. Table 7 is now viewable.
www.nuvoton.com 4 Revision 1.2 WPCN381U Table of Contents
1.0 Signal/Pin Connect ion and Description
2.0 Power, Reset and Clocks
3.0 Device Architecture and Configuration
Table of Contents (Continued) Revision 1.2 5 www.nuvoton.com WPCN381U
Table of Contents (Continued) www.nuvoton.com 6 Revision 1.2 WPCN381U
4.0 LPC Bus Interface
5.0 General-Purpose Input /Output (GPIO) Port
6.0 Legacy Functional Blocks
7.0 Device Characteristics
Table of Contents (Continued) Revision 1.2 7 www.nuvoton.com WPCN381U
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1.0 Signal/Pin Connecti on and Description
1.1 CONNECTION DIAGRAM
48-Pin Low-Profile Plastic Quad Flatpack (LQFP) Order Number WPCN381UA0DG WPCN381UA0DG 48-Pin LQFP (Top View) 37384044 39 41424345464748 SERIRQ VSS VDD LDRQ/XOR_OUT LFRAME LAD0 LAD1 LAD2 LAD3 LRESET CLKRUN/GPIO22 LCLK CLKIN DTR1_BOUT1/BADDR VDD VSS 212019181716151413 VSS VDD GPIO01 GPIO02 GPIO03 GPIO04 VCORF GPIO20 2322 GPIO21/LPCPD GPIO23 RI1 GPIO00 IRRX1/SIN2 IRTX/SOUT2 NC = Not Connected (These pins should be left unconnected, except for XOR Tree operation, where the pins must be pulled low.) CTS1 NC IRRX2_IRSL0/GPIO17 NC GPO24 NC NC NC NC NC NC NC NC DCD1 DSR1 SIN1 RTS1/TRIS SOUT1/TEST
1.0 Signal/Pin Connect ion and Description (Continued)
1.2 BUFFER TYPES AND SIGNAL/PIN DIRECTORY
This section describes all signals. The signals are organized in functional groups.
1.3 PIN MULTIPLEXING
figuration registers and bit values for selecting multiplexed options. Table 2. Pin Multiplexing Configuration Table 1. Buffer Types
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1.4 DETAILED SIGNAL/PIN DESCRIPTIONS
This section describes all signals of the WPCN381U.
1.4.1 LPC Bus Interface
1.4.2 Clocks
1.4.3 Infrared (IR)
1.4.4 Serial Ports (SP1, SP2)
Signal Pin(s) I/O Buffer Type Description LAD3-0 40, 38, 36, 32 I/O IN PCI/OPCI LPC Address-Data. Multiplexed command, address, bidirectional data and cycle status. LCLK 25 I IN PCI LPC Clock. Same as PCI clock. LDRQ 16 O O PCI LPC DMA Request . Encoded DMA request for the LPC interface. LFRAME 30 I IN PCI LPC Frame. Low pulse indicates the begi nning of a new LPC cycle or the termination of a broken cycle. LRESET 27 I IN PCI LPC Reset. Same as PCI system reset. SERIRQ 28 I/O IN PCI/OPCI Serial IRQ. The interrupt requests are serialized over a single pin, where each IRQ level is delivered during a designated time slot. LPCPD 21 I IN PCI Power Down. Indicates that the LPC interface power will be turned off. CLKRUN 19 I/O IN PCI/OD6 Clock Run. Same as PCI CLKRUN . Signal Pin(s) I/O Buffer Type Description CLKIN 43 I IN T Clock In. 14.318 MHz or 48 MHz clock input. Signal Pin(s) I/O Buffer Type Description IRRX1 5 I IN TS IR Receive 1. Primary input for serial data from the FIR transceiver. IRRX2_ IRSL0 7I / O I N TS/O3/6 IRRX2 - IR Receive 2. Auxiliary input for serial data to support a second FIR receiver. IRSL0 - IR Select . Output used to control the FIR transceiver. IRTX 6 O O 6/12 IR Transmit. FIR serial output data. Signal Pin(s) I/O Buffer Type Description CTS1 1I I N TS Clear to Send. When low, indicates that the modem or other data transfer device is ready to exchange data. DCD1 44 I IN TS Data Carrier Detected. When low, indicates that the modem or other data transfer device has detected the data carrier. DSR1 45 I IN TS Data Set Ready. When low, indicates that the data transfer device, e.g., modem, is ready to establish a communications link. DTR1_BOUT1 2 O O 3/6 Data Terminal Ready. When low, indicates to the modem or other data transfer device that the UART is read y to establish a communications link. Baud Output. Provides the associated serial channel baud rate generator output signal if Test Mode is selected, i.e., if bit 7 of the EXCR1 register is set.
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1.4.5 General-Purpose Input/Output (GPIO) Ports
1.4.6 Power and Ground
RI1 3I I N TS Ring Indicator. When low, indicates that a telephone ring signal was received by the modem. RTS1 47 O O 3/6 Request to Send. When low, indicates to the modem or other data transfer device that the corresponding UART is ready to exchange data. A system reset sets this signal to inactive high; a loopback operation holds it inactive. SIN1 46 I IN TS Serial Input. Receives composite serial data from the communications link (peripheral device, modem or other data transfer device). SOUT1 48 O O 3/6 Serial Output. Sends composite serial data to the communications link (peripheral device, modem or other data transfer device). These signals are set active high after a system reset. SIN2 5 I IN TS Serial Input. Same as SIN1. SOUT2 6 O O 6/12 Serial Output. Same as SOUT1. Signal Pin(s) I/O Buffer Type Description GPIO00-04 11, 12, 13, 14, I/O IN TS/ OD6, O3/6 General-Purpose I/O Port 0, bits 0-4. Each pin is configured independent- ly as input or I/O, with or without static pull-up and with either open-drain or push-pull output type. The port supports interrupt assertion, and each pin can be enabled or masked as an interrupt source. GPIO17 7 I/O IN TS/ OD6, O3/6 General-Purpose I/O Port 1, bit 7. Same as Port 0. GPIO20-22 17, 21, I/O IN TS/ OD6, O3/6 General-Purpose I/O Port 2, bits 0-2. Same as Port 0, without interrupt support. GPIO23 22 I/O IN TS/ OD14, O14/14 General-Purpose I/O Port 2, bit 3. Same as Port 0, without interrupt support. GPO24 20 O OD 6, O3/6 General-Purpose Output Port 2, bit 4. The pin is configured independently with or without static pu ll-up and with either open-drain or push-pull output type. Signal Pin(s) I/O Buffer Type Description VDD 35, 24, 8 I PWR Main 3.3V Power Supply. VSS 34, 23, 9 I GND Ground. Signal Pin(s) I/O Buffer Type Description
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1.4.7 Strap Configuration
1.4.8 Test and Miscellaneous
Signal Pin(s) I/O Bu ffer Type Description BADDR 2 I IN TS Base Address. Sampled at V DD Power-Up reset to determine the base address of the configuration Index-Data register pair. – No pull-down resistor (default) - the Index-Data pair at 164Eh-164Fh. – 10 K Ω1 external pull-down resistor - the Index-Data pair at 2Eh-2Fh. The external pull-down resistor must be connected to V SS. 1. Because the strap function is multiplexed with the Serial Port pins, a CMOS transceiver device is recommended for Serial Port functionality; in this case, the value of the external pull-down resistor is 10 KΩ. If, however, a TTL transceiver device is used, the value of the external pull-down resistor must be 470Ω, and since the Serial Port pins are not able to drive this load, the external pull-down resistor must disconnect t EPLV after V DD power-up (see Section 7.4.3 on page 62). TRIS 47 I IN TS TRI-STATE Device. Sampled at VDD power-up to force the device to float all its output and I/O pins. – No pull-down resistor (default) - normal pin operation – 10 K Ω1 external pull-down resistor - floating device pins The external pull-down resistor must be connected to V SS. When TRIS is set to 0 (by an exter nal pull-down resistor), TEST must be 1 (i.e., left unconnected). TEST 48 I IN TS XOR Tree Test Mode. Sampled at VDD power-up to force the device pins into a XOR tree configuration. – No pull-down resistor (default) - normal device operation – 10 K Ω1 external pull-down resistor - pins configured as XOR tree. The external pull-down resistor must be connected to V SS. When TEST is set to 0 (by an external pull-down resistor), TRIS must be 1 (i.e., left unconnected). Signal Pin(s) I/O Bu ffer Type Description XOR_OUT 16 O O PCI XOR Tree Output. All the device pins (except ground and power pins) are internally connected in a XOR tree structure. VCORF 10 I/O - On-Chip Core Power Converter Filter. Powers the core logic of all the device modules. An external 0.1 µF ceramic filter capacitor must be connected between this pin and V SS.
1.5 INTERNAL PULL-UP AND PULL-DOWN RESISTORS
page 60 for the values of each resistor type. Table 3. Internal Pull-Up and Pull-Down Resistors
- Active only during VDD Power-Up reset.
2.1 POWER
2.1.1 Power Planes
on-chip voltage converter. This power plane feeds all the core logic.
2.1.2 Power States
Power Off - VDD is inactive.
2.1.3 Power Connection and Layout Guidelines
erates a voltage below 3V for the internal logic. VDD and VCORF use a common ground return marked VSS. To obtain the best performance, bear in mind the following recommendations. The decoupling capacitors of the Main power supply (V DD) pins. The decoupling capacitor of the on-chip core power converter (V CORF) pin. Note that a low-impedance ground layer also improves noise isolation. addition, place one 10 −47 µF tantalum capacitor on the common net as close to the device as possible. Figure 1. Decoupling Capacitor Connections
2.0 Power, Reset and Clocks (Continued)
2.2 RESET SOURCES AND TYPES
VDD Power-Up Reset - activated when V DD is powered up. Hardware Reset - activated when the LRESET input is asserted (low).
2.2.1 V DD Power-Up Reset
Section 7.4.3 on page 62) to ensure that the WPCN381U operates correctly. during this time, the WPCN381U LPC interface ignores the transaction (that is, it does not return a SYNC handshake). Puts pins with strap options into TRI-STAT E and enables their internal pull-up resistors. Samples the logic levels of the strap pins.
2.2.2 Hardware Reset
Resets all lock bits in configuration registers. Loads default values to all the bits in the Configuration Control. Resets all the logical devices. Loads default values to all the module registers.
2.3 CLOCK DOMAINS
The WPCN381U has two clock domains, as shown in Table 4.
2.3.1 LPC Domain
The LPC clock signal at the LCLK pin must become valid before the end of the Hardware reset (LRESET); see Section 2.2.2. This clock can be stopped using the CLKRUN protocol. clocks, 24 MHz and 48 MHz. After Power-Up or Hardware reset, the clock (Clock Generator or external clock) is disabled. logic level until the clock generator provides a stable output clock that meets all requirements. Then the clock starts toggling. may toggle regardless of the state of the LRESET pin. The Clock Generator waits for a toggling input clock. Table 4. Clock Domains of the WPCN381U
48 MHz 48 MHz On-chip Clock Generator or
www.nuvoton.com 16 Revision 1.2 WPCN381U Bit 4 (read-only) of the CLOCKCF register is the Valid Clock Generator status bit. While stabilizing, the output clock is frozen to a steady logic level, and the status bit is cleared to 0 to indicate a frozen clock. When the clock generator is stable, the output clock starts toggling and the status bit is set to 1. The status bit tells the software when the Clock Generator is ready. The software should poll this status bit until it is set (1), and only then activate the Serial Ports and the Fast Infrared interface. The clock generator and its output clock do not consume power when they are disabled.
2.3.3 WPCN381U Power-Up
To ensure proper operation, proceed as follows after power-up: 3. Set bit 5 of the Clock Generator Control register (CLO CKCF) at Index 29h according to the clock source used. 4. Enable the clock. 5. If the clock source is 14.31818 MHz: — Poll bit 4 of the CLOCKCF register while the clock generator is stabilizing. — When bit 4 of CLOCKCF is set to 1, go to step 6 6. Enable any module in the chip, as needed.
2.3.4 Specifications
Wake-up time is 33 msec (maximum). This is measured from the time the Clock Generator is enabled until the clock is stable. Note: The reference clock must be stable at the time the Clock Generator is enabled. Tolerance (long term deviation) of the generator output clock, rela tive to the input clock, is ±110 ppm. Total tolerance is therefore ± (input clock tolerance + 110 ppm).
2.4 TESTABILITY SUPPORT
2.4.1 ICT
mounted on the tested board. It then checks their outputs for the correct logic levels.
2.4.2 XOR Tree Testing
correct connection of the device pins to the board. VCORF) are excluded from the XOR Tree. During XOR-Tree testing, the Not Connected (NC) pins must be pulled low. Figure 2. XOR Tree (Simplified Diagram) The maximum propagation delay through the XOR tree, from the first pin in the chain to XOR_OUT is 200 ns.
2.4.3 Test Mode Entry Sequence
strap pins and are latched into the WPCN381U on power up. Table 5. Test Mode Selection
3.0 Device Architectur e and Configuration
cluding special implementation of generic blocks, system interface and device configuration.
3.1 OVERVIEW
central internal bus. Figure 3 illustrates the blocks and related logic. write transactions for I/O and DMA, as defined in Intel’s LPC Interface Specification, Revision 1.1. Figure 3. WPCN381U Detailed Block Diagram
3.0 Device Architectur e and Configuration (Continued)
3.2 CONFIGURATION STRUCTURE AND ACCESS
The configuration structure is comprised of a set of banked registers which are accessed via a pair of specialized registers.
3.2.1 The Index-Data Register Pair
Access to the WPCN381U configuration registers is via an Index-Data register pair, using only two system I/O byte locations. ping option on the BADDR pin. Table 6 shows the selected base addresses as a function of BADDR. Table 6. BADDR Strapping Options configuration register file, and holds the index of the configuration register that is currently accessible via the Data register. Reading the Index register returns the last value written to it (or the default of 00h after reset). actually accesses the configuration register that is currently pointed to by the Index register.
3.2.2 Banked Logical Device Registers Structure
values of the WPCN381U functional blocks. Any value not listed is reserved. ister, within the logical device currently selected by the LDN register. Figure 4. Structure of Standard Configuration Register File
02 E h 2 F h
Table 7. Logical Device Number (LDN) Assignments (indicating no DMA channel is active). The configuration registers are accessible immediately after reset.
3.2.3 Standard Configuration Register Definitions
All registers are read/write. these bits. Use read-modify-write to prevent the valu es of reserved bits from being changed during write. Write-only registers must not use read-modify-write during updates. Table 8. Standard General Configuration Registers WPCN381U configuration registers and ID registers. Table 9. Logical Device Activate Register 30h Activate Bits 7-1:Reserved. Bit 0: Logical device activation control; see Section 3.3 on page 23. Table 10. I/O Space Configuration Registers Indicates selected I/O lower limit address bits 15−8 for I/O Descriptor 0. Indicates selected I/O lower limit address bits 7−0 for I/O Descriptor 0.
Table 11. Interrupt Configuration Registers 70h Interrupt Number Indicates selected interrupt number. devices, as it causes the WPCN381U to behave unpredictably. Bit 1: Polarity of interrupt request selected in previous register. Bit 0: Type of interrupt request selected in previous register. Table 12. DMA Configuration Registers channel if more than one DMA channel is used).
- A value of 0, 1, 2, or 3 selects DMA channel 0, 1, 2, or 3, respectively.
- A value of 4 indicates that no DMA channel is active.
- The values 5-7 are reserved.
as it causes the WPCN381U to behave unpredictably. channel if more than one DMA channel is used).
- A value of 0, 1, 2, or 3 selects DMA channel 0, 1, 2, or 3, respectively.
- A value of 4 indicates that no DMA channel is active.
- The values 5−7 are reserved.
as it causes the WPCN381U to behave unpredictably. Table 13. Special Logical Device Configuration Registers Special (vendor-defined) configuration options.
3.2.4 Standard Configuration Registers
Figure 5. Configuration Register Map A subset of these registers is implemented for each logical device. See the functional block descriptions in the following sections. enabled even when the logical device is not activated. Select 1 (Index 75h) allocates a second DMA channel, where applicable.
Revision 1.2 23 www.nuvoton.com WPCN381U Special Configuration The vendor-defined registers, starting at Index F0h, contro l function-specific parameters such as operation modes, power saving modes, pin TRI-STATE, and non-standard extensions to generic functions.
3.2.5 Default Configuration Setup
In the event of a VDD Power-Up or Hardware reset, the WPCN381U wakes up with the following default configuration setup: The configuration base address is 2Eh or 164Eh, according to the BADDR strap pin value, as shown in Table 6 on page 19. All logical devices are disabled. All multiplexed GPIO pins are configured to their respecti ve default function. When configured as GPIO, they have an internal static pull-up (default direction is input). The legacy devices (Serial Ports and FIR) are assigned with their legacy system resource allocation. Nuvoton proprietary functions are not assigned with any defa ult resources; the default values of their base addresses are all 00h. See Section 2.2 on page 15 for more details on WPCN381U reset sources and types.
3.3 MODULE CONTROL
3.3.1 Module Enable/Disable
Module control is performed primarily through the Activation bit (bit 0 of Index 30h) of each logical device. The operation of each module can be controlled by the host through the LPC bus. Module enable/disable by the host through the LPC bus is controlled by the following bits: Activation bit (bit 0) in Index 30h of the Standard configurat ion registers; see Section 3.2.3 on page 20 . Fast Disable bit in SIOCF6 register; for Serial Ports 1-2 and FIR modules only; see Section 3.7.4 on page 28 . Global Enable bit (GLOBEN) in SIOCF1 register; see Section 3.7.2 on page 27 . A module is enabled only if all of these bits are set to their “enable” value. When a legacy module (SP1, SP2, FIR) is disabled, the following occurs: The host system resources of the logical device (IRQ, DMA and runtime address range) are unassigned. Access to the standard- and device-spe cific Logical Device configuration registers through the LPC bus remains en- abled. Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). The module’s internal clock is disabled (the module is not functional) to lower the power consumption. When a GPIO module is disabled, the following occurs: The host system resources of the logical device (IRQ and runtime address range) are unassigned. Access to the standard- and device-spe cific Logical Device configuration registers through the LPC bus remains en- abled. Access to the module’s runtime registers through the LPC bus is disabled (transactions are ignored; SYNC cycle is not generated). The module is functional.
3.3.2 Floating Module Output
The pins of the Legacy modules (Serial Port 1) can be floated. When the TRI-STATE Control bit (bit 0) is set in the specific module configuration register (at Index F0h of the specific logical device in the configuration space) and the module is dis- abled (see Section 3.3.1), the module output signals are floated and the I/O signals are configured as inputs (note that the logic level at the inputs is ignored by the module, which is disabled).
Figure 6 shows the control mechanism for floating the pins of a Legacy module. Figure 6. Control of Enabling and of Floating Legacy Module Pins
3.4 INTERNAL ADDRESS DECODING
blocks. However, the number of configurable bits in the base address registers varies for each logical device.
- Wherever the bit is implemented
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3.5 PROTECTION
The WPCN381U provides features to protect the hardware co nfiguration from changes made by application software run- ning on the host. The protection is activated by the software setting a “sticky” lock bit. Each lock bit protects a group of configuration bits lo- cated either in the same register or in different registers. When the lock bit is set, the lock bit and all the protected bits become read-only and cannot be further modified by the host through the LPC bus. All the lock bits are reset by Hardware reset, thus unlocking the protected configuration bits. The bit locking protection mechanism is optional. The protected groups of configuration bits are described below.
3.5.1 Multiplexed Pin Configuration Lock
Protects the configuration of all the multiplexed device pins. Lock bit: LOCKMCF in SIOCF1 regi ster (Device Configuration). Protected bits: LOCKMCF and IOWAIT (in SIOCF1 register) and all bits in SIOCF2 and SIOCFC registers (Device Con- figuration).
3.5.2 GPIO Ports Configuration Lock
Protects the configuration (but not the data) of all the GPIO Ports. Lock bit: LOCKGCF in SIOCF1 register (Device Configuration). Protected bits for each GPIO Port: LOCKGCF in SIOCF1 register, and all bits in GPCFG register (except LOCKCFP bit) and GPEVR register (Device Configuration).
3.5.3 Fast Disable Configuration Lock
Protects the Fast Disable bits for all the Legacy modules. Lock bit: LOCKFDS in SIOCF6 register (Device Configuration). Protected bits: All bits in SIOCF6 regi ster (except General-Purpose Scratch bi ts) and GLOBEN bit in SIOCF1 register Device Configuration).
3.5.4 Clock Control Lock
Protects the Clock Generator control bits. Lock bit: LOCKCCF in CLOCKCF regi ster (Device Configuration). Protected bits: All bits in CLOCKCF register (Device Configuration).
3.5.5 GPIO Ports Lock
Protects the configuration and data of all the GPIO Ports. Lock bit: LOCKCFP in GPCFG register, for each GPIO Port (Device Configuration). Protected bits for each GPIO Port: PUPCTL, OUTTYPE and OUTENA in GP CFG register; the corresponding bit (to the port pin) in GPDO register (GPIO Ports).
3.6 REGISTER TYPE ABBREVIATIONS
The following abbreviations are used to indicate the Register Type: R/W = Read/Write. R = Read from register (data written to this address is sent to a different register). W = Write (see above). RO = Read Only. Writing to the register/bit is ignored. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect. R/W1S = Read/Write 1 to Set. Writing 1 to a bi t sets its value to 1. Writing 0 has no effect.
3.7 SUPERI/O CONFIGURATION REGISTERS
20h-2Eh). See Table 14 for a summary and directory of these registers. Table 14. SuperI/O Configuration Registers
3.7.1 SuperI/O ID Register (SID)
This register contains the identity number of the chip. The WPCN381U family is identified by the value F4h.
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3.7.2 SuperI/O Configuration 1 Register (SIOCF1)
Location: Index 21h Type: Varies per bit
3.7.3 SuperI/O Configuration 2 Register (SIOCF2)
Location: Index 22h Type: R/W or RO Bit 76 5 43210 Name LOCKMCF LOCKGCF Reserved (must be ‘01’) IOWAIT Reserved GLOBEN Reset 00 0 10001 Bit Type Description 7R / W 1 S LOCKMCF (Lock Multiplexing Configuration). When set to 1, locks the configuration of registers SIOCF1, SIOCF2 and SIOCFC by disabling writing to all bits in these registers (including the LOCKMCF bit itself), except for the LOCKGCF and GLOBEN bits in SIOCF1. Once set, this bit can only be cleared by Hardware reset. 0: R/W bits are enabled for write (default). 1: All bits are RO. 6R / W 1 S LOCKGCF (Lock GPIO Pins Configuration). When set to 1,locks the conf iguration registers of all GPIO pins (see Section 3.10.3 on page 33 ) by disabling writes to all their bits (including the LOCKGCF bit itself). The locked registers include the GPCFG (except LOCKCFP bit) and GPEVR registers of all GPIO pins. Once set, this bit can only be cleared by Hardware reset. 0: R/W bits are enabled for write (default). 1: All bits are RO. 5-4 Reserved. These bits must be ‘01’. 3-2 R/W or RO IOWAIT (Number of I/O Wait States). Sets the number of wait states for I/O transactions through the LPC bus. Bits 3 2 Number of Wait States 0 0: 0 (default). 01 : 2 . 10 : 6 . 1 1: 12. 1 Reserved. This bit must be 0. 0R / W o r RO GLOBEN (Global Device Enable). Makes it possible to disable all logical devices by setting a single bit (to 0). In addition, when the bit is set to 1, it enables the operation of all the logical devices of the WPCN381U, as long as the logical device is itself enabled (see Table 7 on page 20 ). The behavior of the devices is explained in Section 3.3 on page 23 . 0: All logical devices in the WPCN381U are disabled and their resources are released. 1: Enables each WPCN381U logical device that is itself enabled (default); see Section 3.3.1 on page 23. Bit 7654 3 210 Name Reserved1 1. During initialization, this reserved field must be set to ‘00’ to allow correct operation of the chip. CLKRUNSEL Reserved LPCPDSEL Reserved IRRX2SEL Reserved Reset 0110 0 011 Bit Description 7-6 Reserved. This field must be initialized to ‘00’.
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3.7.4 SuperI/O Configuration 6 Register (SIOCF6)
This register provides a fast way to disable one or more modules without acce ssing the Activate regi ster of each; see Section 3.3.1 on page 23. Location: Index 26h Type: Varies per bit 5 CLKRUNSEL (CLKRUN Selection Control). Selects the function connected to pin 19. This bit is reset on V DD power-up only. Bit 5F u n c t i o n 0: GPIO22. 1: CLKRUN (default). 4 Reserved. 3 LPCPDSEL (LPCPD Selection Control). Selects the function connected to pin 21. This bit is reset on V DD power-up only. Bit 3F u n c t i o n 0: GPIO21 (default). 1: LPCPD 2 Reserved. 1 IRRX2SEL (IRRX2 Selection Control). Selects the function connected to pin 7. 0: GPIO17. 1: IRRX2_IRSL0 (default). 0 Reserved. Bit 76543210 Name LOCKFDS General-Purpose Scratch Reserved SER1DIS FIRDIS Reserved Reset 00000000 Bit Type Description 7R / W 1 S LOCKFDS (Lock Fast Disable Configuration). When set to 1, this bit locks itself, SER1DIS and FIRDIS bits in this register and GLOBEN bit in SIOCF1 regist er by disabling writing to all of these bits. Once set, this bit can only be cleared by Hardware reset. 0: R/W bits are enabled for write (default). 1: All bits are RO. 6-5 R/W General-Purpose Scratch. 4 Reserved. 3R / W or RO SER1DIS (Serial Port 1 Disable). 0: Enabled or Disabled, according to Activation bit (default). 1: Disabled. 2R / W or RO FIRDIS (Fast InfraRed and Serial Port 2 Disable). 0: Enabled or Disabled, according to Activation bit (default). 1: Disabled. 1-0 Reserved. Bit Description
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3.7.5 SuperI/O Revision ID Register (SRID)
This register contains the ID number of the specific family member (Chip ID) and the chip revision number (Chip Rev). Location: Index 27h Type: RO
3.7.6 Clock Generator Control Register (CLOCKCF)
Location: Index 29h Type: Varies per bit Bit 76543210 Name Chip ID Chip Rev Reset 000XXXXX Bit Description 7-5 Chip ID. For the WPCN381U device, these bits are ‘000’. 4-0 Chip Rev. These bits identify the device revision. Bit 76 5 43210 Name CKEN Reserved CK48SEL CKVALID LOCKCCF Reserved Reset 00 0 00000 Bit Type Description 7R / W o r RO CKEN (Clock Enable). Enables the internal clock of the WPCN 381U. If the clock source selected by CK48SEL bit is the Clock Generator, CKEN enables the Clock Generator; otherwise, it enables the path from the CLKIN input pin. 0: Clock disabled (default). 1: Clock enabled. 6 Reserved. 5R / W o r RO CK48SEL (48 MHz Clock Select). Selects the source of the internal 48 MHz clock. 0: The source of the internal 48 MHz clock is CLKIN pin (default). Use when the CLKIN pin is connected to a 48 MHz clock source. 1: The source of the internal 48 MHz clock is the Clock Generator. Use when the CLKIN pin is connected to a 14.31818 MHz clock source. 4R O CKVALID (Valid Clock Generator, Clock Status). Indicates the status of the on-chip, 48 MHz Clock Generator and controls the generator output clock signal. The WPCN381U modules using this clock may be enabled (see Section 3.3.1 on page 23 ) only after this bit is read high (generator clock is valid). 0: Generator output clock frozen (default). 1: Generator output clock active (stable and toggling). 3R / W 1 S LOCKCCF (Lock Clock Configuration). When set to 1, this bit locks the CLOCKCF register by disabling writing to all its bits (including to the LO CKCCF bit itself). Once set, this bit can only be cleared by Hardware reset. 0: The R/W bits are enabled for write (default). 1: All the bits are read-only. 2-0 Reserved.
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3.7.7 SuperI/O Configuration C Register (SIOCFC)
Location: Index 2Ch Type: R/W or RO Bit 76543210 Name Reserved SP2SEL Reset 00000000 Bit Description 7-1 Reserved. 0 SP2SEL (Serial Port 2 Selection Control). Selects the function connected to pins 5, 6. 0: IRRX1, IRTX (default). 1: SIN2, SOUT2.
3.8 FAST INFRARED AND SERIAL PORT 2 CONFIGURATION
3.8.1 Logical Device 2 (FIR and SP2) Configuration
Table 15. Fast Infrared and Serial Port 2 Configuration Registers
3.8.2 Fast Infrared and Serial Port 2 Configuration Register
7 Bank Select Enable. Enables bank switching for Fast Infrared and Serial Port 2. 0: All attempts to access th e extended registers in Fast Infrared and Serial Port 2 are ignored (default). 1: Enables bank switching for Fast Infrared and Serial Port 2. the Fast Infrared and Serial Port 2 logical device. 0: No transfer in progress (default). maintained (unlike Active bit in Index 30, which also prevents access to Infrared registers). Fast Infrared and Serial Port 2 clock enabled. Infrared is functional when the logical device is active (default).
3.9 SERIAL PORT 1 CONFIGURATION
3.9.1 Logical Device 3 (SP1) Configuration
Table 16. Serial Port 1 Configuration Registers
3.9.2 Serial Port 1 Configuration Register
7 Bank Select Enable. Enables bank switching for Serial Port 1. the Serial Port 1 logical device. 0: No transfer in progress (default). vents access to Serial Port 1 registers). Serial Port 1 clock enabled. Serial Port 1 is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE.
3.10 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION
3.10.1 General Description
Port 0 contains five GPIOE pins (i.e., GPIO pins with event detection). Port 1 contains one GPIOE pin. Port 2 contains four GPIO pins (i.e., GPIO pins without event detection) and one GPO pin. . The GPIO base address is 16-byte aligned. Address bits 3-0 are used to indicate the register offset. Table 17. Runtime Registers in GPIO Address Space
3.10.2 Implementation
detection functionality, are reserved.
3.10.3 Logical Device 7 (GPIO) Configuration
Table 18 lists the configuration registers that affect the GPIO. Only the last thr ee registers (F0h - F2h) are described here. Table 18. GPIO Configuration Register
Figure 7 shows the organization of these registers. Figure 7. Organization of GPIO Pin Registers
3.10.4 GPIO Pin Select Register (GPSEL)
GPIO Pin Configuration register). only values that correspond to implemented GPIO pins are legal.
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3.10.5 GPIO Pin Configuration Register (GPCFG)
This register reflects, for both read and write, the register currently selected by the GPIO Pin Select register (GPSEL). All the GPIO Pin registers that are accessed via this register have a common bit structure, as shown below. This register is reset to 44h for port 0 and port 1, and to 04h for port 2. Location: Index F1h Type: Varies per bit Port 0, pins 0-4; Port 1, pin 7 (with event detection capability): Port 2, pins 0-4 (without event detection capability): Bit 76543210 Name Reserved EVDBNC EVPOL EVTYPE LOCKCFP PUPCTL OUTTYPE OUTENA Reset 01000100 Bit 76543210 Name Reserved LOCKCFP PUPCTL OUTTYPE OUTENA Reset 0 0 000100 Bit Type Description 7 Reserved. 6R / W o r RO EVDBNC (Event Debounce Enable). (Port 0 and Port 1, pin 7 with event detection capability). Enables transferring the signal only after a predetermined debounce period. 0: Disabled. 1: Enabled (default). Reserved. (Port 2 always 0). 5R / W o r RO EVPOL (Event Polarity). (Port 0 and Port 1, pin 7 with event detection capability). Defines the polarity of the signal that issues an interrupt from the co rresponding GPIO pin (falling/low or rising/high). 0: Falling edge or low level input (default). 1: Rising edge or high level input. Reserved. (Port 2). Always 0. 4R / W o r RO EVTYPE (Event Type). (Port 0 and Port 1, pin 7 with event de tection capability). Defines the type of the signal that issues an interrupt from the corresponding GPIO pin (edge or level). 0: Edge input (default). 1: Level input. Reserved. (Port 2). Always 0. 3R / W 1 S LOCKCFP (Lock Configuration of Pin) . When set to 1, locks the GPIO pin configuration and data (see also Section 5.4 on page 42 ) by disabling writing to itself, to GPCFG register bits PUPCTL, OUTTYPE and OUTENA, and to the corresponding bit in GPDO register. Once set, this bit can only be cleared by reset. 0: R/W bits are enabled for write (default). 1: All bits are RO. 2R / W o r RO PUPCTL (Pull-Up Control). This bit is used to enable/disable the internal pull-up capability of the corresponding GPIO pin. It supports open-drain output signals with internal pull-ups and TTL input signals. 0: Disabled. 1: Enabled (default). 1R / W o r RO OUTTYPE (Output Type). Controls the output buffer type (open-drain or push-pull) of the corresponding GPIO pin. 0: Open-drain (default). 1: Push-pull. 0R / W o r RO OUTENA (Output Enable). Indicates the GPIO pin output state. It has no effect on the input path. 0: TRI-STATE (default). 1: Output enabled.
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3.10.6 GPIO Event Routing Register (GPEVR)
This register enables the routing of the GPIO event to IRQ. It is implemented only for ports 0,1 which have event detection capability. Location: Index F2h Type: R/W Bit 76543210 Name Reserved EV2IRQ Reset 00000000 Bit Description 7-1 Reserved. 0 EV2IRQ (Event to IRQ Routing). Controls the routing of the ev ent from the selected GPIO pin to IRQ; see Section 5.3.2 on page 40 . 0: Disabled (default). 1: Enabled.
4.1 OVERVIEW
Specification, Revision 1.1.
4.2 LPC TRANSACTIONS
4.3 CLKRUN FUNCTIONALITY
An IRQ is pending internally, waiting to be sent through the serial IRQ. A DMA request is pending internally, wait ing to be sent through the serial DMA. Note: When the CLKRUN signal is not in use, the WPCN381U assumes a valid clock on the LCLK pin.
4.4 LPCPD FUNCTIONALITY
er supply exists while LPCPD is active, it is not mandatory to reset the WPCN381U when LPCPD is deasserted.
4.5 INTERRUPT SERIALIZER
The Interrupt Serializer translates internal IRQ sources into serial interrupt request data transmitted over the SERIRQ bus. Figure 8 shows the interrupt serialization mechanism. Figure 8. Interrupt Serialization Mechanism
5.0 General-Purpose Inpu t/Output (GPIO) Port
This chapter describes one 8-bit port. A device may include a combination of several ports with different implementations. For the device specific implementation, see Section 3.10 on page 33.
5.1 OVERVIEW
Back-drive protected pins. behavior of each pin. There are two 8-bit registers for each GPIO pin. n in each one of the four registers is associat ed with GPIOXn pin, where X is the port number. cludes event detection and system notification. Figure 9. GPIO Port Architecture
8 GPCFG
8 GPEVR
5.0 General-Purpose Input /Output (GPIO) Port (Continued)
5.2 BASIC FUNCTIONALITY
GPDI. The configuration and operation of a single GPIOXn pin (pin n in port X) is shown in Figure 10. Figure 10. GPIO Basic Functionality
5.2.1 Configuration Options
Port Direction - Controlled by the Output Enable bit (bit 0). portion of the output buffer. (Including the Lock bit itself). Once locked, it can be released by reset only.
5.2.2 Operation
the external device when the port is configured as an input port). Writing to this register is ignored. or the GPDO value; there is thus no effect on the outputs of the pins.
5.3 EVENT HANDLING AND SYSTEM NOTIFICATION
capability is shown in Figure 11. System notification is shown in Figure 12. Figure 11. Event Detection
5.3.1 Event Configuration
mined behavior of the source pin. The GPCFG register determines the event detection trigger type for the system notification. active level (for level) is determined by Event Polarity (bit 5 of the GPCFG register). of the GPEVEN register setting. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. the IRQ deassertion is not acceptable. The debounce is controlled by Event Debounce Enable (bit 6 of the GPCFG register).
5.3.2 System Notification
System notification on GPIO-triggered events is done by asserting an Interrupt Request (via the device’s Bus Interface). The system notification for each GPIO pin is controll ed by the corresponding bits in the GPEVEN and GPEVR registers. mechanism is shown in Figure 12.
Figure 12. GPIO Event Routing Mechanism The GPEVST register reflects the event source pending status. bit settings. Writing 1 to the Status bit clears it to 0. Writing 0 is ignored. The Event Type is level and the pin is at active level. The Event Type is edge and the corresponding bit of t he GPEVST register is set. The target means of system notification is asserted if at least one GPIO pin is in event pending state. figuration. The assertion of any means of system notification is blocked when the GPIO functional block is deactivated. System event notification functionality is provided even when the GPIO pin is enabled as output. is recommended to disable the input debouncer. is disabled. The target IRQ line is detached from the GPIO and deasserted. the status registers are cleared.
5.4 GPIO PORT REGISTERS
R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
5.4.1 GPIO Pin Configuration Registers Structure
which reflect the configuration of the currently selected pin (see Table 19).
5.4.2 GPIO Port Runtime Register Map
5.4.3 GPIO Data Out Register (GPDO)
Table 19. GPIO Configuration Registers
- Depending on port number.
- The location of this register is defined in Section 3.10.1 on page 33.
of the pin value and configuration. 0: Corresponding pin driven to low. 1: Corresponding pin driven or released (accordi ng to buffer type selection) to high (default).
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5.4.4 GPIO Data In Register (GPDI)
Location: Device specific Type: RO
5.4.5 GPIO Event Enable Register (GPEVEN)
Location: Device specific Type: R/W
5.4.6 GPIO Event Status Register (GPEVST)
Location: Device specific Type: R/W1C Bit 76543210 Name DATAIN Reset XXXXXXXX Bit Description 7-0 DATAIN (Data In). Bits 7-0 correspond to pins 7-0 of the specific Port. Reading each bit returns the value of the corresponding GPIO pin. Pin configuration and the GPDO re gister value may influence the pin value. Writes are ignored. 0: Corresponding pin level low. 1: Corresponding pin level high. Bit 76543210 Name EVTENA Reset 00000000 Bit Description 7-0 EVTENA (Event Enable). Bits 7-0 correspond to pins 7-0 of th e specific Port. Each bit enables system notification by the corresponding GPIO pin. The bit has no effect on the co rresponding Status bit in GPEVST register. 0: Event pending by corresponding GPIO pin masked. 1: Event pending by corresponding GPIO pin enabled. Bit 76543210 Name EVTSTAT Reset 00000000 Bit Description 7−0 EVTSTAT (Event Status). Bits 7-0 correspond to pins 7-0 of the specific Port. The setting of each bit is independent of the Event Enable bit in GPEVEN register. An active event sets the Status bit, which may be cleared only by software writing 1 to the bit. 0: No active edge or level detected since last cleared. 1: Active edge or level detected.
www.nuvoton.com 44 Revision 1.2 WPCN381U This chapter briefly describes the following blocks, which provide legacy device functions: Serial Port 1 (SP1) Fast Infrared and Serial Port 2 (FIR and SP2) The description of each Legacy block includes the sections listed below. For details on the general implementation of each legacy block, see the SuperI/O Legacy Functional Blocks Datasheet. General Description Register Map table(s) Bitmap table(s) The register maps in this chapter use the following abbreviations for Type: R/W = Read/Write. R = Read from a specific address returns the value of a specific register. Write to the same address is to a different register. W = W r i t e . RO = Read Only. R/W1C = Read/Write 1 to Clear. Writing 1 to a bit clears it to 0. Writing 0 has no effect.
6.1 SERIAL PORT 1 (SP1)
6.1.1 General Description
The Serial Port functional block supports serial data communication with a remote peripheral device or modem using a wired interface. The Serial Port can function in one of three modes: 16450-Compatible mode (Standard 16450) 16550-Compatible mode (Standard 16550) Extended mode Extended mode provides advanced functionality for the UART. The Serial Port provides receive and transmit channels that can operate concurrently in full-duplex mode. It performs all func- tions required to conduct parallel data interchange with the system and composite serial data exchange with the external data channel, including: Format conversion between the internal parallel data format and the external programmable composite serial format Serial data timing generation and recognition Parallel data interchange wi th the system using a choice of bi directional data tr ansfer mechanisms Status monitoring for all phases of communication activity Complete MODEM-control capability. Existing 16550-based legacy software is completely and transparently supported. Module organization and specific fallback mechanisms switch the module to 16550-Compatible mode on reset or when initialized by 16550 software.
6.1.2 Register Bank Overview
Four register banks, each containing eight registers, control Serial Port operation. All registers use the same 8-byte address space to indicate offsets 00h through 07h. The active bank must be selected by the software. The register bank organization enables access to the banks as required for activation of all module modes, while maintaining transparent compatibility with 16450 or 16550 software. The Bank Selection register (BSR) selects the acti ve bank and is common to all banks as shown in Figure 13. Therefore, each bank defines seven new registers. The default bank selection after system reset is 0.
6.0 Legacy Functional Blocks (Continued)
Figure 13. Register Bank Architecture
6.1.3 SP1 Register Maps
Table 20. Bank 0 Register Map
16550 Banks
Table 21. Bank 1 Register Map Table 22. Bank 2 Register Map Table 23. Bank 3 Register Map
6.1.4 SP1 Bitmap Summary
Table 24. Bank 0 Bitmap Table 25. Bank 1 Bitmap
Table 26. Bank 2 Bitmap Table 27. Bank 3 Bitmap
6.2 FAST INFRARED AND SERIAL PORT 2 (FIR AND SP2)
6.2.1 General Description
datasheet of the relevant device. Note: Since Serial Port 2 and FIR use the same hardware, only one of them can be used at a time. anisms switch the Serial Port to 16550-Compatible mode on reset or when initialized by 16550 software. speed, full-duplex, UART-based applications.
6.2.2 Register Bank Overview
space to indicate offsets 00h-07h. The active bank must be selected by the software. transparent compatibility with 16450 or 16550 software. defines seven new registers. The default bank selection after system reset is 0. Figure 14. FIR and SP2 Register Bank Architecture banks 4-7 control and configure the IR modes only.
Table 28. Register Bank Summary
6.2.3 FIR and SP2 Register Map
Table 29. Bank 0 Register Map Table 30. Bank 1 Register Map
Table 31. Bank 2 Register Map Table 32. Bank 3 Register Map Table 33. Bank 4 Register Map
Table 34. Bank 5 Register Map Table 35. Bank 6 Register Map Table 36. Bank 7 Register Map
6.2.4 FIR and SP2 Bitmap Summary
Table 37. Bank 0 Bitmap Table 38. Bank 1 Bitmap
Table 39. Bank 2 Bitmap Table 40. Bank 3 Bitmap Table 41. Bank 4 Bitmap
Table 42. Bank 5 Bitmap Table 43. Bank 6 Bitmap Table 44. Bank 7 Bitmap
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7.1 GENERAL DC ELECTRICAL CHARACTERISTICS
7.1.1 Recommended Operating Conditions
7.1.2 Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt- ages are relative to ground.
7.1.3 Capacitance
7.1.4 Power Consumption under Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit VDD Supply Voltage 3.0 3.3 3.6 V TA Operating Temperature 0 +70 °C Symbol Parameter Conditions Min Max Unit VDD Supply Voltage −0.5 +4.1 V VI Input Voltage LPC1 signals, and also the signals mul- tiplexed with them 1. LCLK, LAD3-0, LFRAME, LRESET, SERIRQ, LPCPD, LDRQ, CLKRUN. −0.5 V DD + 0.5 V All other pins −0.5 5.5 V VO Output Voltage LPC1 signals, and also the signals mul- tiplexed with them −0.5 V DD + 0.5 V All other pins −0.5 5.5 V TSTG Storage Temperature −65 +150 °C PD Power Dissipation 500 mW TL Lead Temperature Soldering (10 s) +260 °C ESD Tolerance CZAP = 100 pF R ZAP = 1.5 K Ω2 2. Value based on test complying with RAI-5-048-RA human body model ESD testing. 2000 V Symbol Parameter Min2 Typ1 1. TA = 25°C, f = 1 MHz. Max2 2. Not tested; guaranteed by design. Unit CLCLK LCLK Pin Capacitance 5 8 12 pF CPIN Other Pins Capacitance 8 10 pF Symbol Parameter Conditions Typ Max Unit IDD VDD Average Main Supply Current V IL = 0.5 V, V IH = 2.4 V No Load 81 0 m A IDDLP VDD Quiescent Main Supply Current in Low Power Mode VIL = V SS, VIH = V DD No Load 1.5 2 mA
7.0 Device Characteristics (Continued)
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7.1.5 Voltage Thresholds
7.2 DC CHARACTERISTICS OF PINS, BY I/O BUFFER TYPES
The following tables summarize the DC characteristics of all device pins described in the Chapter 1.2 on page 9. The char- acteristics describe the general I/O buffer types defined in Table 1 on page 9. For exceptions, refer to Section 7.2.8 on page 59. The DC characteristics of the system interface meet the PCI2.2 3.3V DC signaling. 7.2.1 Input, PCI 3.3V Symbol: INPCI
7.2.2 Input, TTL Compatible
Symbol: INT Symbol Parameter1 1. All parameters specified for 0°C ≤ TA ≤ 70°C. Min2 2. Not tested; guaranteed by characterization. Typ Max2 Unit VDDON VDD Detected as Power-on 2.2 2.6 2.9 V VDDOFF VDD Detected as Power-off 2.1 2.5 2.8 V Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 0.5V DD VDD + 0.5 1 1. Not tested; guaranteed by design. V VIL Input Low Voltage −0.51 0.3VDD V lILK 2. For additional conditions, see Section 7.2.8 on page 59. Input Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested; guaranteed by design. V VIL Input Low Voltage −0.51 0.8 V IILK 2. For additional conditions, see Section 7.2.8 on page 59. Input Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA VDD = 3.0V - 3.6V and V DD < V PIN < 5.5V 3 3. Only if all the buffers of the specific pin are back-drive protected and 5V tolerant. ±1 µA
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7.2.3 Input, TTL Compatible with Schmitt Trigger
Symbol: INTS 7.2.4 Output, PCI 3.3V Symbol: OPCI
7.2.5 Output, Push-Pull Buffer
Symbol: Op/n Output, push-pull buffer that is capable of sourcing p mA and sinking n mA.
7.2.6 Output, Open-Drain Buffer
Symbol: ODn Output, Open-Drain output buffer, capable of sinking n mA. Output from these signals is open-drain and cannot be forced high. Symbol Parameter Conditions Min Max Unit VIH Input High Voltage 2.0 5.51 1. Not tested; guaranteed by design. V VIL Input Low Voltage −0.5 1 0.8 V VH Input Hysteresis 2502 2. Not tested; guaranteed by characterization. mV IILK 3. For additional conditions, see Section 7.2.8 on page 59. Input Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA VDD = 3.0V - 3.6V and V DD < V PIN < 5.5V 4 4. Only if all the buffers of the specific pin are back-drive protected and 5V tolerant. ±1 µA Symbol Parameter Conditions Min Max Unit VOH Output High Voltage l out = −500 µA0 . 9 V DD V VOL Output Low Voltage l out =1500 µA0 . 1 V DD V lOLK 1. For additional conditions, see Section 7.2.8 on page 59. Output Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA Symbol Parameter Conditions Min Max Unit VOH Output High Voltage I OH = −p mA 2.4 V VOL Output Low Voltage I OL = n mA 0.4 V IOLK 1. For additional conditions, see Section 7.2.8 on page 59. Output Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA VDD = 3.0V - 3.6V and V DD < V PIN < 5.5V 2 2. Only if all the buffers of the specific pin are back-drive protected and 5V tolerant. ±1 µA Symbol Parameter Conditions Min Max Unit VOL Output Low Voltage I OL = n mA 0.4 V IOLK 1. For additional conditions, see Section 7.2.8 on page 59. Output Leakage Current V DD = 3.0V - 3.6V and 0 < V PIN < V DD ±1 µA VDD = 3.0V - 3.6V and V DD < V PIN < 5.5V 2 2. Only if all the buffers of the specific pin are back-drive protected and 5V tolerant. ±1 µA
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7.2.7 Leakage Current
7.2.8 Exceptions
- All pins are 5V tolerant except for the pins with PCI (IN PCI, OPCI) buffer types. 2. All pins are back-drive protected, except for the pins with PCI (INPCI, OPCI) buffer types. 3. I ILK and IOLK are measured in the following cases (where applicable): — Internal pull-up resistor is disabled. — Push-pull output buffer is disabled (TRI-STATE mode). — Open-drain output buffer is at high level. 4. I ILK and IOLK are not cumulative per pin. This means that for pins having multiple buffer types (such as different types of input buffers or input/output buffers), the leakage current is the maximum caused by the relevant buffer types at the given supply voltage and pin voltage. 5. The following pins have an internal static pull-up resistor (when enabled) and therefore may have leakage current from VDD (when VIN = 0): GPIO00-04, GPIO17, GPIO20-23, GPO24. 6. The following strap pins have an internal static pull-up resistor enabled during V DD Power-Up reset and therefore may have leakage current to VDD (when VIN = 0): BADDR, TRIS, TEST. 7. I OH is valid for a GPIO pin only when it is not configured as open-drain.
7.2.9 Terminology
Back-Drive Protection. Back-drive protected pins sustain any voltage within the specified voltage limits when the device power supply is off. 5-Volt Tolerance. 5V-tolerant pins sustain 5V even if the applied voltage is above the device power supply voltage. A pin is 5V-tolerant in the following conditions (where applicable): Internal pull-up or pull-down resistor is disabled Push-pull output buffer is disabled (TRI-STATE mode) Note: If a pin has multiple buffers, the lowest “maximum voltage” among the buffers is the “maximum voltage” allowed to be applied to the pin. Symbol Parameter Conditions Min Max1 1. Not tested; guaranteed by characterization. Unit ILKTOT Total leakage of all device pins V DD = 3.0V - 3.6V and 0 < VPIN < VDD -2 0 µA ILKTOT5 Total leakage of all 5V-tolerant pins VDD = 3.0V - 3.6V and VDD < VPIN < 5.5V - 20 µA IBD Leakage of back-drive protected input and output pins VDD = 0V and VPIN < 5.5V - 1 µA
7.3 INTERNAL RESISTORS
Figure 15. Internal Resist or Test Conditions, TA = 0 °C to 70 °C, VSUP = 3.3V Figure 16. Internal Pull-Up Resistor for Straps, T A = 0 °C to 70 °C, VSUP = 3.3V
- The equivalent resistance of the pull-up resistor is calculated by R PU = (VSUP − VPIN) / IPU.
- The equivalent resistance of the pull-down resistor is calculated by R PD = VPIN / IPD.
7.3.1 Pull-Up Resistor
7.3.2 Pull-Down Resistor
- Not tested; guaranteed by characterization.
- Not tested; guaranteed by characterization.
7.4 AC ELECTRICAL CHARACTERISTICS
7.4.1 AC Test Conditions
Figure 17. AC Test Conditions, T A = 0 °C to 70 °C, VDD = 3.3 V ±10%
- C L = 50 pF for all output pins except the following pin group; this value includes both jig and oscilloscope capacitance.
CL = 100 pF for Serial Port pins.
- S 1 = Open for push-pull output pins.
S1 = VDD for high impedance to active low and active low to high impedance measurements. S1 = GND for high impedance to active high and active high to high impedance measurements. RL = 1.0 KΩ for all the pins.
- The following abbreviations are used in Section 7: RE = Rising Edge; FE = Falling Edge
7.4.2 Clock Input Timing
- Not tested; guaranteed by characterization.
- Not tested; guaranteed by design.
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7.4.3 V DD Power-Up Reset
Symbol Clock Input Parameters Reference Conditions CLKIN = 48 MHz UnitsMin Typ Max tCIH Clock High Pulse Width 1 1. Not tested; guaranteed by characterization. From VIH to V IH 6n s tCIL Clock Low Pulse Width 1 From VIL to V IL 6n s tCIP Clock Period1 20 20.83 21.5 ns FCIN Clock Frequency1 FCINTYP − 0.1% 48 (FCINTYP) FCINTYP + 0.1% MHz tCIR Clock Rise Time2 2. Not tested; guaranteed by design. From VIL to V IH 43 3. Recommended value. ns tCIF Clock Fall Time2 From VIH to V IL 43 ns Symbol Description Reference Conditions Min1 1. Not tested; guaranteed by design. Max1 tIRST Internal Power-Up reset time V DD power-up to end of internal reset t LRST tLRST LRESET active time VDD_GOOD 2 to end of LRESET 2. VDD_GOOD occurs either at the transition of PS_PWR_OK (a system signal not connected to the WPCN381U), if its threshold is ≥ 0.9 * VDD, or at the moment VDD power reaches 0.9 * VDD. 10 ms tIPLV Internal strap pull-up resistor, valid time3 3. Active only during VDD Power-Up reset. Before end of internal reset t IRST tEPLV External strap pull-up resistor, valid time Before end of internal reset t IRST tCIL tCIPtCIH VIHVIH VIL VIL VIH tCIF tCIR CLKIN Internal Straps tIPLV tEPLV (Pull-up) (Pull-Down) External Straps VDD (Power) (Internal) LRESET VDD Power-Up Reset tIRST VDDONmin tLRST VDD_GOOD PS_PWR_OK (External, not a device signal)
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7.4.4 LPC Interface Timing
Symbol Parameter Min Max Units tCYC 1. The PCI may have any clock frequency between 25 MHz and 33 MHz. The clock frequency may be changed at any time during the operation of the system as long as the clock edges remain “clean” (monotonic) and the minimum cycle, high and low times are not violated. The clock may only be stopped in a low state. LCLK Cycle Time 30 ns tHIGH LCLK High Time 2 2. Not tested; guaranteed by characterization. 11 ns tLOW LCLK Low Time 2 11 ns - LCLK Slew Rate3,4 3. Not tested; guaranteed by design. 4. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the minimum peak-to-peak portion of the clock waveform (0.2 * VDD to 0.6 * VDD), as shown below.
14 V / n s
- LRESET Slew Rate3,5 5. The minimum LRESET slew rate applies only to the rising (deassertion) edge of the reset signal; it ensures that system noise cannot render an otherwise monotonic signal to appear to bounce in the switching range. 50 mV/ns tWRST LRESET pulse width 100 ns Symbol Description Referen ce Conditions Min Max Unit tVAL Output Valid Delay After RE of LCLK 2 11 ns tON Float to Active Delay After RE of LCLK 2 ns tOFF Active to Float Delay After RE of LCLK 28 ns tSU Input Setup Time Before RE of LCLK 7 ns tHL Input Hold Time After RE of LCLK 0 ns tHIGH tLOW tCYC
0.6 VDD
0.2 VDD
0.5 VDD
0.4 VDD
0.3 VDD
0.4 VDD p-to-p
(minimum) LCLK
www.nuvoton.com 64 Revision 1.2 WPCN381U Leakage OnlyLeakage Only
0.285 VDD
0.615 VDD
0.4 VDD 0.4 VDDLCLK LAD3−LAD0, SERIRQ LDRQ, CLKRUN Outputs tVAL tON tOFF tVAL LAD3−LAD0, SERIRQ Output Enabled
0.4 VDDLCLK
LAD3−LAD0, LFRAME SERIRQ, CLKRUN Inputs tHLtSU
Revision 1.2 65 www.nuvoton.com WPCN381U
7.4.5 Serial Port, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol Parameter Conditions Min1 1. Not tested; guaranteed by design. Max1 Unit tBT Single Bit Time in Serial Port, Sharp-IR and Consumer Remote Control Transmitter tBTN − 25 2 2. tBTN is the nominal bit time in Serial Port, Sharp-IR, SIR and Consumer Remote Control modes. It is deter- mined by the setting of the Baud Generator Divisor registers. tBTN + 25 ns Receiver t BTN − 2% t BTN + 2% ns tCMW Modulation Signal Pulse Width in Sharp-IR and Consumer Remote Control Transmitter tCWN − 25 3 3. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is determined by MCPW field (bits 7-5) of IRTXMC register and TXHSC bit (bit 2) of RCCFG register. tCWN + 25 ns Receiver 500 ns tCMP Modulation Signal Period in Sharp-IR and Consumer Remote Control Transmitter tCPN − 25 4 4. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It is deter- mined by MCFR field (bits 4-0) of IRTXMC register and TXHSC bit (bit 2) of RCCFG register. tCPN + 25 ns Receiver tMMIN 5. tMMIN and tMMAX define the time range within which the period of the in-coming subcarrier signal must fall for the signal to be accepted by the receiver. These time values are determined by the contents of IRRXDC regis- ter and the setting of RXHSC bit (bit 5) of RCCFG register. tMMAX 5 ns tSPW SIR Signal Pulse Width Transmitter, Variable (3/16) x t BTN − 15 2 (3/16) x t BTN + 15 2 ns Transmitter, Fixed 1.48 1.78 µs Receiver 1 µs SDRT SIR Data Rate Tolerance. % of Nominal Data Rate. Transmitter ±0.87% Receiver ±2.0% tSJT SIR Leading Edge Jitter. % of Nominal Bit Duration. Transmitter ±2.5% Receiver ±6.5% Serial Port tCMW tCMP Sharp-IR Consumer Remote Control tBT SIR tSPW
7.4.6 MIR and FIR Timing
Figure 18. MIR and FIR Timing
7.4.7 Modem Control Timing
- Not tested; guaranteed by design.
- tMWN is the nominal pulse width for MIR mode. It is deter mined by M_PWID field (bits 4-0) in MIR_PW register
- Not tested; guaranteed by characterization.
- Not tested; guaranteed by design.
WPCN381U Legacy-Reduced SuperI/O with Fast Infrared Port, Two Serial Ports and GPIOs www.nuvoton.com Physical Dimensions All dimensions are in millimeters Important Notice Nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Furthermore, Nu- voton products are not intended for applications wherein failure of Nuvoton products could result or lead to a situation wherei n personal injury, death or severe property or environmental damage could occur. Nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nuvoton for any damages resulting from such improper use or sales. Please note that all data and specifications are subject to change without notice. All trademarks of products and companies mentioned in this document belong to their respective owners. Headquarters No. 4, Creation Rd. 3, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.nuvoton.com.tw/ Nuvoton Technology Corporation America
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