N572F072 NUVOTON | Alldatasheet
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Technical content
Release Date : Aug 2014 Revision 1.4 - 1 - N572F072/P072 Data Sheet 32-BIT MULTI-ALGORITHM VOICE PROCESSOR (NuVoice™)
Release Date: Aug 2014 Revision 1.4 - 2 - Table of Content
Release Date: Aug 2014 Revision 1.4 - 3 - 1. General Description The N572F072 is the enhanced NuVoice™ series from N572F065. NuVoice is the first SoC specific for voice applications based on Cortex™-M0 CPU. It runs up to 48MHz and equips with 72KB flash and 8KB SRAM for high performance process of audio and voice algorithms. Integrating rich analog peripherals, like pre-amplifier, ADC, DAC, hardware mixer, and PA, this chip saves a lot of system design effort and cost. To unfold the high performance M0 and high density of SRAM, advanced algorithms are designed, optimized, and tested with N572 chip s. These algorithms include voice changer , low-bit rate compression – NuOne; NuSound; NuLite; NuVox, beat detection, pitch in and pitch out, talk2sing, and more in developing. In additional to algorithms developed by Nuvoton, we als o seek thir d parties for more interesting features/software to enrich the applications on N572. With the NVIC in M0, the latency of interrupt and respo nse time to external eve nts is very short and efficient. Multiple algorithms can be run together smoothly and naturally. The development tools are based on Keil ™ MDK using C/C++ programming language. This is a rob ust and easy to use environment for software development and debug. Features in Keil ™ MDK are compiler, debugger, and profiler. With the Nu -Link™ and evaluation board, the overall system, including HW and SW, can work seamlessly in your system testing and verification. In this full -features development environment and tools, you can design and build application software in an efficient way and get optimized code that can best realize your idea on N572. Following is a brief table of all Part No. of NuVoice Series: Part No. N572F072 N572P072 N572F065 Program ROM 72KB Flash 64KB OTP + 8KB Flash 64KB Flash SRAM 8KB CPU freq 48MHz SPI Interface Master/Slave mode 12MHz, 1 set Master mode 24MHz (3.3V), 1 set Master mode 12MHz, 2 sets USB N/A N/A FS/12Mbps 2. Features Core – ARM® Cortex™-M0 core runs up to 48MHz – Support low power sleep mode – Single-cycle 32-bit hardware multiplier – NVIC for the 16 interrupt inputs, each with 4-level of priority – 24-bit SysTick timer – Serial Wire Debug supports with 2 watchpoints/4 breakpoints Widely operating voltage range from 2.4V to 5.5V Flash Memory – 72KB Flash (for N572F072) – 64KB OTP and 8KB Flash (for N572P072) – Support ISP for Flash update – 512 bytes page erase for Flash – Support 2-wire ICP update from ICE interface
Release Date: Aug 2014 Revision 1.4 - 4 - – Security Lock preventing content in Flash access from external interface SRAM Memory – 8KB embedded SRAM Clock Control – Flexible selection for different applications – Support PLL, up to 48MHz, for high performance system operation – External 32KHz crystal input for RTC function and system clock – Internal 48MHz RC oscillator GPIO – Four I/O modes: Quasi bi-direction Push-Pull output Open-Drain output Input only with high impendence – TTL/Schmitt trigger input selectable – I/O pin can be configured as interrupt source with edge/level setting Timers – 3 sets of the timer with 8-bit pre-scaler and 16-bit timer. – Counter auto reload. – IR carrier generator – One fixed frequency timer Watch Dog Timer – Default ON/OFF by configuration setting – Multiple clock sources – 8 selectable time out period from around 32ms ~ 8sec (based on 32768Hz clock) – Able to wake up power down/sleep – Interrupt or reset selectable on watchdog time-out RTC – Support time out interrupt – Support wake up function PWM Timer – One 16-bit timer and four 16-bit comparators – Five clock selectors – One 8-bit pre-scaler and one clock divider – Two Dead-Zone generators – Programmable duty control of output waveform – Auto reload mode or one-shot pulse mode – Capture function SPI – Two sets of SPI device – Master mode up to 24MHz (3.3V) – Support master/slave mode – Full duplex synchronous serial data transfer – Variable length of transfer data from 1 to 32 bits – MSB or LSB first data transfer – Rx and Tx on both rising or falling edge of serial clock independently – 2 slave/device select lines
Release Date: Aug 2014 Revision 1.4 - 5 - – Two 32-bit buffers ADC – 8-ch 12-bit with 320Ksps – Single scan/single cycle scan/continuous scan – 8 channels share 8 result registers – Programmable channel scan sequence – Threshold voltage detection – Conversion start by S/W or an external pin – Programmable gain control for sound record – Internal microphone bias APU – 13-bit DAC – H/W mixer with 2 channel PCM inputs – Embedded power amplifier – 7-level volume control Voltage Detector – with 2 levels: 3.0V/2.7V LDO – Built-in 1.8V LDO Voltage Output – Built-in 3V regulator power supply Voutx for driving external spi-flash Low Voltage Reset 1.8V Operating Temperature: 0℃~70℃ Packages: – All Green package (RoHS) – 7mmx7mm LQFP 64-pin or COB 3. Application Fields Recordable story books Karaoke musical player Toy masks with voice change Voice recognition toys Interactive toys on learning of music, languages Toy robots
Release Date: Aug 2014 Revision 1.4 - 6 - 4. Functional Block Diagram 72KB Flash or 64KB OTP + 8KB Flash Cortex-M0 48MHz Clock Control AHB SRAM 8KB APB Bridge GPIO A/B RTC WDT APB APU PWM Timer Timer 0/1/2/F Ext. 32K Xtal P L L 48M RC OSC LDO 1.8V 12-bit ADC POR VD LVR SPI 0/1 13-bit DAC Power Amplifier Voutx (LDO 3.0V) PGC Mic Bias
Release Date: Aug 2014 Revision 1.4 - 7 - 5. Pin Configuration
5.1 Pin Diagram
ICE_CLK VMID AVSS1 ICE_DAT RSTB PLLC GPA5/TM0 VSSIO2 VDDIO2 MIC_BIAS REGVREF X32I X32O GPA6/INT0 AVSS0 NC AVDDC GPA7/STADC PGCVREF GPB5 GPB9/PWM1 GPB12/CPR0 LDO18 GPB10/PWM2 GPB11/PWM3 GPB7 GPB8/PWM0 GPB6 VSSIO4 VDDIO4 Voutx GPB13/IROUT GPB15/TM2 GPB14/TM1 SPKVSS049 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 GPA9/ADC1 GPA10/ADC2 GPA11/ADC3 GPA12/ADC4 GPA13/ADC5 GPA14/ADC6 GPA15/ADC7 GPA4/MOSI0 GPA3/MISO0 GPA2/SPCK0 GPA1/SSB00 GPA0/SSB01 GPB4/MOSI1 GPB3/MISO1 GPB2/SPCK1 GPB1/SSB10 GPB0/SSB11 NC AVDD ADCVREF VSSIO1
Release Date: Aug 2014 Revision 1.4 - 8 -
5.2 Pad Description
- GPIO GPA0 ~ GPA15 I/O Bidirectional general purpose I/O ports. Most of these pins have alternate function, refer to section 5.3 for detail. GPB0 ~ GPB15 I/O Bidirectional general purpose I/O ports. Most of these pins have alternate function, refer to section 5.3 for detail. 2. Oscillator X32I I 32KHz crystal input X32O O 32KHz crystal output PLLC A Capacitor connection for built-in PLL1 3. PGC and ADC AVDD P Analog power supply AVSS0 P Analog ground AVSS1 P Analog ground ADCVREF A Reference voltage input for ADC MIC_BIAS A Microphone bias output AVDDC A Regulator output pin for ADC and PGC, its output voltage is 0.85xAVDD. Connect an external 4.7uF capacitor to AVSS. PGCVREF A AVDDC/2 for PGC. A 4.7uF (or higher) capacitor for low pass filter to filter power noise is needed. REGVREF A AVDD/2 for microphone output. A 4.7uF (or higher) capacitor for low pass filter to filter power noise is needed. 4. Speaker Driver DAC/SPK+ O Speaker positive output pin, or current type DAC output. SPK- O Speaker negative output pin. SPKVDD P Analog power supply SPKVSS1 P Analog ground. SPKVSS0 P Analog ground. VMID A Connect a capacitor to SPKVSS1 5. Power VDDIO4 P Power supply for I/O port, LVR, LVD and source of LDO.
Release Date: Aug 2014 Revision 1.4 - 9 - VSSIO4 P Ground pin, connect to 0V. VDDIO2 P Power supply for I/O port, SWD, and RSTB VSSIO2 P Ground pin, connect to 0V. VDDIO1 P Power supply for I/O port. VSSIO1 P Ground pin, connect to 0V. VDDIO3 P Power supply for I/O port. VSSIO3 P Ground pin, connect to 0V. LDO18 P 1.8V LDO output Voutx P 3.0V regulator output for driving external 6. SWD ICE_CLK I Serial Wired Debugger Clock pin ICE_DAT I/O Serial Wired Debugger Data pin 7. Other RSTB I Reset input pin, low active. Internal pull-high.
Release Date: Aug 2014 Revision 1.4 - 10 -
5.3 Alternate Function List of GPIO
GPIO Power Alternate I/O of Alternate Function Description GPA0 VDDIO1 SSB01 O SPI0 2nd chip select pin GPA1 VDDIO1 SSB00 O SPI0 1st chip select pin GPA2 VDDIO1 SPCK0 O SPI0 serial clock output GPA3 VDDIO1 MISO0 I SPI0 master data input GPA4 VDDIO1 MOSI0 O SPI0 master data output GPA5 VDDIO2 TM0 I Timer0 counter external clock input GPA6 VDDIO2 INT0 I External interrupt input pin GPA7 VDDIO2 STADC I ADC external trigger input GPA8 AVDD ADC0 A ADC analog input 0 GPA9 AVDD ADC1 A ADC analog input 1 GPA10 AVDD ADC2 A ADC analog input 2 GPA11 AVDD ADC3 A ADC analog input 3 GPA12 AVDD ADC4 A ADC analog input 4 GPA13 AVDD ADC5 A ADC analog input 5 GPA14 AVDD ADC6 A ADC analog input 6 GPA15 AVDD ADC7 A ADC analog input 7 GPB0 VDDIO3 SSB11 O SPI1 2nd chip select output pin GPB1 VDDIO3 SSB10 I/O SPI1 1st chip select output/input pin GPB2 VDDIO3 SPCK1 I/O SPI1 serial clock output/input GPB3 VDDIO3 MISO1 I/O SPI1 master data input, slave data output GPB4 VDDIO3 MOSI1 I/O SPI1 master data output, slave data input GPB5 VDDIO4 - GPB6 VDDIO4 - GPB7 VDDIO4 - GPB8 VDDIO4 PWM0 O PWM output pin 0 GPB9 VDDIO4 PWM1 O PWM output pin 1
Release Date: Aug 2014 Revision 1.4 - 11 - GPB10 VDDIO4 PWM2 O PWM output pin 2 GPB11 VDDIO4 PWM3 O PWM output pin 3 GPB12 VDDIO4 CPR0 I Capture input GPB13 VDDIO4 IROUT O IR carrier output GPB14 VDDIO4 TM1 I Timer1 counter external clock input GPB15 VDDIO4 TM2 I Timer2 counter external clock input I: Input, O: Output, A: Analog input
Release Date: Aug 2014 Revision 1.4 - 12 - 6. Typical Application Circuit
6.1 Recording and Playback
Release Date: Aug 2014 Revision 1.4 - 13 -
6.2 Dual Microphones for Sound Direction Detection and Motor Control
Release Date: Aug 2014 Revision 1.4 - 14 - 7. Software and Development Environment
7.1 Development Environment
The Keil ™ MDK includes IDE, compiler, linker, and debugger is for your software development. Debug hardware requires Nu-Link™ and N572 EVB. A Nu-Link driver is required to add views of peripherals and add-ons within MDK’s IDE. With software library, you can develop and debug in the MDK environment. Please refer to Programming Guide for details. Nu-Link N572-EVB Keil IDE Nu-Link Drivers N572 SDS Drivers Libraries Sample Projects Algorithms
Release Date: Aug 2014 Revision 1.4 - 15 -
7.2 Library and Document Guide
N572 SDS is for N572F072/P072/ F065 which provides a bunch of sample codes, libraries, document, and EVB schematic for your reference. To get familiar with the whole development environment, ple ase install Keil then this SDS. There will be a N572 SDS Document Index under N572 SDS Vxxx from Start menu to show all the useful information. Even better is the links to directly open Keil and load sample projects in a click! The algorithms are collected in library. Demo Sample is also a good place for user to understand the capability of NuVoice™.
Release Date: Aug 2014 Revision 1.4 - 16 -
7.3 Supported Codec
Following table shows the supported codec and suggested sample rate and corresponding bit rate. The Bit Rate of NuOne, NuLite, and NuSound could be configurable. For example, using 8K sample rate, the bit rate could be 8Kbps (1bit per sample) or 12Kbps (1.5 bit per sample) or 16Kbps (2 bit per sample). Details please refer to document in SDS. Codec Sample Rate (Hz) *note1 Bit Rate (bps) For Availability NuOne 8K~20K 8K ~ 20 K @1b/sample *note2 Speech, Music Codec NuLite 8K~12K 9.6K ~ 14.4 K @1.2b/sample *note2 Speech, Music Codec NuSound 8K~20K 16K~40K @2b/sample *note3 Speech, Music Decoder MD4 8K~20K 32K~80K Speech, Music Decoder IMAADPCM 8K~20K 32K~80K Speech, Music Codec LP8 8K~20K 64K~160K Speech, Music Codec NuVox24 8K 2.4K Speech Decoder NuVox53/63 8K 5.3K/6.3K Speech Decoder *note1: suggested sampling rate *note2: bits per sample range from 0.5b/sample ~ 3b/sample, with 0.1b/sample incremental step *note3: bits per sample range from 1.5b/sample ~ 3b/sample, with 0.1b/sample incremental step
Release Date: Aug 2014 Revision 1.4 - 17 - 8. Electrical Characteristics
8.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT DC Power Supply VDDVSS -0.3 +7.0 V Input Voltage VIN VSS-0.3 VDD+0.3 V Oscillator Frequency 1/tCLCL 0 48 MHz Operating Temperature TA 0 +70 C Storage Temperature TST -55 +150 C Maximum Current into VDD - 120 mA Maximum Current out of VSS 120 mA Maximum Current sunk by a n I/O pin 35 mA Maximum Current sourced by a n I/O pin 35 mA Maximum Current sunk by total I/O pins 100 mA Maximum Current sourced by total I/O pins 100 mA
8.2 DC Electrical Characteristics
VDD-VSS=4.5V, TA=25°C, unless otherwise specified. PARAMETER SYM SPECIFICATION TEST CONDITIONS MIN. TYP. MAX. UNIT Operation voltage VDD 2.4 5.5 V Power Ground VSS AVSS -0.3 V Analog Operating Voltage AVDD 0 VDD V Analog Reference Voltage Vref 0 AVDD V Operating Current at Normal Run Mode IDD1 20 mA VDD=5.5V@48MHz, enable all IPs’ clock IDD3 18 mA VDD=3V@48MHz, enable all IPs’ clock Operating Current at Idle Mode IIDLE2 3 mA VDD=5.5V@48MHz, disable all IPs IIDLE4 3 mA VDD=3V@48MHz, disable all IPs Operating Current at Power-down Mode IPWD1 10 15 A VDD = 5.5V, No load, disable Voutx, LVD, LVR, … IPWD2 9 15 A VDD = 3.3V, No load, disable Voutx,
Release Date: Aug 2014 Revision 1.4 - 18 - LVD, LVR, … Input Current GPA/GPB IIN1 -60 - +15 A VDD = 5.5V, VIN = 0V or VIN=VDD Input Current at RSTB [1] IIN2 -160 -130 -100 A VDD = 5.5V, VIN = 0.45V Input Leakage Current GPA/GPB ILK -0.1 - +0.1 A VDD = 5.5V, 0<VIN<VDD Input Low Voltage GPIO (TTL input) VIL1 -0.3 - 1.0 V VDD = 4.5V Input High Voltage GPIO (TTL input) VIH1 2.2 - VDD +0.2 V VDD = 5.5V 1.5 - VDD +0.2 VDD = 3.0V Source Current GPA/GPB (Quasi-bidirectional Mode) ISR11 -300 -370 -450 VDD = 4.5V, VS = 2.4V ISR12 -50 -70 -90 VDD = 2.7V, VS = 2.2V ISR13 -40 -60 -80 VDD = 2.5V, VS = 2.0V Source Current GPA/GPB (Push-pull Mode) ISR21 -20 -24 -28 mA VDD = 4.5V, VS = 3.0V ISR22 -4 -6 -8 VDD = 2.7V, VS = 2.2V ISR23 -3 -5 -7 VDD = 2.5V, VS = 2.0V Sink Current GPA/GPB (Quasi-bidirectional and Push-pull Mode) ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V ISK2 7 10 13 VDD = 2.7V, VS = 0.45V ISK3 6 9 12 VDD = 2.5V, VS = 0.45V Notes: 1. RSTB pin is a Schmitt trigger input.
Release Date: Aug 2014 Revision 1.4 - 19 -
8.3 AC Electrical Characteristics
The following data are measured under VDD-VSS=4.5V, TA=25°C, unless otherwise specified.
8.3.1 Internal 48MHz RC Oscillator
PARAMETER CONDITION MIN. TYP. MAX. UNIT Center Frequency 48.24 MHz Calibrated Internal Oscillator Frequency +25C -1 +1 % Operating current VDD=1.8V 900 uA
8.4 Analog Characteristics
The following data are measured under VDD-VSS=4.5V, TA=25°C, unless otherwise specified. 8.4.1 12-bit SAR ADC PARAMETER SYM. MIN. TYP. MAX. UNIT Resolution - - - 12 Bit Differential nonlinearity error DNL - ±1 - LSB Integral nonlinearity error INL - ±1 - LSB Offset error EO - ±1 - LSB Gain error (Transfer gain) EG - 1 - - Monotonic - Guaranteed - ADC clock frequency FADC - - 8 MHz Sample & Conversion time TADC - 25 - Clock Sample rate FS - - 320 Ksps Supply voltage VDD - 1.8 - V VDDA 3 - 5.5 V Supply current (Avg.) IDD - 0.5 - mA IDDA - 1.5 - mA Reference voltage VREFP - VDDA - V
8.4.2 Voice Recorder
Parameter Sym. Condition Min. Typ. Max. Unit Operation Voltage VDDA 3 5 5.5 V
Release Date: Aug 2014 Revision 1.4 - 20 - Operation Current IDD 3.5 mA Programmable Gain PG 0 30 dB Preamp Gain PAG 20 40 dB Offset Bit OS 9-bit Control -64 64 mV THD+N THD+N Preamp Gain=40dB, Programmable Gain=0dB -55 dB 8.4.3 1.8V LDO for Internal Core Parameter Condition MIN. TYP. MAX. Unit Input Voltage 2.4 5 5.5 V Output Voltage -- 1.8 -- V 8.4.4 Voutx (3.0V LDO) for External Driving Parameter Condition Min. Typ. Max. Unit Input Voltage 3.3 5 5.5 V Output Voltage -10% 3.0 +10% V Turn off floating - V Iload 40 mA
8.4.5 Low Voltage Reset
PARAMETER CONDITION MIN. TYP. MAX. UNIT Threshold voltage Temperature=25C 1.6 1.8 2.0 V
8.4.6 Voltage Detector
PARAMETER CONDITION MIN. TYP. MAX. UNIT Detected Voltage CVDTV=0 2.7 V CVDTV=1 3.0 V
8.4.7 Power Amplifier and DAC
PARAMETER CONDITION MIN. TYP. MAX. UNIT Operation voltage SPKVDD 2.4 4.5 5.5 V Output Power SPKVDD=4.5V, 8Ω BTL load, 0dB gain 400 mW
Release Date: Aug 2014 Revision 1.4 - 21 - Total Harmonic Distortion SPKVDD=4.5V, 8Ω BTL load, 0dB gain, 400mW -48 dB Power Amplifier Gain -18 0 dB DAC output current DACGN=0 2.4 3 3.6 mA DACGN=1 4.0 5.0 6.0 DAC operation Current SPKVDD=4.5V 4 mA DAC Quiescent Current SPKVDD=4.5V 200 A Power Amplifier Quiescent Current DAC fine-tuned, SPKVDD=4.5V 6 mA Power Down Current DAC fine-tuned, SPKVDD=4.5V 1 A Operation Current SPKVDD=4.5V, 400mW 250 mA
8.4.8 PLL
PARAMETER SYMBOL CONDITION MIN. TYP. MAX. UNIT Operating Voltage Range VDD -- 1.8 -- V Temperature 0 25 70 C Input Clock Frequency Fin -- 32.768 -- KHz Output Clock Frequency Fout -- 48 -- MHz Duty Cycle -- Fout=48MHz 40 50 60 % Operating Current Iop 25C 3 mA
Release Date: Aug 2014 Revision 1.4 - 22 - 9. Package Information 64L LQFP(7x7x1.4mm footprint 2.0mm)
Release Date: Aug 2014 Revision 1.4 - 23 - 10. Ordering Information 11. Revision History VERSION DATE DESCRIPTIONS
1.0 Oct, 2011 Preliminary draft
1.1 May, 2012 Review to make official release
1.2 Nov, 2012 Add codec table
Add section of Application Fields Keep only 64KB OTP+ 8KB Flash for N572P072
1.3 Aug, 2013 Update Operating Temperature as 0℃~70℃
Update application circuit Remove supply voltage VDD & un-calibrated part in 8.3.1 table Update minimum input spec of SPKVDD & 1.8V LDO to 2.4V. 1.4 Aug, 2014 Update Internal RC 48MHz Center Frequency as 48.24MHz (typical) Update Calibrated Internal Oscillator Frequency as ±1% Correct Voice Recorder THD+N as -55dB (typical) PART NUMBER PACKAGE SPECIAL FEATURE PB FREE + HALOGEN FREE (GREEN) RELEASE DATE N572F072 NA (Die Form) MTP Yes Available N572F072G LQFP 64pin 7mmx7mm MTP Yes Available N572P072 NA (Die Form) OTP + MTP Yes Available N572P072G LQFP 64pin 7mmx7mm OTP + MTP Yes Available
Release Date: Aug 2014 Revision 1.4 - 24 - Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk , and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.