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16M-BIT Low Voltage, Serial MASK ROM with 50MHz SPI Bus Interface P/N: PM1437 REV. 1.1, MAR., 2010 GENERAL DESCRIPTION The N55S016 is a 16Mbit (2M Bytes) Serial Mask ROM accessed by a high speed Serial peripheral interface . KEY FEATURES
- Operating voltage ranges from 3.0V to 3.6V
- Serial Peripheral Interface compatible-mode 0 and 3
- High performance: "fast read" mode at 50MHz and "normal read" at 20MHz
- Low power consumption: 8mA for fast read mode or 4mA for normal read mode
- Low standby current: 15uA PIN DESCRIPTION SYMBOL DESCRIPTION SCLK Serial Clock SI Serial Data Input SO Serial Data Output CSB Chip Select HOLDB Hold to pause the device without deselecting the device VCC Power Supply VSS Ground ORDER INFORMATION Part No. Speed Grade N55S016 20ns Commercial
7 VSS1
8 VSS2
10 SCLK
1 HOLDB
2 VCC1
3 VCC2
4 CSB
FIGURE 1. DIE PAD
- The IC substrate should be connected to VSS in PCB layout.
P/N: PM1437 REV. 1.1, MAR., 2010 TABLE 1. PAD
DESCRIPTION
ORDER PAD-NAME X-COORD Y-COORD 1 HOLDB -1920.09 -1348.72 2 VCC1 -1649.20 -1348.71 3 VCC2 -1431.48 -1348.71 4 CSB 354.43 -1348.71 5 SO 797.48 -1348.71 6 NC 1865.85 1350.00 7 VSS1 1597.71 1350.15 8 VSS2 1380.07 1350.15 9 SI -1609.25 1350.00 10 SCLK -1848.82 1349.99
P/N: PM1437 REV. 1.1, MAR., 2010 X-Decoder MEMORY ORGANIZATION The memory is organized as: - 2M bytes BLOCK DIAGRAM Address Generator Memory Array SI Data Regist er Y-Decoder CS# HOLD Mode Logic State Machine Sense Amplifier Output Buffer SO SCLK Clock Generator
until next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of SPI mode 0 and mode 3 is shown as Figure 1. Figure 1. SPI Modes Supported
0 SCLK
1 SCLK
which SPI mode is supported.
HOLD# pin signal goes low to hold any serial communications with the device. be low, HOLD operation will not end until Serial Clock being low), Please refer to Figure 2. Figure 2. Hold Condition Operation
Table 1. COMMAND
- n bytes are read out until CS# goes high.
- It is not recommended to adopt any code not in the above command definition table.
P/N: PM1437 REV. 1.1, MAR., 2010 COMMAND DESCRIPTION (1) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and is followed by Device ID of 2-byte. The nuvoTon Manufacturer ID is C2h, the memory type ID is 05h as the first-byte device ID, and the individual device ID of sec- ond-byte ID is:15h. The sequence of issuing RDID instruction is: CS# goes low-> sending RDID instruction code -> 24-bits ID data is sent out on SO -> to end RDID operation which can use CS# to be high at any time during data out. (see Figure 3) When CS# goes high, the device is at standby stage. Table of ID Definitions: RDID manufacturer ID memory type memory density 9Fh C2h 05h 15h (2) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address is sent on SI -> data out on SO-> to end READ operation which can use CS# to be high at any time during data out. (see Figure 4) (3) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low-> send FAST_READ instruction code-> 3-byte address is sent on SI-> 1-dummy byte address is sent on SI->data out on SO-> to end FAST_READ operation which can use CS# to be high at any time during data out. (see Figure 5) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im- pact on the Program/Erase/Write Status Register current cycle.
Figure 5. Read at Higher Speed (FAST_READ) Sequence (Command 0B)
24 BIT ADDRESS
P/N: PM1437 REV. 1.1, MAR., 2010 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Commercial grade 0C to 70C Storage Temperature -65C to 150C Applied Input Voltage -0.6V to 4.0V Applied Output Voltage -0.6V to 4.0V VCC to Ground Potential -0.6V to 4.0V NOTICE: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage of the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions in long period of time may a ffect reliability. 2. Specifications contained within the following Table 2 and 3 are subjects to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see Figure 6,7. F i g u r e 6 . M a x i m u m N e g a t i v e O v e r s h o o t Waveform F i g u r e 7 . M a x i m u m P o s i t i v e O v e r s h o o t Waveform V ss Vss - 2.0V 20ns 20ns 20ns Vcc + 2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25C, f = 20 MHz SYMBOL PARAMETER MIN. TYP MAX. UNIT CONDITIONS CIN Input Capacitance 6 pF VIN = 0V COUT Output Capacitance 8 pF VOUT = 0V
Table 2. DC CHARACTERISTICS ( Temperature = 0C to 70C, VCC = 3.0V ~ 3.6V)
Table 3. AC CHARACTERISTICS ( Temperature = 0C to 70C, VCC = 3.0V ~ 3.6V) (1). tCH + tCL must be greater than or equal to 1/ fC. production. (3). Indicated as a slew rate.
P/N: PM1437 REV. 1.1, MAR., 2010 Figure 12. Hold
- SI is "don't care" during HOLD operation.
Revision History
Version Date Substantial Changes Page A1.0 Oct. 2008 Initial Release All A1.1 Mar. 2010
P/N: PM1437 REV. 1.1, MAR., 2010 Important Notice Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usag e includes, but is not limited to: equipment for surgical implementation, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instrume nts, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, custome r shall indemnify the damages and liabilities thus incurred by Nuvoton.