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Release Date: Mar. 2017 - 1 - Version A2.1 8 ~ 24 I/O EXPANDER WITH 256-lEVEL PWM OUTPUT N55Pxxx Data Sheet The information described in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of Peripheral based system design. Nuvoton assumes no responsibility for errors or omissions. All data and specifications are subject to change without notice. For additional information or questions, please contact: Nuvoton Technology Corporation. www.nuvoton.com
Release Date: Mar. 2017 - 2 - Version A2.1 Table of Contents
Release Date: Mar. 2017 - 3 - Version A2.1 1. General Description The N55Pxxx series is a general purpose program mable I/O device usable with different microprocessors through SPI interface. The N55Pxxx contains up to three 8 -bit ports (BPA, BPB and BPC). There are 8~24 I/O pins which may be individually programmed for 6 separate command groups. The N55Pxxx features logical operating capability AND/OR/XOR for each bit of internal configuration register to speed up access . These GPIO pads can drive LED directly with 256 levels of brightness. The N55Pxxx series contains following bodies with different GPIO pins: Part No. GPIO I/O port N55P082 8 pads BPB N55P162 16 pads BPA, BPB N55P242 24 pads BPA, BPB, BPC 2. Features Wide range of operating voltage: 2.0 ~ 5.5V SPI interface in mode 0 4 SPI pins for communication CSB as chip select pin (low active) SCK for data synchronization (up to 8MHz) MOSI for N55Pxxx to receive commands and data MISO for the microcontroller to receive data 1 wakeup pad for the microcontroller 8~24 I/O pads Bi-directional I/O pads o N55P082: 8 I/O pads o N55P162: 16 I/O pads o N55P242: 24 I/O pads Status of each pad is independently controlled o Input Floating Pull high Pull low Dynamic pull low
Release Date: Mar. 2017 - 4 - Version A2.1 Dynamic pull high o Output CMOS high/low Inverted CMOS high/low Inverted open-drain NMOS output Open-drain PMOS output Constant sink current output Any pad can be selected for wakeup to work Speed up (AND/OR/XOR) groups to minimize load of MCU PWM I/O 256 levels output Internal ring oscillator @ 8 MHz 4 clock sources Reset management Power-on reset S/W reset Standby current <1uA Connection of up to 2 N55Pxxx devices
Release Date: Mar. 2017 - 5 - Version A2.1 3. Pad Description Pad Name Type Power Supply Description BPA0 ~ BPA7 IO VDDIOA General-purpose IO, BPA port. BPB0 ~ BPB7 IO VDDIOB General-purpose IO, BPB port. BPC0 ~ BPC7 IO VDDIOC General-purpose IO, BPC port. RJPA I VDDIOA RJPA is connected to an external resistor to set the constant current of BPA port. It can be NC if constant current is not enabled. RJPB I VDDIOB RJPB is connected to an external resistor to set the constant current of BPB port. It can be NC if constant current is not enabled. RJPC I VDDIOC RJPC is connected to an external resistor to set the constant current of BPC port. It can be NC if constant current is not enabled. CSB I VDDSPI SPI chip select (low active) SCK I VDDSPI SPI clock MOSI I VDDSPI SPI data input MISO O VDDSPI SPI data output (clock output if TEST bit is “1”) DEVICE I VDDSPI Device ID (floating) WAKEUP O VDDSPI Host wakeup VDD P Positive power supply for core logic VDDSPI P Positive power supply for SPI pads VSS P Negative power supply for core logic and SPI pads VDDIOA P Positive power supply for BPA port VSSIOA P Negative power supply for BPA port VDDIOB P Positive power supply for BPB port VSSIOB P Negative power supply for BPB port VDDIOC P Positive power supply for BPC port VSSIOC P Negative power supply for BPC port
Release Date: Mar. 2017 - 6 - Version A2.1 4. Block Diagram CSB SCK MOSI MISO SPI PORTA (PWM) BPADEVICE WAKEUP PORTB (PWM) BPB PORTC (PWM) BPC RJPA RJPB RJPC
Release Date: Mar. 2017 - 7 - Version A2.1 5. Electrical Characteristics
5.1 Absolute Maximum Ratings
Parameter Symbol Conditions Rated Value Unit Power Supply VDDVSS - -0.3 to +7.0 V Input Voltage VIN All Inputs VSS -0.3 to VDD +0.3 V Storage Temp. TSTG - -55 to +150 C Operating Temp. TOPR - 0 to +70 C Total Max. IO Current IM - -200/200 mA Note: Exposure to conditions beyond those listed under the Absolute Maximum Ratings table may adversely affect the life and reliability of the device.
5.2 DC Characteristics
(VDD VSS = 4.5V, TA = 25 C, No Load unless otherwise specified) Parameter Sym. Conditions Min. Typ. Max. Unit Operating Voltage VDD 2.0 - 5.5 V Operating Current IOP1 VDD=5.5V, CLK @8MHz - 800 A Standby Current (STOP) IDD1 VDD=5.5V, CSB=VDD - - 1 A Input Low Voltage VIL VDD=4.5V VSS - 0.3 VDD V Input High Voltage VIH VDD=4.5V 0.7 VDD - VDD V Input Pull-High Resistor RPH VDD=3.0V 360 450 540 K Input Pull-Low Resistor RPL VDD=3.0V 360 450 540 K Output Current IOL VDD = 3V, VOUT = 0.4V 8 - - mA IOH VDD = 3V, VOUT = 2.6V -4 - - mA Constant Output Low Current IOLC VOUT= 1.0V, RJPx = 82K VOUT= 1.0V, RJPx = 220K 13 mA Constant Current Dev. by Voltage Drop I/I VDD = 2.6~4.5V RJPx = 82K 10 15 %
Release Date: Mar. 2017 - 8 - Version A2.1
5.3 AC Characteristics
(VDD – VSS = 3.0V, TA = 25C ; unless otherwise specified) Parameter Sym. Conditions Min. Typ. Max. Unit SCK Clock Frequency fCLK - - 8 MHz Input Rise Time tR - - 5 nS Input Fall Time tF - - 5 nS SCK High Time tWH 58 - - nS SCK Low Time tWL 58 - - nS CSB High Time tCS 100 - - nS CSB Setup Time tCSS 50 - - nS CSB Hold Time tCSH 50 - - nS Data in Setup Time tSU 5 - - nS Data in Hold Time tH 5 - - nS Output Valid Time tV - - 50 nS Output Hold Time tHO 0 - - nS Output Disable Time tDIS - - 100 nS Output Disable Time tDIS - - 100 nS
Release Date: Mar. 2017 - 9 - Version A2.1 SPI Timing CSB CLK MOSI Valid data data tCS tCSH tDIStHOtV HZ tCSS tWH tWL tSU tH
Release Date: Mar. 2017 - 10 - Version A2.1 6. Reference Application Circuit Disable Constant Current Enable Constant Current
Release Date: Mar. 2017 - 11 - Version A2.1 2 x N55Pxxx Cascade
Release Date: Mar. 2017 - 12 - Version A2.1 7. Package Information
Release Date: Mar. 2017 - 13 - Version A2.1
Release Date: Mar. 2017 - 14 - Version A2.1
Release Date: Mar. 2017 - 15 - Version A2.1
Release Date: Mar. 2017 - 16 - Version A2.1
Release Date: Mar. 2017 - 17 - Version A2.1 8. Ordering Information Part No. Shape Type Remark N55P242 H Die Form 24 I/O N55P162 H Die Form 16 I/O N55P082 H Die Form 8 I/O
Release Date: Mar. 2017 - 18 - Version A2.1 9. Revision History Version Date Substantial Changes Page A1.0 Oct. 2016 Initial Release All A2.0 Jan. 2017 Revise SCK Clock Frequency AC spec Add Package Information 12~16 A2.1 Mar. 2017 Update Constant current deviation DC spec 7 Important Notice Nuvoton Products are neither intended nor warranted for usage in sys tems or equipment, any malfunction or failure of which may cause loss of human life, bodily injury or severe property damage. Such applications are deemed, “Insecure Usage”. Insecure usage includes, but is not limited to: equipment for surgical implementa tion, atomic energy control instruments, airplane or spaceship instruments, the control or operation of dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all types of safety devices, and other applications intended to support or sustain life. All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the damages and liabilities thus incurred by Nuvoton.