N40P112 AMSCO | Alldatasheet
Document overview
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- PDF pages: 34
Technical content
Datasheet sections
- 1 General Description
- 2 Key Features
- 3 Applications
- 4 Benefits
- 5 Pin Assignments
- 5.1 Pin Descriptions
- 6 Absolute Maximum Ratings
- 7 Electrical Characteristics
- 7.1 Operating Conditions
- 7.2 Digital IO Pads DC/AC Characteristics
- 7.3 Switch Characteristics
- 7.4 Mechanical Specifications
- 7.5 Recommended Reflow Temperature Profile
- 8 Using the N40P112 Module
- 8.1 Powering up the Module
- 8.2 Registers Initialization
- 8.3 C Source Code Example
- 8.3.1 Initialization
- 8.3.2 Offset Calibration
- 8.3.3 Dead Zone area
- 8.3.4 Interrupt Routine
- 9 XY Coordinates Interpretation
- 9.1 EasyPoint Operating Principle
- 9.1.1 Knob Displacement and Register Value Relation
- 9.2 Operation Principle
- 10 I²C interface
- 10.1 Interface Operation
- 10.2 I²C Electrical Specification
- 10.3 I²C Timing
- 10.4 I²C Modes
- 10.4.1 Automatic Increment of Address Pointer
- 10.4.2 Invalid Addresses
- 10.4.3 Reading
- 10.4.4 Writing
- 10.4.5 High Speed Mode
- 10.4.6 Automatic Increment of Address Pointer
- 10.4.7 Invalid Addresses
- 10.5 SDA, SCL Input Filters
- 11 I²C Registers
- 11.1 Control Register 1 (0Fh)
- 11.2 X Register (10h)
- 11.3 Y_res_int Register (11h)
- 11.4 Xp Register (12h)
- 11.5 Xn Register (13h)
1 General Description
built in the module provides a “select” function. Figure 1. N40P112-xxxxx-H
2 Key Features
3 Applications
4 B e n e f i t s
Figure 2. Typical Application Diagram
www.austriamicrosystems.com/N40P112 Revision 1.1 3 - 34
5 Pin Assignments
Figure 3. N40P112-xxxxx-H Schematics
5.1 Pin Descriptions
Table 1. Pin Descriptions
3 Power GND
4 Bi-directional SDA: I²C bus data, open drain
5 Input SCL: I²C bus clock
6 Input
7 Open drain
8 Output
9 Input
6 Absolute Maximum Ratings
maximum rating conditions for extended periods may affect device reliability. Table 2. Absolute Maximum Ratings
7 Electrical Characteristics
7.1 Operating Conditions
7.2 Digital IO Pads DC/AC Characteristics
Table 3. Operating Conditions
10 TAMB = 50 to +70 ºC
Table 4. Digital IO Pads DC/AC Characteristics
7.3 Switch Characteristics
Table 5. Switch Characteristics Bouncing (On/Off) 5 ms Rate: 2 times/sec.
7.4 Mechanical Specifications
7.5 Recommended Reflow Temperature Profile
Figure 4. Reflow T emperature Profile Table 6. Mechanical Specifications to concrete surface, module is assembled to phone mechanics.
8 Using the N40P112 Module
8.1 Powering up the Module
internal reset is completed, the POR cell is disabled in order to save current during normal operation. Figure 5. Power-up Sequence
8.2 Registers Initialization
- VDD and VDDp Power up, and reached their nominal values (VDD>2.7V, VDDp>1.7V).
- Perform an Offset Calibration (X and Y coordinate compensation for zero position)
- Configure the Dead Zone Area for Wake-up function (if needed)
- Configure the wanted Power Mode and INT function into register [0Fh] (Idle mode / Low Power Mode with Timebase configuration, INT
- X Y coordinates are ready to be read.
Datasheet - Using the N40P112 Module www.austriamicrosystems.com/N40P112 Revision 1.1 10 - 34
8.3 C Source Code Example
8.3.1 Initialization
void EasyPoint_init (void) unsigned char Reset_status = 0; RESETn = 0;Delay_ms(1);// RESETn pulse after power up RESETn = 1; Delay_ms(1); while (Reset_status != 0xF0)// Check the reset has been done Reset_status = I2C_Read8(0x40, 0x0F) & 0xFE; I2C_Write8(0x40, 0x2d, 0x0D); // Scaling factor for N40 (1.0mm knob travel)
8.3.2 Offset Calibration
void Offset_Calibrate (void) char i; int x_cal=0, y_cal=0; EA = 0;// Disable the MCU interrupts I2C_Write8(0x40, 0x0F, 0x00);// Low Power Mode 20ms Delay_ms(1); I2C_Read8(0x40, 0x11); // Flush an unused Y_reg to reset the interrupt for (i=0; i<16; i++)// Read 16 times the coordinates and then average while (INTn);// Wait until next interrupt (new coordinates) x_cal += (signed char) I2C_Read8(0x40, 0x10); // Read X position y_cal += (signed char) I2C_Read8(0x40, 0x11); // Read Y position // offset_X and offset_Y are global variables, used for each coordinate readout in the interrupt routine offset_X = -(x_cal>>4); // Average X: divide by 16 offset_Y = -(y_cal>>4); // Average Y: divide by 16 EA = 1; // Enable the MCU interrupts
Datasheet - Using the N40P112 Module www.austriamicrosystems.com/N40P112 Revision 1.1 11 - 34
8.3.3 Dead Zone area
The dead zone area is set around the zero position of the module. The zero position is known after the offset calibration. The dead zone area is a square with a width of 2*center_threshold, around the calibrated zero position. void Interrupt_Calibrate (center_threshold) EA = 0; // Disable the MCU interrupts I2C_Write8(0x40, 0x12, center_threshold - offset_X ); // Xp register I2C_Write8(0x40, 0x13, -center_threshold - offset_X); // Xn register I2C_Write8(0x40, 0x14, center_threshold - offset_Y); // Yp register I2C_Write8(0x40, 0x15, -center_threshold - offset_Y); // Yn register EA = 1; // Enable the MCU interrupts
8.3.4 Interrupt Routine
void EasyPoint_interrupt (void) interrupt 0 int X_temp, Y_temp; EA=0;// Disable MCU interrupts /* OPTIONAL: If the module is in a slow power mode (e.g. Wakeup mode INT_function=1 with 320ms rate), configure to a higher rate with INTn for new coordinates ready (e.g. INT_function = 0 with 20ms rate) */ x_reg = I2C_Read8(0x40, 0x10); // Read X position y_reg = I2C_Read8(0x40, 0x11); // Read Y position with interrupt reset // Add the X and Y offset for correct recentering X_temp = x_reg + offset_X; Y_temp = y_reg + offset_Y; /* OPTIONAL: If X_temp and Y_temp are near the center since a few interrupts, meaning the knob has been released, the module can be put back in a slow power mode (e.g. Wakeup mode INT_function=1 with 320ms rate) */ EA = 1; // Enable the MCU interrupts
9 XY Coordinates Interpretation
9.1 EasyPoint Operating Principle
Figure 6. Mechanical to XY Register Interpretation Xp=10, Xn = -10, Yp = 10, Yn = -10. The four registers are programmable independently for the four directions. Note: Due to the mechanical tolerance, the coordinates read on X and Y_res_int output registers can show a small offset on both directions. values X and Y_res_int represented in this datasheet are compensated values. The knob is released and on its initial position (0,0). The EasyPoint module is configured with INT_function (Reg 0Fh [2]) = 1. X_reg and Y_reg register values are (0,0), and the interrupt is not active.
microcontroller. The interrupt is reseted HIGH (not active) once the register Y_res_int has been read (see I²C Registers on page 23). The magnet has been moved to the maximum distance from the center (+1.0mm). The maximum X value is -128 decimal.
9.1.1 Knob Displacement and Register Value Relation
0.0mm is the center of the module, when the knob is released). values are the upper side knob movements. the knob is released. More information can be found in chapters 8.2 and 8.3. Figure 7. X Register / X Displacement (Y=0µm)
9.2 Operation Principle
Figure 8. Operation Principle switches automatically into the WAIT state. The hall element data are measured, x/y coordinates are calculated and available in registers 10h and 11h after Tconv = 450µs max.
10 I²C interface
The N40P112 supports the 2-wire high-speed I²C protocol in device mode, according to the NXP specification UM10204. The host MCU (master) has to initiate the data transfers. The 7-bit device address of the N40P112 depends on the state at the pin ADDR. For other I²C addresses, please contact austriamicrosystems. synchronize the SDA data in read and write mode. The maximum I²C clock frequency is 3.4MHz, data are triggered on the rising edge of SCL.
10.1 Interface Operation
Figure 9. I²C Timing Diagram for FS-mode Figure 10. Timing Diagram for HS-mode
Datasheet - I²C interface www.austriamicrosystems.com/N40P112 Revision 1.1 16 - 34
10.2 I²C Electrical Specification
Standard-mode, Fast-mode, High Speed-mode Symbol Parameter Condition Min Max Unit VIL LOW-Level Input Voltage -0.5 0.3VDDp V VIH HIGH-Level Input Voltage 0.7VDDp VDDp + 0.51 1. Maximum V IH = VDDpmax +0.5V or 5.5V, which ever is lower. V Vhys Hysteresis of Schmitt Trigger Inputs VDDp < 2V 0.1VDDp - V VOL LOW-Level Output Voltage (open-drain or open-collector) at 3mA Sink Current VDDp < 2V - 0.2VDDp V ICS Pull-up current of SCLH current source SCLH output levels between 0.3VDDp and 0.7VDDp 31 2 m A tSP Pulse Width of Spikes that must be suppressed by the Input Filter -1 0 n s Ii Input Current at each I/O Pin Input Voltage between 0.1VDDp and 0.9VDDp -1 0 µ A CB Total Capacitive Load for each Bus Line -4 0 0 p F CI/O I/O Capacitance (SDA, SCL)2 2. For capacitive bus loads between 100pF and 400pF, the timing parameters must be linearly interpolated. -1 0 p F
Datasheet - I²C interface www.austriamicrosystems.com/N40P112 Revision 1.1 17 - 34
10.3 I²C Timing
10.4 I²C Modes
The N40P112 supports the I²C bus protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The device that controls the message is called a master. The devices that are controlled by the master are referred to as slaves. A master device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions must control the bus. The N40P112 operates as a slave on the I²C bus. Connections to the bus are made through the open-drain I/O lines SDA and the input SCL. Clock stretching is not included. Symbol Parameter Condition FS-mode HS-mode CB=100pF HS-mode CB=400pF1 1. For bus line loads Cb between 100 and 400 pF, the timing parameters must be linearly interpolated. Unit Min Max Min Max Min Max fSCLK SCL clock Frequency - 400 - 3400 - 1700 kHz tBUF Bus Free Time; time between STOP and START condition 500 - 500 - 500 - ns t HD;STA Hold time; (Repeated) START condition2 2. After this time the first clock is generated. 600 - 160 - 160 - ns tLOW LOW period of SCL clock 1300 - 160 - 320 - ns tHIGH HIGH period of SCL clock 600 - 60 - 120 - ns tSU;STA Setup time for a repeated START condition 600 - 160 - 160 - ns tHD;DAT Data Hold Time3 3. A device must internally provide a minimum hold time (300ns for Fast-mode, 80ns / max 150ns for High-speed mode) for the SDA signal (referred to the VIHmin of the SCL) to bridge the undefined region of the falling edge of SCL. 0 900 0 70 0 150 ns tSU;DAT Data Setup Time4 4. A fast-mode device can be used in standard-mode system, but the requirement tSU;DAT = 250ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tRmax + tSU;DAT = 1000 + 250 = 1250ns before the SCL line is released. 100 - 10 - 10 - ns trCL Rise time of SCLH signal External pull-up source of 3mA - - 10 40 20 80 ns trCL1 Rise time of SCLH signal after repeated START condition and after an acknowledge bit External pull-up source of 3mA - - 10 80 20 160 ns t R Rise time of SDA and SCL signals 20+0.1CB 120 - - - - ns tF Fall time of SDA and SCL signals 20+0.1CB 120 - - - - ns tSU;STO Setup time for STOP condition 600 - 160 - 160 - ns VnL Noise margin at LOW level For each connected device (including hysteresis) 0.1VDDp - 0.1VDDp - 0.1VDDp - V V nH Noise margin at HIGH level 0.2VDDp - 0.2VDDp - 0.2VDDp - V
Datasheet - I²C interface www.austriamicrosystems.com/N40P112 Revision 1.1 18 - 34
10.4.1 Automatic Increment of Address Pointer
The N40P112 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not.
10.4.2 Invalid Addresses
If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte.
10.4.3 Reading
When reading from a wrong address, the N40P112 slave data returns all zero. The address pointer is increased after each byte. Sequential read over the whole address range is possible including address overflow.
10.4.4 Writing
A write to a wrong address is not acknowledged by the N40P112 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including address overflow. The following bus protocol has been defined: Data transfer may be initiated only when the bus is not busy. During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH are interpreted as start or stop signals. Accordingly, the following bus conditions have been defined: Bus Not Busy. Both data and clock lines remain HIGH. Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition. Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition. Data Valid. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited, and are determined by the master device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit. Acknowledge. Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of READ access to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition.
10.4.5 High Speed Mode
The N40P112 is capable to work in HS-mode. within the minimum bus free time tBUF which is 500ns. 10ns, in FS-mode spikes up to 50ns have to be suppressed. detection of 80ns (max. 150ns), in FS-mode an internal hold time of 160ns (max. 250ns) has to be provided. Adapt the slope control for SDAH output stage. Figure 15. Data Transfer Format in HS-mode Figure 16. A Complete HS-mode Transfer
Datasheet - I²C interface www.austriamicrosystems.com/N40P112 Revision 1.1 22 - 34
10.4.6 Automatic Increment of Address Pointer
The N40P112 slave automatically increments the address pointer after each byte transferred. The increase of the address pointer is independent from the address being valid or not.
10.4.7 Invalid Addresses
If the user sets the address pointer to an invalid address, the address byte is not acknowledged. Nevertheless a read or write cycle is possible. The address pointer is increased after each byte. Reading: When reading from a wrong address, the N40P112 slave returns all zero. The address pointer is increased after each byte. Sequential read over the whole address range is possible including address overflow. Writing: A write to a wrong address is not acknowledged by the N40P112 slave, although the address pointer is increased. When the address pointer points to a valid address again, a successful write accessed is acknowledged. Page write over the whole address range is possible including address overflow.
10.5 SDA, SCL Input Filters
Input filters for SDA and SCL inputs are included to suppress noise spikes of less than 50ns. Furthermore, the SDA line is delayed by 120ns to provide an internal hold time for Start/Stop detection to bridge the undefined region of the falling edge of SCL. The delay needs to be smaller than tHD.STA 260ns. For Standard-mode and Fast-mode an internal hold time of 300ns is required, which is not covered by the N40P112 slave.
Datasheet - I²C Registers www.austriamicrosystems.com/N40P112 Revision 1.1 23 - 34
11 I²C Registers
11.1 Control Register 1 (0Fh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Idle Time base bit[2] Time base bit[1] Time base bit[0] INT_disable INT_function Soft_rst Data_valid R/W R/W R/W R/W R/W R/W R/W R Reset value: 1111 0000 Bit Bit Description 0 = Low Power Mode The measurements are triggered with an internal low power oscillator – the user can select between 8 different timings by setting the low power timebase (Control Register 1 [6:4]) 1 = Idle Mode (default) A new measurement cycle is started after the I²C ACK bit following the read out of the Y-coordinate 11h. The readout rate and thus the power consumption is externally controlled by the host MCU. 6:4 Low Power time base Configure the time base of the automatic wakeup in Low Power Mode (see Table 7). 0 = Interrupt output INTn is enabled (default) 1 = Interrupt output INTn is disabled and is fixed to ‘1’ (Hi-Z) 0 = Interrupt output INTn is active ‘0’ after each measurement (default): - Automatically triggered in Low Power mode, depending on the time base chosen - 450µs after Y readout in Idle mode The interrupt is cleared after the I²C ACK bit following the read out of the Y-coordinate 11h. In block read mode, the several other bytes could be transferred before the interrupt is cleared. 1 = Interrupt output INTn is active ‘0’ when the movement of the magnet exceeds the Dead Zone area (see Figure 17). The Dead Zone area is set by registers Xp (Reg 12h), Xn (Reg 13h), Yp (Reg 14h), Yn (Reg 15h). The interrupt is cleared after the I²C ACK bit following the read out of the Y-coordinate 11h, and will be active ‘0’ at the next measurement if the magnet is still in the Detection Area. In block read mode, several other bytes can be transferred before the interrupt is cleared. It is recommended to use this mode with the Low Power mode (Idle = 0), in order to wake up automatically a system when the magnet has been moved away from the center. The polling time is the Low Power time base bit [6:4]. 0 = Normal mode (default) 1 = Reset mode. All the internal registers are loaded with their reset value. The Control Register 1 is loaded as well with the value 1111 0000, then the Soft_rst bit goes back to 0 once the internal reset sequence is finished. 0 = Conversion of new coordinates ongoing, no valid coordinate is present in the X and Y_res_int registers. Reading those registers at that moment can give wrong values. 1 = New coordinate values are ready in X and Y_res_int registers.
Figure 17. Dead Zone Representation with INT_function=1 Note: The values in Control Register 1, X_register and Y_res_int register are frozen when the I²C address pointer is set to 0Fh, 10h or 11h. the address pointer to any other address. Table 7. Configuration
Datasheet - I²C Registers www.austriamicrosystems.com/N40P112 Revision 1.1 25 - 34
11.2 X Register (10h)
11.3 Y_res_int Register (11h)
11.4 Xp Register (12h)
11.5 Xn Register (13h)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R RRRRR Reset value: 0000 0000 Bit Bit Description 7:0 X coordinate, Two’s complement format (signed -128 ~ +127). Positive X values represent left side knob movements. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R RRRRR Reset value: 0000 0000 Bit Bit Description 7:0 Y coordinate, Two’s complement format (signed -128~+127). Reading this register will reset the INTn output to Hi-Z, after the ACK bit of Y_res_int register readback. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Xp[7] Xp[6] Xp[5] Xp[4] Xp[3] Xp[2] Xp[1] Xp[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0101 (5d) Bit Bit Description 7:0 Xp range value, Two’s complement (signed: -128 ~ +127). Determines the LEFT threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 23). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Xn[7] Xn[6] Xn[5] Xn[4] Xn[3] Xn[2] Xn[1] Xn[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 1111 1011 (-5d) Bit Bit Description 7:0 Xn range value, Two’s complement (signed: -128 ~ +127). Determines the RIGHT threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 23).
Datasheet - I²C Registers www.austriamicrosystems.com/N40P112 Revision 1.1 26 - 34
11.6 Yp Register (14h)
11.7 Yn Register (15h)
11.8 M_ctrl Register (2Bh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Yp[7] Yp[6] Yp[5] Yp[4] Yp[3] Yp[2] Yp[1] Yp[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0101 (5d) Bit Bit Description 7:0 Yp range value, Two’s complement (signed: -128 ~ +127). Determines the TOP threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 23). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Yn[7] Yn[6] Yn[5] Yn[4] Yn[3] Yn[2] Yn[1] Yn[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 1111 1011 (-5d) Bit Bit Description 7:0 Yn range value, Two’s complement (signed: -128 ~ +127). Determines the BOTTOM threshold for the activation of INTn output (if output enabled), when bit INT_function = 1 (see Control Register 1 (0Fh) on page 23). Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 M_ctrl[7] M_ctrl[6] M_ctrl[5] M_ctrl[4] M_ctrl[3] M_ctrl[2] M_ctrl[1] M_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0000 (00h) Bit Bit Description 7:0 Middle hall element control register. The M_ctrl register must be set to 00h (default value) after power up for N40P112 module.
Datasheet - I²C Registers www.austriamicrosystems.com/N40P112 Revision 1.1 27 - 34
11.9 J_ctrl Register (2Ch)
11.10 T_ctrl Register (2Dh)
11.11 Control Register 2 (2Eh)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 J_ctrl[7] J_ctrl[6] J_ctrl[5] J_ctrl[4] J_ctrl[3] J_ctrl[2] J_ctrl[1] J_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 0110 (06h) Bit Bit Description 7:0 Sector dependent attenuation of the outer Hall elements. The J_ctrl register must be set to 06h (default value) after power up for N40P112 module. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T_ctrl[7] T_ctrl[6] T_ctrl[5] T_ctrl[4] T_ctrl[3] T_ctrl[2] T_ctrl[1] T_ctrl[0] R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 0000 1001 (09h) Bit Bit Description 7:0 Scaling control register. This register controls the scaling factor of the XY coordinates to fit to the 8-bit X and Y register (full dynamic range). The T_ctrl register must be set to 0Dh after power up for N40P112 module. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Test Test Test Test Test Test inv_spinning Test R/W R/W R/W R/W R/W R/W R/W R/W Reset value: 1000 0100 Bit Bit Description 7 Test bit. Must configured ‘1’. 6:3 Test bit. Must configured ‘0’. 2 Test bit. Must configured ‘1’. 1 Magnet Polarity. Must be set to ‘0’ with EasyPoint modules. 0 Test bit. Must be ‘0’.
11.12 Registers Table
The following registers / functions are accessible over the serial I²C interface. Table 8. Registers Disables the interrupt functionality.
1 R 0Fh 0b <0> Data valid indicator
inv_spinning 1 R/W 2Eh 0b <1> Invert the channel voltage.
Figure 18. N40P112 Dimensions (mm ±0.15) Figure 19. Recommended PCB Layout (mm ±0.05)
Figure 20. Recommended on Casing Design & Mounting Note
Datasheet - Revision History www.austriamicrosystems.com/N40P112 Revision 1.1 32 - 34
Revision History
Note: Typos may not be explicitly mentioned under revision history. Revision Date Owner Description 0.8 16 Jul, 2010 jlu Initial release 1.0 01 Dec, 2010 Updated Applications on page 1 and url in the footer
The devices are available as the standard products shown in Table 9. Note: All products are RoHS compliant. Table 9. Ordering Information
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