MTEA0N10J3 CYSTEKEC | Alldatasheet

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Technical content

Features

  • Low Gate Charge
  • Simple Drive Requirement
  • Pb-free lead plating package Equivalent Circuit Outline MTEA0N10J3 TO-252AB TO-252AA G D S G D S G：Gate D：Drain S：Source Absolute Maximum Ratings (TC=25°C, unless otherwise noted) Parameter Symbol Limits Unit Drain-Source V oltage VDS 100 Gate-Source V oltage VGS ±20 V Continuous Drain Current @ VGS=10V , TC=25°C (Note 1) 16 Continuous Drain Current @ VGS=10V , TC=100°C (Note 1) 11 Continuous Drain Current @ VGS=10V , TA=25°C (Note 2) 3.7 Continuous Drain Current @ VGS=10V , TA=100°C (Note 2) ID 2.3 Pulsed Drain Current (Note 3) IDM 64 Avalanche Current (Note 3) IAS 11 A Avalanche Energy @ L=0.5mH, ID=11A, RG=25Ω (Note 2) EAS 30 Repetitive Avalanche Energy@ L=0.1mH (Note 3) EAR 6 mJ Total Power Dissipation @TC=25℃ (Note 1) 60 Total Power Dissipation @TC=100℃ (Note 1) PD 30 Total Power Dissipation @TA=25℃ (Note 2) 2.5 W PDSM Total Power Dissipation @TA=70℃ (Note 2) 1.6 Operating Junction and Storage Temperature Range Tj, Tstg -55~+175 °C

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 2/10 MTEA0N10J3 CYStek Product Specification Thermal Data Parameter Symbol Value Unit Thermal Resistance, Junction-to-case, max Rth,j-c 2.5 °C/W Thermal Resistance, Junction-to-ambient, max (Note 2) RθJA 50 °C/W Thermal Resistance, Junction-to-ambient, max (Note 4) RθJA 110 °C/W Note : 1.The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2. The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air environment with TA=25°C. The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user’s specific board design, and the maximum temperature of 175°C may be used if the PCB allows it. 3. Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and low duty cycles to keep initial TJ=25°C. 4. When mounted on the minimum pad size recommended (PCB mount), t≤10s. Characteristics (Tc=25°C, unless otherwise specified) Symbol Min. Typ. Max. Unit Test Conditions Static BVDSS 100 - - V VGS=0, ID=250μA VGS(th) 2 3.2 4 V VDS =VGS, ID=250μA IGSS - - ±100 nA VGS=±20, VDS=0 - - 1 VDS =80V , VGS =0 IDSS - - 25 μA VDS =80V , VGS =0, TJ=125°C - 83 110 VGS =10V , ID=12A RDS(ON) *1 - 100 130 mΩ VGS =6V , ID=10A GFS *1 - 11 - S VDS =5V , ID=12A Dynamic Qg *1, 2 - 5.5 - Qgs *1, 2 - 1.3 - Qgd *1, 2 - 2.1 - nC ID=10A, VDS=50V , VGS=10V td(ON) *1, 2 - 4 - tr *1, 2 - 15 - td(OFF) *1, 2 - 15 - tf *1, 2 - 3.9 - ns VDS=50V , ID=1A, VGS=10V , RG=6Ω Ciss - 361 - Coss - 54 - Crss - 20 - pF VGS=0V , VDS=25V , f=1MHz Source-Drain Diode IS *1 - - 12 ISM *3 - - 30 A VSD *1 - 0.89 1.3 V IF=IS, VGS=0V trr - 35 - ns Qrr - 22 - nC IF=10A, dIF/dt=100A/μs Note : *1.Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2% *2.Independent of operating temperature *3.Pulse width limited by maximum junction temperature.

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 3/10 MTEA0N10J3 CYStek Product Specification

Ordering Information

(Pb-free lead plating and halogen-free package) 2500 pcs / Tape & Reel

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 4/10 MTEA0N10J3 CYStek Product Specification Typical Characteristics Typical Output Characteristics 02468 1 0 Brekdown Voltage vs Ambient Temperature 0.4 0.6 0.8 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 Tj, Junction Temperature(°C) BVDSS, Normalized Drain-Source Breakdown Voltage ID=250μA, VGS=0V VDS, Drain-Source Voltage(V) ID, Drain Current (A) 10V 7V VGS=6V VGS=5V Static Drain-Source On-State resistance vs Drain Current 100 1000 0.01 0.1 1 10 100 ID, Drain Current(A) RDS(on), Static Drain-Source On-State Resistance(mΩ) VGS=10V VGS=4.5V VGS=6V Reverse Drain Current vs Source-Drain Voltage 0.2 0.4 0.6 0.8 1.2 02468 I DR, Reverse Drain Current(A) VSD, Source-Drain Voltage(V) 1 0 Tj=25°C Tj=150°C VGS=0V Static Drain-Source On-State Resistance vs Gate-Source Voltage 120 160 200 240 280 320 360 400 02468 1 Drain-Source On-State Resistance vs Junction Tempearture 0.4 0.8 1.2 1.6 2.4 -60 -20 20 60 100 140 180 Tj, Junction Temperature(°C) RDS(on), Normalized Static Drain- Source On-State Resistance VGS=10V, ID=12A RDS(ON)@Tj=25°C : 83mΩ VGS, Gate-Source Voltage(V) RDS(on), Static Drain-Source On- State Resistance(mΩ) ID=12A

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 5/10 MTEA0N10J3 CYStek Product Specification Typical Characteristics(Cont.) Capacitance vs Drain-to-Source Voltage 100 1000 0.1 1 10 100 VDS, Drain-Source Voltage(V) Capacitance---(pF) Coss Ciss Crss Threshold Voltage vs Junction Tempearture 0.4 0.6 0.8 1.2 1.4 -60 -20 20 60 100 140 Tj, Junction Temperature(°C) VGS(th), Normalized Threshold Voltage ID=250μA Forward Transfer Admittance vs Drain Current 0.01 0.1 100 0.001 0.01 0.1 1 10 ID, Drain Current(A) GFS, Forward Transfer Admittance(S) Ta=25°C Pulsed VDS=5V Gate Charge Characteristics 0123456 Qg, Total Gate Charge(nC) VGS, Gate-Source Voltage(V) ID=10A VDS=80V VDS=50V VDS=20V Maximum Safe Operating Area 0.01 0.1 100 0.1 1 10 100 1000 VDS, Drain-Source Voltage(V) ID, Drain Current(A) TC=25°C, Tj=175°C VGS=10V, θJC=2.5°C/W Single Pulse DC 100ms RDSON Limited 100μs 1ms 10ms Maximum Drain Current vs Case Temperature 25 50 75 100 125 150 175 200 T C, Case Temperature(°C) ID, Maximum Drain Current(A)VGS=10V, RθJC=2.5°C/W

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 6/10 MTEA0N10J3 CYStek Product Specification Typical Characteristics(Cont.) Typical Transfer Characteristics 02468 1 0 VGS, Gate-Source Voltage(V) ID, Drain Current(A) VDS=10V Power Derating Curve 0 25 50 75 100 125 150 175 200 T C, Case Temperature(℃) PD, Power Dissipation(W) Transient Thermal Response Curves 0.001 0.01 0.1 t1, Square Wave Pulse Duration(s) r(t), Normalized Effective Transient Thermal Resistance Single Pulse 0.01 0.02 0.05 0.1 0.2 D=0.5 1.RθJC(t)=r(t)*RθJC 2.Duty Factor, D=t1/t2 3.TJM-TC=PDM*RθJC(t) 4.RθJC=2.5°C/W Single Pulse Maximum Power Dissipation 100 200 300 400 500 600 700 800 900 1000 0.001 0.01 0.1 1 10 100 1000 Pulse Width(s) Peak Transient Power (W) TJ(MAX)=175°C TC=25°C θJC=2.5°C/W

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 7/10 MTEA0N10J3 CYStek Product Specification Reel Dimension Carrier Tape Dimension

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 8/10 MTEA0N10J3 CYStek Product Specification Recommended wave soldering condition Soldering Time Product Peak Temperature Pb-free devices 260 +0/-5 °C 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Sn-Pb eutectic Assembly Pb-free Assembly Average ramp-up rate (Tsmax to Tp) 3°C/second max. 3°C/second max. Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: −Temperature (TL) − Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak Temperature(TP) 240 +0/-5 °C 260 +0/-5 °C Time within 5°C of actual peak temperature(tp) 10-30 seconds 20-40 seconds Ramp down rate 6°C/second max. 6°C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface.

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 9/10 MTEA0N10J3 CYStek Product Specification TO-252AB Dimension *: Typical Inches Millimeters Inches Marking: Device Name Date Code EA0 N10 □□□□ Style: Pin 1.Gate 2.Drain 3.Source 4.Drain 3-Lead TO-252AB Plastic Surface Mount Package CYStek Package Code: J3 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material:

  • Lead : Pure tin plated.
  • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0.

CYStech Electronics Corp. Spec. No. : C871J3 Issued Date : 2013.01.03 Revised Date : Page No. : 10/10 MTEA0N10J3 CYStek Product Specification TO-252AA Dimension Marking: Style: Pin 1.Gate 2.Drain 3.Source 4.Drain 3-Lead TO-252AA Plastic Surface Mount Package CYStek Package Code: J3 Device Name Date Code EA0 N10 □□□□ 1 2 3 Notes: 1.Controlling dimension: millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material:

  • Lead : Pure tin plated.
  • Mold Compound: Epoxy resin family, flammability solid burning class: UL94V-0. Important Notice:
  • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
  • CYStek reserves the right to make changes to its products without notice.
  • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
  • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance.