MTE2D4N06F3 CYSTEKEC | Alldatasheet

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(Pb-free lead plating and RoHS compliant package) 800 pcs / Tape & Reel TO-263 MTE2D4N06F3 G：Gate D：Drain S：Source BVDSS 60V ID @VGS=10V , TC=25°C 60A RDSON(TYP) @ VGS=10V , ID=20A 3.3mΩ RDSON(TYP) @ VGS=7V , ID=20A 3.5mΩ G D S Environment friendly grade : S for RoHS compliant products, G for RoHS compliant and green compound products Packing spec, T7 : 800 pcs / tape & reel, 13” reel Product rank, zero for no rank products Product name

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 2/9 MTE2D4N06F3 CYStek Product Specification Absolute Maximum Ratings (TC=25°C, unless otherwise noted) Parameter Symbol Limits Unit Drain-Source V oltage VDS 60 Gate-Source V oltage VGS ±30 V Continuous Drain Current @ TC=25°C(silicon limit) 188 Continuous Drain Current @ TC=100°C(silicon limit) 133 Continuous Drain Current @ TC=25°C(package limit) (Note 1) ID Pulsed Drain Current (Note 3) IDM 480 Continuous Drain Current @ TA=25°C (Note 2) 15 Continuous Drain Current @ TA=70°C (Note 2) IDSM 12 Avalanche Current (Note 3) IAS 120 A Avalanche Energy @ L=1mH, ID=40A, RG=25Ω (Note 4) EAS 800 mJ TC=25°C (Note 1) 330 Power Dissipation TC=100°C (Note 1) PD 165 TA=25°C (Note 2) 2 Power Dissipation TA=70°C (Note 2) PDSM 1.3 W Operating Junction and Storage Temperature Tj, Tstg -55~+175 °C Thermal Data Parameter Symbol Value Unit Thermal Resistance, Junction-to-case, max Rth,j-c 0.45 Thermal Resistance, Junction-to-ambient, max, (Note 2) Rth,j-a 62.5 °C/W Note : 1.The power dissipation PD is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation limit for cases where additional heatsinking is used. 2.The value of RθJA is measured with the device mounted on 1 in²FR-4 board with 2 oz. copper, in a still air environment with TA=25°C. The power dissipation PDSM is based on RθJA and the maximum allowed junction temperature of 150°C. The value in any given application depends on the user’s specific board design, and the maximum temperature of 175°C may be used if the PCB allows it. 3. Pulse width limited by junction temperature TJ(MAX)=175°C. Ratings are based on low frequency and low duty cycles to keep initial TJ=25°C. 4. 100% tested by conditions of L=1mH, IAS=25A, VGS=15V , VDD=25V . 5. The static characteristics are obtained using <300μs pulses, duty cycle 0.5% maximum. 6. The RθJA is the sum of thermal resistance from junction to case RθJC and case to ambient.

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 3/9 MTE2D4N06F3 CYStek Product Specification Characteristics (TC=25°C, unless otherwise specified) Symbol Min. Typ. Max. Unit Test Conditions Static BVDSS 60 - - VGS=0V , ID=250μA VGS(th) 2.0 - 4.0 V VDS = VGS, ID=250μA GFS - 40.8 - S VDS =10V , ID=20A IGSS - - ±100 nA VGS=±30V - - 1 VDS =48V , VGS =0V IDSS - - 25 μA VDS =48V , VGS =0V , Tj=125°C - 3.3 4.5 VGS =10V , ID=20A *RDS(ON) - 3.5 5.5 mΩ VGS =7V , ID=20A Dynamic *Qg - 124.4 - *Qgs - 22.5 - *Qgd - 54.0 - nC ID=120A, VDS=30V , VGS=10V *td(ON) - 47.6 - *tr - 55 - *td(OFF) - 88.2 - *tf - 40 - ns VDS=30V , ID=60A, VGS=10V , RG=4.7Ω Ciss - 5871 - Coss - 1011 - Crss - 335 - pF VGS=0V , VDS=25V , f=1MHz Rg - 2.9 - Ω f=1MHz Source-Drain Diode *IS - - 60 *ISM - - 480 A *VSD - 0.66 0.9 V IS=1A, VGS=0V *trr - 41 - ns *Qrr - 53 - nC IF=20A, VGS=0V , dIF/dt=100A/μs *Pulse Test : Pulse Width ≤300μs, Duty Cycle≤2%

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 4/9 MTE2D4N06F3 CYStek Product Specification Typical Characteristics Typical Output Characteristics 120 160 200 012345 V DS, Drain-Source Voltage(V) ID, Drain Current(A) 10V, 9V, 8V VGS=5.5V Brekdown Voltage vs Ambient Temperature 0.4 0.6 0.8 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) BVDSS, Normalized Drain-Source Breakdown Voltage ID=250μA, VGS=0V Static Drain-Source On-State resistance vs Drain Current 100 1000 0.01 0.1 1 10 100 ID, Drain Current(A) RDS(ON), Static Drain-Source On-State Resistance(mΩ) VGS=6V 10V Reverse Drain Current vs Source-Drain Voltage 0.2 0.4 0.6 0.8 1.2 048 1 2 1 6 2 IDR, Reverse Drain Current(A) VSD, Source-Drain Voltage(V) Tj=25°C Tj=150°C Static Drain-Source On-State Resistance vs Gate-Source Voltage 100 02468 1 Drain-Source On-State Resistance vs Junction Tempearture 0.4 0.8 1.2 1.6 2.4 2.8 -75 -50 -25 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) RDS(ON), Normalized Static Drain- Source On-State Resistance VGS=10V, ID=20A RDS( ON)@Tj=25°C :3.3mΩ typ VGS, Gate-Source Voltage(V) RDS(ON), Static Drain-Source On- State Resistance(mΩ) ID=20A

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 5/9 MTE2D4N06F3 CYStek Product Specification Typical Characteristics(Cont.) Capacitance vs Drain-to-Source Voltage 100 1000 10000 0 5 10 15 20 25 30 VDS, Drain-Source Voltage(V) Capacitance---(pF) Coss Ciss Crss NormalizedThreshold Voltage vs Junction Tempearture 0.2 0.4 0.6 0.8 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 Tj, Junction Temperature(°C) VGS(th), Normalized Threshold Voltage ID=250μA ID=1mA Forward Transfer Admittance vs Drain Current 0.01 0.1 100 0.001 0.01 0.1 1 10 100 ID, Drain Current(A) GFS, Forward Transfer Admittance(S) VDS=10V Pulsed Ta=25°C Gate Charge Characteristics 0 20 40 60 80 100 120 140 160 Total Gate Charge---Qg(nC) VGS, Gate-Source Voltage(V) VDS=30V ID=120A Maximum Safe Operating Area 0.1 100 1000 0.1 1 10 100 1000 VDS, Drain-Source Voltage(V) ID, Drain Current(A) DC 10ms 100ms 1ms 10μsRDS( ON) Limited TC=25°C, Tj=175°, VGS=10V RθJC=0.45°C/W, Single Pl 100μs Maximum Drain Current vs Case Temperature 120 160 200 25 50 75 100 125 150 175 200 T C, Case Temperature(°C) ID, Maximum Drain Current(A) VGS=10V, RθJC=0.45°C/W silicon limit package limit

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 6/9 MTE2D4N06F3 CYStek Product Specification Typical Characteristics(Cont.) Typical Transfer Characteristics 120 160 200 02468 1 0 V GS, Gate-Source Voltage(V) ID, Drain Current (A) VDS=10V Single Pulse Maximum Power Dissipation 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 0.0001 0.001 0.01 0.1 1 10 Pulse Width(s) Power (W) TJ(MAX)=175°C TC=25°C RθJC=0.45°C/W Transient Thermal Response Curves 0.001 0.01 0.1 t1, Square Wave Pulse Duration(s) r(t), Normalized Effective Transient Thermal Resistance Single Pulse 0.01 0.02 0.05 0.1 0.2 D=0.5 1.RθJC(t)=r(t)*RθJC 2.Duty Factor, D=t1/t2 3.TJM-TC=PDM*RθJC(t) 4.RθJC=0.45 °C/W

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 7/9 MTE2D4N06F3 CYStek Product Specification Reel Dimension Carrier Tape Dimension

CYStech Electronics Corp. Spec. No. : C933F3 Issued Date : 2015.12.11 Revised Date : Page No. : 8/9 MTE2D4N06F3 CYStek Product Specification Recommended wave soldering condition Product Peak Temperature Soldering Time Pb-free devices 260 +0/-5 °C 5 +1/-1 seconds Recommended temperature profile for IR reflow Profile feature Sn-Pb eutectic Assembly Pb-free Assembly Average ramp-up rate (Tsmax to Tp) 3°C/second max. 3°C/second max. Preheat −Temperature Min(TS min) −Temperature Max(TS max) −Time(ts min to ts max) 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds Time maintained above: −Temperature (TL) − Time (tL) 183°C 60-150 seconds 217°C 60-150 seconds Peak Temperature(TP) 240 +0/-5 °C 260 +0/-5 °C Time within 5°C of actual peak temperature(tp) 10-30 seconds 20-40 seconds Ramp down rate 6°C/second max. 6°C/second max. Time 25 °C to peak temperature 6 minutes max. 8 minutes max. Note : All temperatures refer to topside of the package, measured on the package body surface.

CYStech Electronics Corp. Issued Date : 2015.12.11 Revised Date : Page No. : 9/9 Spec. No. : C933F3 MTE2D4N06F3 CYStek Product Specification TO-263 Dimension *:Typical Inches Marking : E 0.1600 0.1900 4.06 4.83 α1 - - 6° 8° F 0.0450 0.0550 1.14 1.40 α2 - - 6° 8° G 0.0900 0.1100 2.29 2.79 α3 - - 0° 5° H 0.0180 0.0290 0.46 0.74 Notes : 1.Controlling dimension : millimeters. 2.Maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.If there is any question with packing specification or packing method, please contact your local CYStek sales office. Material :

  • Lead : Pure tin plated.
  • Mold Compound : Epoxy resin family, flammability solid burning class:UL94V-0. Important Notice:
  • All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of CYStek.
  • CYStek reserves the right to make changes to its products without notice.
  • CYStek semiconductor products are not warranted to be suitable for use in Life-Support Applications, or systems.
  • CYStek assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. A B C D 123 K L J G H E F 2 α1 Style : Pin 1.Gate 2.Drain 3.Source 3-Lead Plastic Surface Mounted Package CYStek Package Code : F3 E2D4 N06 □□□□ Device Name I Date Code Date Code : (From left to right) First Code : Year code, the last digit of Christinr year. For example, 2014→4, 2015→, 2016→6, …, etc. Second Code : Month code, Jan→A, Feb→B, Mar→C, Apr→D, May→E, Jun→F, Jul→G, A u g→H, Sep→J, Oct→K, Nov→L, Dec→M Third and fourth codes : production serial number, 01~99