MSP3438G MICRONAS | Alldatasheet
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- 2 MICRONAS INTERMETALL
Edition July 27, 1999 6251-494-1PD PRELIMINARY DATA SHEET MICRONAS INTERMETALL MICRONAS
Contents, continued Page Section Title PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 3 25 3.3.2.5. Write Registers on I 2C Subaddress 12hex 31 3.3.2.6. Read Registers on I 2C Subaddress 13hex 33 3.4. Programming Tips 33 3.5. Examples of Minimum Initialization Codes 33 3.5.1. B/G-FM (A2 or NICAM) 33 3.5.2. BTSC-Stereo 33 3.5.3. BTSC-SAP with SAP at Loudspeaker Channel 34 3.5.4. FM-Stereo Radio 34 3.5.5. Automatic Standard Detection 34 3.5.6. Software Flow for Interrupt driven STATUS Check 35 4. Specifications 35 4.1. Outline Dimensions 37 4.2. Pin Connections and Short Descriptions 40 4.3. Pin Descriptions 43 4.4. Pin Configurations 47 4.5. Pin Circuits 49 4.6. Electrical Characteristics 49 4.6.1. Absolute Maximum Ratings 50 4.6.2. Recommended Operating Conditions (T A = 0 to 70 °C) 50 4.6.2.1. General Recommended Operating Conditions 50 4.6.2.2. Analog Input and Output Recommendations 51 4.6.2.3. Recommendations for Analog Sound IF Input Signal 52 4.6.2.4. Crystal Recommendations 53 4.6.3. Characteristics 53 4.6.3.1. General Characteristics 54 4.6.3.2. Digital Inputs, Digital Outputs 55 4.6.3.3. Reset Input and Power-Up 56 4.6.3.4. I 2C-Bus Characteristics 57 4.6.3.5. I 2S-Bus Characteristics 59 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC 61 4.6.3.7. Sound IF Inputs 61 4.6.3.8. Power Supply Rejection 62 4.6.3.9. Analog Performance 65 4.6.3.10. Sound Standard Dependent Characteristics 68 5. Appendix A: Overview of TV-Sound Standards 68 5.1. NICAM 728 69 5.2. A2-Systems 70 5.3. BTSC-Sound System 70 5.4. Japanese FM Stereo System (EIA-J) 71 5.5. FM Satellite Sound 71 5.6. FM-Stereo Radio
MSP 3438G PRELIMINARY DATA SHEET
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Contents, continued Page Section Title 72 6. Appendix B: Manual Mode 72 6.1. Demodulator Write and Read Registers for Manual Mode 73 6.2. DSP Write and Read Registers for Manual Mode 74 6.3. Manual Mode: Description of Demodulator Write Registers 74 6.3.1. Automatic Switching between NICAM and Analog Sound 74 6.3.1.1. Function in Automatic Sound Select Mode 74 6.3.1.2. Function in Manual Mode 75 6.3.2. A2 Threshold 75 6.3.3. Carrier-Mute Threshold 76 6.3.4. DCO-Registers 77 6.4. Manual Mode: Description of Demodulator Read Registers 77 6.4.1. NICAM Mode Control/Additional Data Bits Register 77 6.4.2. Additional Data Bits Register 77 6.4.3. CIB Bits Register 78 6.4.4. NICAM Error Rate Register 78 6.4.5. Automatic Search Function for FM-Carrier Detection in Satellite Mode 79 6.5. Manual Mode: Description of DSP Write Registers 79 6.5.1. Additional Channel Matrix Modes 79 6.5.2. FM Fixed Deemphasis 79 6.5.3. FM Adaptive Deemphasis 79 6.5.4. NICAM Deemphasis 80 6.5.5. Identification Mode for A2 Stereo Systems 80 6.6. Manual Mode: Description of DSP Read Registers 80 6.6.1. Stereo Detection Registerfor A2 Stereo Systems 80 6.6.2. DC Level Register 80 6.7. Demodulator Source Channels in Manual Mode 80 6.7.1. Terrestrial Sound Standards 80 6.7.2. SAT Sound Standards 82 6.8. Exclusions of Audio Baseband Features 82 6.9. Phase Relationship of Analog Outputs 83 7. Appendix C: Application Circuit 84 8. Data Sheet History
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 5 Multistandard Sound Processor Family The hardware and software description in this docu- ment is valid only for the MSP 3438G version A1. All new versions of the MSP 3438G and all other men- tioned members of the MSP 34x8G family will be real- ized within the MSP 44x8G family with an extended feature set. Please refer to the appropriate data sheet. 1. Introduction The MSP 34x8G family of Multistandard Sound Pro- cessors covers the sound processing of all analog TV- Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, start- ing with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 1–1 shows a simplified functional block diagram of the MSP 34x8G. The high-quality A/D and D/A converters offer the full audio bandwidth of 20 kHz and the backend DSP pro- cessing is performed at a 48 kHz sample rate. The MSP 34x8G has been designed for the usage in hybrid set-top boxes and multimedia applications. Its asynchronous I 2S slave interface allows the reception of digital stereo signals with arbitrary sample rates ranging from 5 to 50 kHz. Synchronization is per- formed by means of an adaptive sample rate con- verter. The processed standards include the multichannel television sound signal (MTS) which conforms to the recommendations of the BTSC, as well as the Japa- nese FM-FM multiplex standard (EIA-J). For these standards, optimum stereo separation is achieved without any adjustment. In addition, the MSP 34x8G is also able to receive FM stereo radio and, in conjunc- tion with the DRP 3510, ASTRA Digital Radio (ADR). The DBX noise reduction is performed alignment-free. The MSP 34x8G versions are pin and software com- patible to other MSP families. Standard selection requires only a single I 2C transmission. Several built-in automatic functions detect the actual sound standard (Automatic Standard Detection) or evaluate pilot levels and identification signals. Auto- matic switching between mono/stereo/bilingual is per- formed by the Automatic Sound Selection. A status change indication signal makes polling of sta- tus information unnecessary. The ICs are produced in submicron CMOS technology and are available in the following packages: PQFP80, PLQFP64, PLCC68, and PSDIP64. Fig. 1–1:Simplified functional block diagram of the MSP 34x8G Source Select Loud- SCART1 SCART2 SCART1 SCART2 SCART4 SCART3 MONO De- modulator Aux Headphone I2S Sound Processing speaker Sound Processing DAC DAC ADC Loud- DAC DAC ADC SCART DSP Input Select Pre- processing SCART Output Select Prescale Prescale I2S1 I2S2 Sound IF1 Sound IF2 speaker /Modulator I2S3 synchron. I2S asynchron. I2S
MSP 3438G PRELIMINARY DATA SHEET
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1.1. Features of the MSP 34x8G Family 1.2. MSP 34x8G Version List Feature 3408 3418 3438 3448 3458 Standard Selection with single I2C transmission XX X XX Automatic Sound Selection (mono, stereo, or bilingual) XX X XX Automatic Carrier Mute function XX X XX Interrupt output programmable (indicating status change) XX X XX Loudspeaker and Aux channel with volume XX X XX AVC: Automatic Volume Correction XX X XX Processing of all deemphasis filtering XX X XX Two selectable sound IF (SIF) inputs XX X XX Four stereo SCART (line) inputs, one mono input; two stereo SCART outputs XX X XX Complete SCART in/out switching matrix XX X XX Two 48 kHz I2S inputs; one async. 5..50 kHz I2S input; one 48 kHz I2S output XX X XX Automatic Standard Detection of terrestrial TV standards XX X XX All analog FM-Stereo A2 standards XX X Simultaneous demodulation of high-deviation FM-Mono and NICAM XX X Very high-deviation FM-Mono mode XX X FM demodulation of all analog satellite standards XX X Adaptive deemphasis for satellite (Wegener-Panda, according to ASTRA specification)XX X ASTRA Digital Radio (ADR) in conjunction with DRP 3510A XX X All NICAM standards XX Demodulation of the BTSC multiplex signal and the SAP channel X XX Alignment-free digital DBX noise reduction X XX BTSC stereo separation (MSP 3448G also EIA-J) significantly better than specification X XX SAP and stereo detection for BTSC system X XX Demodulation of the FM-Radio multiplex signal X XX Korean FM-Stereo A2 standard XX Alignment-free Japanese standard EIA-J XX Version Status Description MSP 3408G will be realized as MSP 4408G A2 Version MSP 3418G will be realized as MSP 4418G NICAM Version (can handle all A2 systems and all NICAM systems) MSP 3438G A1 available BTSC Version MSP 3448G will be realized as MSP 4448G NTSC Version (can handle A2 Korea, BTSC, and Japanese EIA-J) MSP 3458G will be realized as MSP 4458G Global Version (can handle all systems)
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 7 1.3. MSP 34x8G Versions and their Application Fields Table 1–1 provides an overview of TV sound stan- dards that can be processed by the MSP 34x8G fam- ily. In addition, the MSP 34x8G is able to handle the terrestrial FM-Radio standard. With the MSP 34x8G, a complete multimedia receiver covering all TV sound standards together with terrestrial and satellite radio sound can be built; even ASTRA Digital Radio can be processed (with a DRP 3510A coprocessor). Fig. 1–2:Typical MSP 34x8G application Table 1–1:TV Stereo Sound Standards covered by the MSP 34x8G Family (details see Appendix A) MSP Version System Position of Sound Carrier / MHz Sound Modulation Color System Broadcast e.g. in: 3408 3418 3458 B/G 5.5/5.7421875 FM-Stereo (A2) PAL Germany 5.5/5.85 FM-Mono/NICAM PAL Scandinavia, Spain L 6.5/5.85 AM-Mono/NICAM SECAM-L France I 6.0/6.552 FM-Mono/NICAM PAL UK, Hong Kong D/K 6.5/5.85 FM-Mono/NICAM PAL China, Hungary 3408 6.5/6.2578125 FM-Stereo (A2, D/K1) SECAM-East Slovak. Rep. 6.5/6.7421875 FM-Stereo (A2, D/K2) PAL currently no broadcast 6.5/5.7421875 FM-Stereo (A2, D/K3) SECAM-East Poland Satellite 6.5 7.02/7.2 7.38/7.56 etc. FM-Mono FM-Stereo ASTRA Digital Radio (ADR) with DRP 3510A PAL Europe Sat. ASTRA 3448 M 4.5/4.724212 FM-Stereo (A2) NTSC Korea
4.5 FM-FM (EIA-J) NTSC Japan
4.5 BTSC-Stereo + SAP NTSC USA
FM-Radio 10.7 FM-Stereo Radio USA, Europe 33 34 39 MHz 4.5 9 MHz Loudspeaker Headphone SCART Outputs2 SCART2 SCART1 MSP 34x8G I2S2I2S1 ADR Decoder Digital Signal SCART1 SCART2 SCART3 SCART4 Mono SAW Filter Sound IF Mixer Vision Demo- dulator Tuner SCART Inputs Composite Video I2S3 Dolby- Digital / MPEG / Modulator ADR
MSP 3438G PRELIMINARY DATA SHEET
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- Functional Description D A Prescale Prescale SCART1 Channel Matrix Volume DACA_L DACA_R Source Select Quasi-Peak Detector SCART2 Channel Matrix I2S Channel Matrix Quasi-Peak Channel Matrix Loudspeaker Channel Matrix Aux Channel Matrix AVC Volume I2S Interface Volume I2C Read Register I2S Interface I2S Interface SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R SC3_IN_L SC3_IN_R SC4_IN_L SC4_IN_R MONO_IN Prescale I2S_DA_OUT I2S_DA_IN1 I2S_DA_IN3 D A D A synchronization / Interpolation (sync. 48kHz) (async. 5-50kHz) A D DACM_L DACM_R Volume D A Preem- phasis Prescale Automatic Soundselect Deemphasis: 50/75 ms DBX Panda1 Deemphasis: J17 A D Prescale AGC ANA_IN1+ ANA_IN2+ Standard and Sound Detection I2C Read Register DEMODULATOR (incl. Carrier Mute) Decoded Standards: NICAM AM BTSC EIA-J SAT FM-Radio FM/AM Stereo or A / B Stereo or A Stereo or B FM/AM NICAM ADR-Bus Interface I2S1 I2S3 SCART scale Mix2 scale Mix1 S SCART DSP Input Select SC1_OUT_L SC1_OUT_R SC2_OUT_L SC2_OUT_R SCART Output Select SCART1_L/R SCART2_L/R I2S Interface Prescale I2S_DA_IN2 I2S2 (sync. 48kHz) Mix1 Channel Matrix Mix2 Channel Matrix (sync. 48kHz) I2S_CL I2S_WS I2S_CL3 I2S_WS3 (16hex) (12hex) (11hex) (0Dhex) (0Ehex) (10hex) (08hex) (09hex) (0Bhex) (0Chex) (38hex) (39hex) (0Ahex) (41hex) (3ahex) (3bhex) (06hex) (07hex) (40hex) (00hex)(29hex) (34hex) Beeper S S (14hex) Fig. 2–1:Signal flow block diagram of the MSP 34x8G (input and output names correspond to pin names)
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 9 2.1. Architecture of the MSP 34x8G Family Fig. 2–1 on page 8 shows a simplified block diagram of the IC. The block diagram contains all features of the MSP 3458G. Other members of the MSP 34x8G fam- ily do not have the complete set of features, handling only a subset of the standards. 2.2. Sound IF Processing 2.2.1. Analog Sound IF Input The input pins ANA_IN1+, ANA_IN2+, and ANA_IN- offer the possibility to connect two different sound IF (SIF) sources to the MSP 34x8G. The preselected sound IF signal is fed into an A/D-converter. An analog automatic gain circuit (AGC) allows a wide range of input levels. The highpass filters, formed by the cou- pling capacitors at pins ANA_IN1+ and ANA_IN2+ (see Section 7. “Appendix C: Application Circuit” on page 83), are sufficient in most cases to suppress video components. Some combinations of SAW filters and sound IF mixer ICs, however, show large picture components on their outputs. In this case, further filter- ing is recommended. 2.2.2. Demodulator: Standards and Features The MSP 34x8G is able to demodulate all TV-sound standards worldwide including the digital NICAM sys- tem. Depending on the MSP 34x8G version, the fol- lowing demodulation modes can be performed: A2 Systems: Detection and demodulation of two sep- arate FM carriers (FM1 and FM2), demodulation and evaluation of the identification signal of carrier FM2. NICAM Systems: (Only possible in the MSP 3418G and MSP 3458G). Demodulation and decoding of the NICAM carrier, detection and demodulation of the ana- log (FM or AM) carrier. For D/K-NICAM, the FM carrier may have a maximum deviation of 384 kHz. Very high deviation FM-Mono: Detection and robust demodulation of one FM carrier with a maximum devi- ation of 540 kHz. BTSC-Stereo: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detec- tion and evaluation of the pilot carrier, AM demodula- tion of the (L-R)-carrier and detection of the SAP sub- carrier. Processing of the DBX noise reduction. BTSC-Mono + SAP: Detection and FM demodulation of the aural carrier resulting in the MTS/MPX signal. Detection and evaluation of the pilot carrier, detection and FM demodulation of the SAP subcarrier. Process- ing of the DBX noise reduction. Japan Stereo: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Demodulation and evaluation of the identification signal and FM demodulation of the (L-R)-carrier. FM-Satellite Sound: Demodulation of one or two FM carriers. Processing of high-deviation mono or narrow bandwidth mono, stereo, or bilingual satellite sound according to the ASTRA specification. FM-Stereo-Radio: Detection and FM demodulation of the aural carrier resulting in the MPX signal. Detection and evaluation of the pilot carrier and AM demodula- tion of the (L-R)-carrier. The demodulator blocks of all MSP 34x8G versions have identical user interfaces. Even completely differ- ent systems like the BTSC and NICAM systems are controlled the same way. Standards are selected by means of MSP Standard Codes. Automatic processes handle standard detection and identification without controller interaction. The key features of the MSP 34x8G demodulator blocks are described below. Standard Selection: The controlling of the demodula- tor is minimized: All parameters, such as tuning fre- quencies or filter bandwidth, are adjusted automati- cally by transmitting one single value to the STANDARD SELECT register. For all standards, spe- cific MSP standard codes are defined. Automatic Standard Detection: If the TV sound stan- dard is unknown, the MSP 34x8G can automatically detect the actual standard, switch to that standard, and respond the actual MSP standard code. Automatic Carrier Mute: To prevent noise effects or FM identification problems in the absence of an FM carrier, the MSP 34x8G offers a carrier mute feature, which is activated automatically if the standard is selected by means of the STANDARD SELECT regis- ter. If no FM carrier is available at one of the two MSP demodulator channels, the corresponding demodula- tor output is muted.
MSP 3438G PRELIMINARY DATA SHEET
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2.2.3. Preprocessing of Demodulator Signals All demodulated signals must be processed by a deemphasis filter and adjusted in level (analog signals must also be dematrixed). The correct deemphasis fil- ters are already selected by setting the standard in the STANDARD SELECT register. The level adjustment has to be done by means of the FM/AM and NICAM prescale registers. The necessary dematrix function depends on the selected sound standard and the actual broadcasted sound mode (mono, stereo, or bilingual). It can be manually set by the FM Matrix Mode register or automatically set by the Automatic Sound Selection. 2.2.4. Automatic Sound Select In the Automatic Sound Select mode, the dematrix function is automatically selected based on the identifi- cation information in the STATUS register. No I interaction is necessary when the broadcasted sound mode changes (e.g. from mono to stereo). The demodulator supports the identification check by switching between mono compatible standards (stan- dards that have the same FM mono carrier) automati- cally and non-audible. If B/G-FM or B/G-NICAM is selected, the MSP will switch between these stan- dards. The same action is performed for the stan- dards: D/K1-FM, D/K2-FM, and D/K-NICAM. Switching is only done in the absence of any stereo or bilingual identification. If identification is found, the MSP keeps the detected standard. In case of high bit-error rates, the MSP 34x8G auto- matically falls back from digital NICAM sound to ana- log FM or AM mono. Table 2–1 summarizes all actions that take place when Automatic Sound Select is switched on. To provide more flexibility, the Automatic Sound Select block prepares four different source channels of demodulated sound (Fig 2–3). By choosing one of the four demodulator channels, the preferred sound mode can be selected by means of the Source Select regis- ters, independent for all MSP-outputs. The following source channels of demodulated sound are defined: – “FM/AM” channel: Analog mono sound, stereo if available. In case of NICAM, analog mono only (FM or AM mono). – “Stereo or A/B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains both languages A (left) and B (right). – “Stereo or A” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains language A (on left and right). – “Stereo or B” channel: Analog or digital mono sound, stereo if available. In case of bilingual broad- cast, it contains language B (on left and right). Fig. 2–2 shows the source channel assignment of demodulated signals in case of manual mode. If man- ual mode is required, more information can be found in the section “Demodulator Source Channels in Manual Mode” on page 80. Fig. 2–3 and Table 2–2 show the source channel assignment of the demodulated sig- nals in case of Automatic Sound Select mode for all sound standards. Note: The analog primary input channel contains the signal of the mono FM/AM carrier or the L+R signal of the MPX carrier. The secondary input channel contains the signal of the second FM carrier, the L-R signal of the MPX carrier, or the SAP signal. Fig. 2–2:Source channel assignment of demodulated signals in Manual Mode Fig. 2–3:Source channel assignment of demodulated signals in Automatic Sound Select Mode 2.3. Preprocessing for SCART and I 2S Input Signals The SCART and I2S inputs need only be adjusted in level by means of the SCART and I2S prescale regis- ters. Prescale Source Select primary channel secondary channel NICAM A NICAM B FM/AM Prescale NICAM FM/AM (Stereo or A/B) FM-Matrix NICAM LS Ch. Matrix SC2 Ch. Matrix Output-Ch. Matrices must be set according the standard Prescale Automatic Sound Select Source SelectNICAM A NICAM B FM/AM Prescale NICAM FM/AM Stereo or A/B Stereo or A Stereo or B primary channel secondary channel LS Ch. Matrix SC2 Ch. Matrix Output-Oh. Matrices must be set once to stereo
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 11 Table 2–1:Performed actions of the Automatic Sound Selection Selected TV Sound Standard Performed Actions B/G-FM, D/K-FM, M-Korea, and M-Japan Evaluation of the identification signal and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. Identification is acquired after 500 ms. B/G-NICAM, L-NICAM, I-NICAM, and D/K-NICAM Evaluation of NICAM-C-bits and automatic switching to mono, stereo, or bilingual. Preparing four demodulator source channels according to Table 2–2. NICAM detection is acquired within 150 ms. In case of bad or no NICAM reception, the MSP switches automatically to FM/AM mono and switches back to NICAM if possible. A hysteresis prevents periodical switching. B/G-FM, B/G-NICAM or D/K1-FM, D/K2-FM, D/K-NICAM Automatic searching for stereo/bilingual-identification in case of mono transmission. Automatic and non- audible changes between Dual-FM and FM-NICAM standards while listening to the basic FM-Mono sound carrier. Example: If starting with B/G-FM-Stereo, there will be a periodical alternation to B/G-NICAM in the absence of FM-Stereo/Bilingual or NICAM-identification. Once an identification is detected, the MSP keeps the corresponding standard. M-BTSC-STEREO, FM Radio Evaluation of the pilot signal and automatic switching to mono or stereo. Preparing four demodulator source channels according to Table 2–2. Detection of the SAP carrier. Pilot detection is acquired after 200 ms. M-BTSC-SAP In the absence of SAP, the MSP switches to BTSC-Stereo if available. If SAP is detected, the MSP switches automatically to SAP (see Table 2–2). Table 2–2:Sound modes for the demodulator source channels with Automatic Sound Select Source Channels in Automatic Sound Select Mode Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) M-Korea B/G-FM D/K-FM M-Japan 03, 08 04, 05, 0B1) MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo BILINGUAL: Languages A and B Left = A Right = B Left = A Right = B AB B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) 08, 032) 0B, 04 2), 052) NICAM not available or error rate too high analog Mono analog Mono analog Mono analog Mono MONO analog Mono NICAM Mono NICAM Mono NICAM Mono STEREO analog Mono NICAM Stereo NICAM Stereo NICAM Stereo BILINGUAL: Languages A and B analog Mono Left = NICAM A Right = NICAM B NICAM A NICAM B M-BTSC 20, 21 MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo
20 MONO+SAP Mono Mono Mono Mono
STEREO+SAP Stereo Stereo Stereo Stereo
21 MONO+SAP Left = Mono
Right = SAP Left = Mono Right = SAP Mono SAP STEREO+SAP Left = Mono Right = SAP Left = Mono Right = SAP Mono SAP FM Radio 40 MONO Mono Mono Mono Mono STEREO Stereo Stereo Stereo Stereo 1) The Automatic Sound Select process will automatically switch to the mono compatible analog standard. 2) The Automatic Sound Select process will automatically switch to the mono compatible digital standard. 3) The MSP Standard Codes are defined in Table 3–6 on page 20.
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2.4. Source Selection and Output Channel Matrix The Source Selector makes it possible to distribute all source signals (one of the demodulator source chan- nels, SCART, or I2S input) to the desired output chan- nels (loudspeaker, Aux, etc.). All input and output sig- nals can be processed simultaneously. Each source channel is identified by a unique source address. For each output channel, the output channel matrix can be set to sound A, sound B, stereo, or mono. If Automatic Sound Select is on, the output channel matrix can stay fixed to stereo (transparent) for demodulated signals. 2.4.1. Mixing Unit Any source can be selected as the input for the two channels of the Mixing unit. The mixer channel matri- ces and the scaling factors can be programmed sepa- rately for each channel. After adding up both channels, the signal is fed back and is available as source 15 (Mix output) of the Source Selector. 2.5. Audio Baseband Processing 2.5.1. Automatic Volume Correction (AVC) Different sound sources (e.g. terrestrial channels, SAT channels, or SCART) fairly often do not have the same volume level. Advertisements during movies usually have a higher volume level than the movie itself. This results in annoying volume changes. The AVC solves this problem by equalizing the volume level. To prevent clipping, the AVC’s gain decreases quickly in dynamic boost conditions. To suppress oscillation effects, the gain increases rather slowly for low-level inputs. The decay time is programmable by the AVC register (see page 28). For input signals ranging from -24 dBr to 0 dBr, the AVC maintains a fixed output level of -18 dBr. Fig. 2–4 shows the AVC output level versus its input level. For prescale and volume registers set to 0 dB, a level of 0 dBr corresponds to full scale input / output. This is: – SCART in-, output 0 dBr = 2.0 V rms – Loudspeaker and Aux output 0 dBr = 1.4 Vrms Fig. 2–4:Simplified AVC characteristics 2.5.2. Loudspeaker and Aux Outputs The Loudspeaker and Aux output channels are adjust- able in volume. A square wave beeper with adjustable frequency and volume can be added to them. 2.5.3. Quasi-Peak Detector The Quasi-Peak Readout register can be used to read out the quasi-peak level of any input source. The fea- ture is based on following filter time constants: – attack time: 1.3 ms – decay time: 37 ms input level -18 -24 -12 output level [dBr] [dBr]
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 13 2.6. SCART Signal Routing 2.6.1. SCART DSP In and SCART Out Select The SCART DSP Input Select and SCART Output Select blocks include full matrix switching facilities. To design a TV set with four pairs of SCART-inputs and two pairs of SCART-outputs, no external switching hardware is required. The switches are controlled by the ACB user register (see page 30). 2.6.2. Stand-by Mode If the MSP 34x8G is switched off by first pulling STANDBYQ low and then (after >1ms delay) switching off the 5-V, but keeping the 8-V power supply (‘Stand- by’-mode), the SCART switches maintain their posi- tion and function. This allows the copying from selected SCART-inputs to SCART-outputs in the TV set’s stand-by mode. In case of power on or starting from stand-by (see details on the power-up sequence in Fig. 4–22 on page 55), all internal registers except the ACB register (page 30) are reset to the default configuration (see Table 3–4 on page 18). The reset position of the ACB register becomes active after the first I 2C transmission into the Baseband Processing part (subaddress hex). By transmitting the ACB register first, the reset state can be redefined. 2.7. I2S Bus Interfaces Routing can be done with each input source and out- put channel via the I2S inputs and outputs. The MSP 34x8G has two different kinds of interfaces: syn- chronous master/slave input/output interfaces running on 48 kHz and an asynchronous slave interface, which is capable of dealing with arbitrary sample rates rang- ing from 5...50 kHz. All interfaces support two possible formats: 1. The SONY format: I 2S Wordstrobe changes at the word boundaries. 2. The PHILIPS format: I2S Wordstrobe changes one I2S Clock period before the word boundaries. All I2S options can be set by means of the MODUS register (see page 23). The I2S_DA_IN2/3 pin is used in the PQFP80 pack- age as a second synchronous interface data input. The asynchronous data input of the PQFP80 is I2S_DA_IN3. In the PLCC and PSDIP packages, the I2S_DA_IN2/3 serves as an asynchronous data input. 2.7.1. Synchronous I 2S-Interface(s) The synchronous I2S bus interface consists of the pins: – I2S_DA_IN1, (I2S_DA_IN2/3 for PQFP80 package): signals are accepted, in the format: two channels per line, 2*16 bits per sampling cycle (48 kHz), MSB first. –I 2 S _ D A _ O U T : For output, two channels. 2*16 bits per sampling cycle (48 kHz) are transmitted. – I2S_CL: Gives the timing for the transmission of I 2S serial data. –I 2 S _ W S : The word strobe line defines the left and right sam- ple. If the MSP 34x8G serves as the master on the I2S interface, the clock and word strobe lines are driven by the MSP. In slave mode, these lines are input to the MSP 34x8G and the MSP clock is synchronized to 384 times the I2S_WS rate (48 kHz). NICAM operation is not possible in slave mode. An I 2S timing diagram is shown in Fig. 4–24 on page 58. 2.7.2. Asynchronous I2S-Interface The following pins are used for the asynchronous I2S bus interface: – I2S_WS3 (serves only as input) – I2S_CL3 (serves only as input) – I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package). The interface accepts I 2S-input streams with MSB first and with sample widths of 16,18...32 bits. With Sony/ Philips, left/right alignment and Wordstrobe polarity, there are additional parameters available for the adap- tion to a variety of formats in the MODUS register (see page 23). Synchronization is performed by means of an adaptive sample rate converter, which interpolates sound sig- nals with arbitrary input sample rates in the range of 5...50 kHz to 48 kHz data. The complete digital base- band processing is exclusively performed with 48 kHz.
MSP 3438G PRELIMINARY DATA SHEET
14 MICRONAS INTERMETALL
2.8. ADR Bus Interface For the ASTRA Digital Radio System (ADR), the MSP 3408G, MSP 3418G, and MSP 3458G performs preprocessing such as carrier selection and filtering. Via the 3-line ADR-bus, the resulting signals are trans- ferred to the DRP 3510A coprocessor, where the source decoding is performed. To be prepared for an upgrade to ADR with an additional DRP board, the fol- lowing lines of MSP 34x8G should be provided on a feature connector: – AUD_CL_OUT – I2S_DA_IN1, 2, or 3 – I2S_DA_OUT, I2S_WS, I2S_CL – ADR_CL, ADR_WS, ADR_DA For more details, please refer to the DRP 3510A data sheet. 2.9. Digital Control I/O Pins and Status Change Indication The static level of the digital input/output pins D_CTR_I/O_0/1 is switchable between HIGH and LOW via the I 2C-bus by means of the ACB register (see page 30). This enables the controlling of external hardware switches or other devices via I2C-bus. The digital input/output pins can be set to high imped- ance by means of the MODUS register (see page 23). In this mode, the pins can be used as input. The cur- rent state can be read out of the STATUS register (see page 24). Optionally, the pin D_CTR_I/O_1 can be used as an interrupt request signal to the controller, indicating any changes in the read register STATUS. This makes poll- ing unnecessary, I 2C bus interactions are reduced to a minimum (see STATUS register on page 24 and MODUS register on page 23). 2.10. Preemphasis When using the Aux output for feeding an external modulator, a preemphasis can be applied to the right channel. The signal is scaled down by -3 dB. An overmodula- tion protection is included in the algorithm which limits the output signal to 0 dBFS. Due to the nature of a pre- emphasis, its gain at high frequencies exceeds 3 dB. Thus, even with 0 dB input signals and prescaler / vol- ume set to 0 dB, clipping can occur. There are three modes present: preemphasis off, 50 ms, and 75ms. (see Table 3–10 on page 25) for the register settings. 2.11. Clock PLL Oscillator and Crystal Specifications The MSP 34x8G derives all internal system clocks from the 18.432 MHz oscillator. In NICAM or in I 2S- Slave mode of the synchronous interface, the clock is phase-locked to the corresponding source. Therefore, it is not possible to use NICAM and I 2S-Slave mode of the synchronous interface at the same time. For proper performance, the MSP clock oscillator requires a 18.432-MHz crystal. Note that for the phase-locked modes (NICAM, I 2S-Slave), crystals with tighter tolerance are required. Please note also, that the asynchronous I 2S3 slave interface uses a different locking mechanism and does not require tighter crystal tolerances. Remark on using the crystal: External capacitors at each crystal pin to ground are required. They are necessary for tuning the open-loop frequency of the internal PLL and for stabilizing the fre- quency in closed-loop operation. The higher the capacitors, the lower the resulting clock frequency. The nominal free running frequency should match 18.432 MHz as closely as possible. Clock measurements should be done at pin AUD_CL_OUT. This pin must be activated for this pur- pose (see Table 3–8 on page 22).
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 15 3. Control Interface 3.1. I2C Bus Interface 3.1.1. Device and Subaddresses The MSP 34x8G is controlled via the I2C bus slave interface. The IC is selected by transmitting one of the MSP 34x8G device addresses. In order to allow up to three MSP ICs to be connected to a single bus, an address select pin (ADR_SEL) has been implemented. With ADR_SEL pulled to high, low, or left open, the MSP 34x8G responds to different device addresses. A device address pair is defined as a write address (80, 84, or 88 hex) and a read address (81, 85, or 89 hex) (see Table 3–1). Writing is done by sending the device write address, followed by the subaddress byte, two address bytes, and two data bytes. Reading is done by sending the write device address, followed by the subaddress byte and two address bytes. Without sending a stop condi- tion, reading of the addressed data is completed by sending the device read address (81, 85, or 89 hex) and reading two bytes of data. Refer to section 3.1.2. for the I 2C bus protocol and to section “Programming Tips” on page 33 for proposals of MSP 34x8G I2C tele- grams. See Table 3–2 for a list of available subad- dresses. By means of the RESET bit in the CONTROL register, the MSP can be reset by the controller. Due to the internal architecture of the MSP 34x8G, the IC cannot react immediately to an I 2C request. The typical response time is about 0.3 ms. If the MSP can- not accept another complete byte of data until it has performed some other function (for example, servicing an internal interrupt), it will hold the clock line I2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by ‘Wait’ in section 3.1.2. The maximum wait period of the MSP during normal operation mode is less than 1 ms. Hardware problem handling: In case of any hardware problems (e.g. interruption of the power supply of the MSP), the MSP’s wait period is extended to 1.8 ms. After this time, the MSP does NOT send the acknowledge bit after the device address. The data line will be left HIGH by the MSP and the clock line will be released. The master can then generate a STOP condition to abort the transfer. The master is able to recognize the error state by the missing acknowledge bit from the MSP. The MSP can be reset via I 2C-bus by means of the CONTROL regis- ter. While transmitting the reset protocol to ‘CON- TROL’, the master must ignore the missing acknowl- edge bits (NAK) from the MSP . A general timing diagram of the I 2C Bus is shown in Fig. 4–23 on page 56. Table 3–1:I2C Bus Device Addresses ADR_SEL Low High Left Open Mode Write Read Write Read Write Read MSP device address 80 hex 81 hex 84 hex 85 hex 88 hex 89 hex Table 3–2:I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Write software reset of MSP (see Table 3–3) TEST 0000 0001 01 Write only for internal use WR_DEM 0001 0000 10 Write write address demodulator RD_DEM 0001 0001 11 Write read address demodulator WR_DSP 0001 0010 12 Write write address DSP RD_DSP 0001 0011 13 Write read address DSP
MSP 3438G PRELIMINARY DATA SHEET
16 MICRONAS INTERMETALL
3.1.2. Protocol Description Write to DSP or Demodulator Read from DSP or Demodulator Write to Control or Test Registers Note: S = I 2C-Bus Start Condition from master P = I 2C-Bus Stop Condition from master ACK = Acknowledge-Bit: LOW on I2C_DA from slave (= MSP, light gray) or master (= controller dark gray) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’ or from MSP indicating internal error state Wait = I2C-Clock line is held low, while the MSP is processing the I2C command. This waiting time is max. 1 ms. Fig. 3–1:I2C bus protocol (MSB first; data must be stable while clock is high) Table 3–3:Control Register (Subaddress: 00hex) Name Subaddress 15 (MSB) 14 13..1 0 (LSB) CONTROL 00 hex 1 : RESET 0 : normal 000 Sw r i t e device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK data-byte- high ACK data-byte low ACK P Sw r i t e device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S read device address Wait ACK data-byte- high ACK data-byte low NAK P Sw r i t e device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P S P I2C_DA I2C_CL
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 17 3.1.3. Proposals for General MSP 34x8G I2C Telegrams 3.1.3.1. Symbols dawwrite device address (80hex, 84hex or 88hex) darread device address (81hex, 85hex or 89hex) < Start Condition > Stop Condition aa Address Byte dd Data Byte 3.1.3.2. Write Telegrams <daw 00 d0 00>write to CONTROL register <daw 10 aa aa dd dd>write data into demodulator <daw 12 aa aa dd dd>write data into DSP 3.1.3.3. Read Telegrams <daw 11 aa aa <dar dd dd>read data from demodulator <daw 13 aa aa <dar dd dd>read data from DSP 3.1.3.4. Examples <80 00 80 00>RESET MSP statically <80 00 00 00>Clear RESET <80 10 00 20 00 03>Set demodulator to stand. 03hex <80 11 02 00 <81 dd dd>Read STATUS <80 12 00 08 01 20>Set loudspeaker channel source to NICAM and Matrix to STEREO More examples of typical application protocols are listed in section “Programming Tips” on page 33. 3.2. Start-Up Sequence: Power-Up and I2C Controlling After POWER ON or RESET (see Fig. 4–22), the IC is in an inactive state. All registers are in the reset posi- tion (see tables 3–4 and 3–5), the analog outputs are muted. The controller has to initialize all registers for which a non-default setting is necessary. 3.3. MSP 34x8G Programming Interface 3.3.1. User Registers Overview The MSP 34x8G is controlled by means of user regis- ters. The complete list of all user registers is given in the following tables. The registers are partitioned into the Demodulator section (Subaddress 10 hex for writ- ing, 11hex for reading) and the Baseband Processing sections (Subaddress 12hex for writing, 13hex for read- ing). Write and read registers are 16-bit wide, whereby the MSB is denoted bit [15]. Transmissions via I2C bus have to take place in 16-bit words (two byte transfers, with the most significant byte transferred first). All write regis- ters, except the demodulator write registers, are readable. Unused parts of the 16-bit write registers must be zero. Addresses not given in this table must not be written. An overview of all MSP 34x8G Write Registers is shown in Table 3–4; all Read Registers are given in Table 3–5. To provide more flexibility and for reasons of software compatibility to the MSP 34x0D, an Expert/Compatibil- ity Mode is available. Additional read and write regis- ters, together with a detailed description of the expert mode, can be found in the “Appendix B: Manual Mode” on page 72.
MSP 3438G PRELIMINARY DATA SHEET
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Table 3–4:List of MSP 34x8G Write Registers Write Register Address (hex) Bits Description and Adjustable Range Reset See Page I2C Subaddress = 10hex ; Registers are not readable STANDARD SELECT 00 20 [15..0] Initial Programming of complete Demodulator 00 00 21 MODUS 00 30 [15..0] Demodulator, Automatic and I 2S options 00 00 22 I2C Subaddress = 12hex ; Registers are all readable by using I2C Subaddress = 13hex [7..5] [4..0] 1/8 dB Steps must be set to 0 000bin 00000bin [7..5] [4..0] 1/8 dB Steps must be set to 0 000bin 00000bin Loudspeaker source select 00 08 [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 Loudspeaker channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 Aux source select 00 09 [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 Aux channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 SCART1 source select 00 0A [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 SCART1 channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 I2S source select 00 0B [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 I2S channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 Quasi-peak detector source select 00 0C [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 Quasi-peak detector matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 Prescale SCART input 00 0D [15..8] [00 hex ... 7Fhex]0 0 hex 26 FM matrix [7..0] [NO_MAT, GSTEREO, KSTEREO] NO_MAT 26 Automatic Volume Correction 00 29 [15..8] [off, on, decay time] off 28 Aux Preemphasis on right channel 00 34 [15..8] [OFF, 50µs, 75µs] OFF 28 Mix1 source select 00 38 [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 Mix1 channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 Mix2 source select 00 39 [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM/AM 27 Mix2 channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 19 SCART2 source select 00 41 [15..8] [FM/AM, NICAM, SCART, I 2S1..3, Mix output] FM 27 SCART2 channel matrix [7..0] [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA 27 Table 3–5:List of MSP 34x8G Read Registers Read Register Address (hex) Bits Description and Adjustable Range See Page I2C Subaddress = 11hex ; Registers are not writable STANDARD RESULT 00 7E [15..0] Result of Automatic Standard Detection (see Table 3–7) 24 I2C Subaddress = 13hex ; Registers are not writable Table 3–4:List of MSP 34x8G Write Registers, continued Write Register Address (hex) Bits Description and Adjustable Range Reset See Page
MSP 3438G PRELIMINARY DATA SHEET
20 MICRONAS INTERMETALL
3.3.2. Description of User Registers Table 3–6:Standard Codes for STANDARD SELECT register MSP Standard Code (Data in hex) TV Sound Standard Sound Carrier Frequencies in MHz MSP 34x8G Version Automatic Standard Detection 00 01 Start Automatic Standard Detection all Standard Selection 00 02 M-Dual FM-Stereo 4.5/4.724212 3408, 3418, 3448, 3458 00 03 B/G -Dual FM-Stereo 1) 5.5/5.7421875 3408, 3418, 3458 00 04 D/K1-Dual FM-Stereo 2) 6.5/6.2578125 00 05 D/K2-Dual FM-Stereo 2) 6.5/6.7421875 00 06 D/K -FM-Mono with HDEV3 3), not detectable by Automatic Standard Detection, for China HDEV3 3) SAT-Mono (i.e. Eutelsat, s. Table 6–11) 6.5 00 07 D/K3-Dual FM-Stereo 6.5/5.7421875 3408, 3418, 3458 00 08 B/G -NICAM-FM 1) 5.5/5.85 3418, 3458 00 09 L -NICAM-AM 6.5/5.85 00 0A I -NICAM-FM 6.0/6.552 00 0B D/K -NICAM-FM 2) 6.5/5.85 00 0C D/K -NICAM-FM with HDEV2 4), not detectable by Automatic Standard Detection, for China 6.5/5.85 00 0D D/K -NICAM-FM with HDEV3 3), not detectable by Automatic Standard Detection, for China 6.5/5.85 3418, 3458 00 20 M-BTSC-Stereo 4.5 3438, 3448, 3458 00 21 M-BTSC-Mono + SAP 00 30 M-EIA-J Japan Stereo 4.5 3448, 3458 00 40 FM-Stereo Radio 10.7 3438, 3448, 3458 00 50 SAT-Mono (s. Table 6–11) 6.5 3408, 3418, 3458 00 51 SAT-Stereo (s. Table 6–11) 7.02/7.20 3408, 3418, 3458 00 60 SAT ADR (Astra Digital Radio) 7.2 3408, 3418, 3458 1) In case of Automatic Sound Select, the B/G-codes 3hex and 8hex are equivalent. 2) In case of Automatic Sound Select, the D/K-codes 4hex, 5hex and Bhex are equivalent. 3) HDEV3: Max. FM deviation must not exceed 540 kHz 4) HDEV2: Max. FM deviation must not exceed 360 kHz
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 21 3.3.2.1. STANDARD SELECT Register The TV sound standard of the MSP 34x8G demodula- tor is determined by the STANDARD SELECT Regis- ter. There are two ways to use the STANDARD SELECT Register: – Setting up the demodulator for a TV sound standard by sending the corresponding standard code with a single I 2C-Bus transmission. – Starting the Automatic Standard Detection for ter- restrial TV standards. This is the most comfortable way to set up the demodulator. Within 0.5 s, the detection and set-up of the actual TV sound stan- dard is performed. The detected standard can be read out of the STANDARD RESULT register by the control processor. This feature is recommended for the primary set-up of a TV set. Outputs should be muted during Automatic Standard Detection. The Standard Codes are listed in Table 3–6. Selecting a TV sound standard via the STANDARD SELECT register initializes the demodulator. This includes: AGC, tuning frequency, band-pass filters, demodulation mode (FM, AM, or NICAM), carrier mute, deemphasis, and identification mode. If a present sound standard is impossible for a specific MSP version, it switches to the analog mono sound of this standard. In that case, stereo or bilingual process- ing will not be possible. For a complete setup of the TV sound processing from analog IF input to the source selection, the following transmissions are necessary: MODUS register, STAN- DARD SELECT register, prescale values, FM matrix. Note: The FM matrix is set automatically if Automatic Sound Select is active (MODUS[0]=1). In this case, the FM matrix will be initialized with “Sound A Mono”. Dur- ing operation, the FM matrix will be automatically selected according to the actual identification informa- tion. 3.3.2.2. STANDARD RESULT Register If Automatic Standard Detection is selected in the STANDARD SELECT register, status and result of the Automatic Standard Detection process can be read out of the STANDARD RESULT register. The possible results are based on the mentioned Standard Code and are listed in Table 3–7. In cases where no sound standard has been detected (no standard present, too much noise, strong interfer- ers, etc.) the STANDARD RESULT register contains 00 00 hex. In that case, the controller has to start further actions (for example, set the standard according to a preference list or by manual input). As long as the STANDARD RESULT register contains a value greater than 07 FFhex, the Automatic Standard Detection is still active. During this period, the MODUS and STANDARD SELECT register must not be written. The STATUS register will be updated when the Auto- matic Standard Detection has finished. If a present sound standard is impossible for a specific MSP version, it detects and switches to the analog mono sound of this standard. Example: The MSPs 3438G and 3448G will detect a B/G-NICAM signal as standard 3 and will switch to the analog FM- Mono sound. Table 3–7:Results of the Automatic Standard Detection Broadcasted Sound Standard STANDARD RESULT Register Read 007E hex Automatic Standard Detection could not find a sound standard 0000 hex B/G-FM 0003 hex B/G-NICAM 0008 hex I0 0 0 A hex FM-Radio 0040 hex M-Korea M-Japan M-BTSC 0002hex (if MODUS[14,13]=00) 0020hex (if MODUS[14,13]=01) 0030hex (if MODUS[14,13]=10) L-AM D/K1 D/K2 0009hex (if MODUS[12]=0) 0004hex (if MODUS[12]=1) L-NICAM D/K-NICAM 0009hex (if MODUS[12]=0) 000Bhex (if MODUS[12]=1) Automatic Standard Detection still active >07FF hex
MSP 3438G PRELIMINARY DATA SHEET
22 MICRONAS INTERMETALL
3.3.2.3. Write Registers on I2C Subaddress 10hex Table 3–8:Write Registers on I2C Subaddress 10hex Register Address Function Name STANDARD SELECTION 00 20hex STANDARD SELECTION Register Defines TV Sound or FM-Radio Standard bit [15:0] 00 01hex start Automatic Standard Detection 00 02hex Standard Codes (see Table 3–6)) ... 00 60hex STANDARD_SEL
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 23 MODUS 00 30hex MODUS Register General MSP 34x8G Options bit [0] 0/1 off/on: Automatic Sound Select bit [1] 0/1 disable/enable STATUS change indication by means of the digital I/O pin D_CTR_I/O_1 Necessary condition: MODUS[3] = 0 (active) bit [2] 0 undefined, must be 0 bit [3] state of digital output pins D_CTR_I/O_0 and _1 0 active: D_CTR_I/O_0 and _1 are output pins (can be set by means of the ACB register. see also: MODUS[1]) 1 tristate: D_CTR_I/O_0 and _1 are input pins (level can be read out of STATUS[4,3]) bit [4] 0/1 active/tristate state of I 2S output pins bit [5] 0/1 master/slave mode of I 2S interface (must be set to 0 (= Master) in case of NICAM mode) bit [6] 0/1 Sony/Philips format of I2S word strobe I2S_WS (syn- chronous I2S) bit [7] 0/1 active/tristate state of audio clock output pin AUD_CL_OUT bit [8] 0/1 ANA_IN_1 +/ANA_IN_2+; select analog sound IF input pin bit [9] 0/1 Sony/Philips format of I2S word strobe I2S_WS3 (affects asynchronous I2S). Must be 0 for right aligned data ([11]=1) bit [10] 0/1 WS=0: left, WS=1: right / WS=0: right, WS=1: left Word strobe polarity (affects asynchronous I2S only) bit [11] 0/1 left aligned (16, 18...32 bit)/right aligned (16 bit) data (affects asynchronous I2S only) Preference in Automatic Standard Detection: bit [12] detected 6.5 MHz carrier is interpreted as:1) 0 standard L (SECAM) 1 standard D/K1, D/K2, or D/K NICAM bit [14:13] detected 4.5 MHz carrier is interpreted as:1) 0 standard M (Korea) 1 standard M (BTSC) 2 standard M (Japan) 3 Carrier at 4.5 MHz is ignored (chroma carrier) bit [15] 0 undefined, must be 0 MODUS 1) Valid at the next start of Automatic Standard Detection. Table 3–8:Write Registers on I2C Subaddress 10hex, continued Register Address Function Name
MSP 3438G PRELIMINARY DATA SHEET
24 MICRONAS INTERMETALL
3.3.2.4. Read Registers on I2C Subaddress 11hex Table 3–9:Read Registers on I2C Subaddress 11hex Register Address Function Name STANDARD RESULT 00 7Ehex STANDARD RESULT Register Readback of the detected TV Sound or FM-Radio Standard bit [15:0] 00 00hex Automatic Standard Detection could not find a sound standard 00 02hex MSP Standard Codes (see Table 3–7) ... 00 40hex >07 FFhex Automatic Standard Detection still active STANDARD_RES STATUS 02 00hex STATUS Register Contains all user relevant internal information about the status of the MSP bit [0] undefined bit [1] 0 detected primary carrier (Mono or MPX carrier) 1 no primary carrier detected bit [2] 0 detected secondary carrier (2nd A2 or SAP carrier) 1 no secondary carrier detected bit [3] 0/1 low/high level of digital I/O pin D_CTR_I/O_0 bit [4] 0/1 low/high level of digital I/O pin D_CTR_I/O_1 bit [5,9] 00 analog sound standard (FM or AM) active 01 not obtainable 10 digital sound (NICAM) available (MSP 3418G and MSP 3458G only) 11 bad reception condition of digital sound (NICAM) due to: a. high error rate b. unimplemented sound code c. data transmission only bit [6] 0/1 mono/stereo indication bit [7] 0/1 “1” indicates independent mono sound (only for NICAM on MSP 3418G and MSP 3458G) bit [8] 0/1 “1” indicates bilingual sound mode or SAP present bit [15:10] undefined If STATUS change indication is activated by means of MODUS[1]: Each change in the STATUS register sets the digital I/O pin D_CTR_I/O_1 to high level. Reading the STATUS register resets D_CTR_I/O_1. STATUS
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 25 3.3.2.5. Write Registers on I2C Subaddress 12hex Table 3–10:Write Registers on I2C Subaddress 12hex Register Address Function Name PREPROCESSING 00 0Ehex FM/AM Prescale bit [15:8] 00hex...7Fhex Defines the input prescale gain for the demodulated FM or AM signal 00hex off (RESET condition) For all FM modes except satellite FM, the below combinations of prescale value and FM deviation lead to internal full scale. FM mode bit [15:8] 7Fhex 28 kHz FM deviation 48hex 50 kHz FM deviation 30hex 75 kHz FM deviation 24hex 100 kHz FM deviation 18hex 150 kHz FM deviation 13hex 180 kHz FM deviation (limit) FM high deviation mode (HDEV2, MSP Standard Code = Chex) bit [15:8] 30hex 150 kHz FM deviation 14hex 360 kHz FM deviation (limit) FM very high deviation mode (HDEV3, MSP Standard Code = 6) bit [15:8] 20hex 450 kHz FM deviation 1Ahex 540 kHz FM deviation (limit) Satellite FM with adaptive deemphasis bit [15:8] 10hex recommendation AM mode (MSP Standard Code = 9) bit [15:8] 7Chex recommendation for SIF input levels from 0.1 Vpp to 0.8 Vpp (Due to the AGC switched on, the AM-output level remains stable and independent of the actual SIF-level in the mentioned input range) PRE_FM
MSP 3438G PRELIMINARY DATA SHEET
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(continued) 00 0Ehex FM Matrix Modes Defines the dematrix function for the demodulated FM signal bit [7:0] 00hex no matrix (used for bilingual and unmatrixed stereo sound) 01hex German stereo (Standard B/G) 02hex Korean stereo (also used for BTSC, EIA-J and FM Radio) 03hex sound A mono (left and right channel contain the mono sound of the FM/AM mono carrier) hex sound B mono (i.e. SAP) In case of Automatic Sound Select, the FM Matrix Mode is set automatically, i.e. the low-part of any I2C transmission to the register 00 0Ehex is ignored. To enable a Forced Mono Mode for all analog stereo systems by overriding the internal pilot or identification evaluation, the following steps must be transmitted: 1. MODUS with bit[0] = 0 (Automatic Sound Select off) 2. FM Presc./Matrix with FM Matrix = Sound A Mono (SAP: Sound B Mono) 3. Select FM/AM source channel, with channel matrix set to “Stereo” (transparent) FM_MATRIX 00 10hex NICAM Prescale Defines the input prescale value for the digital NICAM signal bit [15:8] 00hex ... 7Fhex prescale gain examples: hex off 20hex 0 dB gain 5Ahex 9 dB gain (recommendation) 7Fhex +12 dB gain (maximum gain) PRE_NICAM 00 16hex 00 12hex 00 11hex I2S1 Prescale I2S2 Prescale I2S3 Prescale Defines the input prescale value for digital I 2S input signals bit [15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 10hex 0 dB gain (recommendation) 7Fhex +18 dB gain (maximum gain) PRE_I2S1 PRE_I2S2 PRE_I2S3 00 0D hex SCART Input Prescale Defines the input prescale value for the analog SCART input signal bit [15:8] 00hex ... 7Fhex prescale gain examples: 00hex off 19hex 0 dB gain (2 VRMS input leads to digital full scale) 7Fhex +14 dB gain (400 mVRMS input leads to digital full scale) PRE_SCART Table 3–10:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 27 SOURCE SELECT AND OUTPUT CHANNEL MATRIX 00 08hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 00 38hex 00 39hex Source for: Loudspeaker Output Aux Output SCART1 DA Output SCART2 DA Output I 2S Output Quasi-Peak Detector Mix1 input Mix2 input bit [15:8] 0 “FM/AM”: demodulated FM or AM mono signal 1 “Stereo or A/B”: demodulator Stereo or A/B signal 3 “Stereo or A”: demodulator Stereo Sound or Language A (only defined for Automatic Sound Select) 4 “Stereo or B”: demodulator Stereo Sound or Language B (only defined for Automatic Sound Select)
2 SCART input
15 Mix output
For demodulator sources, see Table 2–2. SRC_MAIN SRC_AUX SRC_SCART1 SRC_SCART2 SRC_I2S SRC_QPEAK SRC_MIX1 SRC_MIX2 00 08 hex 00 09hex 00 0Ahex 00 41hex 00 0Bhex 00 0Chex 00 38hex 00 39hex Matrix Mode for: Loudspeaker Output Aux Output SCART1 DA Output SCART2 DA Output I 2S Output Quasi-Peak Detector Mix1 input Mix2 input bit [7:0] 00 hex Sound A Mono (or Left Mono) 10hex Sound B Mono (or Right Mono) 20hex Stereo (transparent mode) 30hex Mono (sum of left and right inputs divided by 2) More modes are listed in section 6.5.1. In Automatic Sound Select mode, the demodulator source channels are set according to Table 2–2. Therefore, the matrix modes of the corresponding out- put channels should be set to “Stereo” (transparent). MAT_MAIN MAT_AUX MAT_SCART1 MAT_SCART2 MAT_I2S MAT_QPEAK MAT_MIX1 MAT_MIX2 Table 3–10:Write Registers on I 2C Subaddress 12hex, continued Register Address Function Name
MSP 3438G PRELIMINARY DATA SHEET
28 MICRONAS INTERMETALL
LOUDSPEAKER AND AUX PROCESSING 00 00hex 00 06hex Volume Loudspeaker Volume Aux bit [15:8] volume table with 1 dB step size 7Fhex +12 dB (maximum volume) 7Ehex +11 dB ... hex +1d B 73hex 0d B 72hex -1d B ... 02hex -113 dB 01hex -114 dB 00hex Mute (reset condition) FFhex Fast Mute (needs about 75ms until the signal is com- pletely ramped down) bit [7:5] higher resolution volume table 0 +0d B 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit [4:0] not used must be set to 0 With large scale input signals, positive volume settings may lead to signal clipping. The MSP 34x8G loudspeaker and aux volume function is divided into a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. To turn volume on again, the volume step that has been used before Fast Mute was activated must be transmitted. VOL_MAIN VOL_AUX 00 29 hex Automatic Volume Correction (AVC) Loudspeaker Channel bit [15:12] 00hex AVC off (and reset internal variables) 08hex AVC on bit [11:8] 08hex 8 sec decay time 04hex 4 sec decay time 02hex 2 sec decay time 01hex 20 ms decay time (intended for quick adaptation to the average volume level after channel change) Note: To reset the internal variables, the AVC should be switched off and then on again during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Prologic mode. AVC 00 34 hex Preemphasis Aux Channel bit [15:8] 00hex Preemphasis OFF 7Fhex Preemphasis 50 µ (-3 dB scaling) FFhex Preemphasis 75 µ (-3 dB scaling) PREEMP_AUX Table 3–10:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 29 SCART OUTPUT CHANNEL 00 07hex 00 40hex Volume SCART1 Output Channel Volume SCART2 Output Channel bit [15:8] volume table with 1 dB step size 7Fhex +12 dB (maximum volume) 7Ehex +11 dB ... hex +1d B 73hex 0d B 72hex -1d B ... 02hex -113 dB 01hex -114 dB 00hex Mute (reset condition) bit [7:5] higher resolution volume table 0 +0 dB 1 +0.125 dB increase in addition to the volume table ... 7 +0.875 dB increase in addition to the volume table bit [4:0] 01hex this must be 01hex VOL_SCART1 VOL_SCART2 Table 3–10:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
MSP 3438G PRELIMINARY DATA SHEET
30 MICRONAS INTERMETALL
SCART SWITCHES AND DIGITAL I/O PINS 00 13hex ACB Register Defines the level of the digital output pins and the position of the SCART switches bit [15] 0/1 low/high of digital output pin D_CTR_I/O_0 (MODUS[3]=0) bit [14] 0/1 low/high of digital output pin D_CTR_I/O_1 (MODUS[3]=0) bit [13:5] SCART DSP Input Select xxxx00 xx0 SCART1 to DSP input (RESET position) xxxx01 xx0 MONO to DSP input (Sound A Mono must be selected in the channel matrix mode for the corresponding output channels) xxxx10 xx0 SCART2 to DSP input xxxx11 xx0 SCART3 to DSP input xxxx00 xx1 SCART4 to DSP input xxxx11 xx1 mute DSP input bit [13:5] SCART1 Output Select xx00xx x0x SCART3 input to SCART1 output (RESET position) xx01xx x0x SCART2 input to SCART1 output xx10xx x0x MONO input to SCART1 output xx11xx x0x SCART1 DA to SCART1 output xx00xx x1x SCART2 DA to SCART1 output xx01xx x1x SCART1 input to SCART1 output xx10xx x1x SCART4 input to SCART1 output xx11xx x1x mute SCART1 output bit [13:5] SCART2 Output Select 00xxxx 0xx SCART1 DA to SCART2 output (RESET position) 01xxxx 0xx SCART1 input to SCART2 output 10xxxx 0xx MONO input to SCART2 output 00xxxx 1xx SCART2 DA to SCART2 output 01xxxx 1xx SCART2 input to SCART2 output 10xxxx 1xx SCART3 input to SCART2 output 11xxxx 1xx SCART4 input to SCART2 output 11xxxx 0xx mute SCART2 output The RESET position becomes active at the time of the first write transmission on the control bus to the audio processing part. By writing to the ACB register first, the RESET state can be redefined. ACB_REG Table 3–10:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 31 3.3.2.6. Read Registers on I2C Subaddress 13hex MIXING UNIT 00 3Ahex 00 3Bhex Scale MIX1 Scale MIX2 Defines the input scale value for the digital mixing unit bit [15:8] 00hex off 20hex 50% (-6 dB gain) 40hex 100% (0 dB gain) 7Fhex 200% (+6 dB gain = maximum gain) Note: If the sum of both mixing inputs exceeds 100%, clipping may occur in the successive processing. VOL_MIX1 VOL_MIX2 BEEPER 00 14hex Beeper Volume and Frequency bit [15:8] Beeper Volume 00hex off 7Fhex maximum volume bit [7:0] Beeper Frequency 01hex 16 Hz (lowest) 40hex 1k H z FFhex 4k H z BEEPER Table 3–11:Read Registers on I2C Subaddress 13hex Register Address Function Name QUASI-PEAK DETECTOR READOUT 00 19hex 00 1Ahex Quasi-Peak Detector Readout Left Quasi-Peak Detector Readout Right QPEAK_L QPEAK_R Table 3–10:Write Registers on I2C Subaddress 12hex, continued Register Address Function Name
MSP 3438G PRELIMINARY DATA SHEET
32 MICRONAS INTERMETALL
ABC 1111A VERSION READOUT Registers 00 1Ehex MSP Hardware Version Code bit [15..8] 01hex MSP 34x8G - A2 A change in the hardware version code defines hardware optimizations that may have influence on the chip’s behavior. The readout of this register is iden- tical to the hardware version code in the chip’s imprint. MSP Major Revision Code bit [7..0] 07hex MSP 34x8G - A2 MSP_HARD MSP_REVISION 00 1Fhex MSP Product Code bit [15..8]08hex MSP 3408 G - A2 12hex MSP 3418 G - A2 26hex MSP 3438 G - A2 30hex MSP 3448 G - A2 3Ahex MSP 3458 G - A2 By means of the MSP-Product Code, the control processor is able to decide which TV sound standards have to be considered. MSP ROM Version Code bit [7..0] 42hex MSP 34x8G - A2 A change in the ROM version code defines internal software optimizations, that may have influence on the chip’s behavior, e.g. new features may have been included. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new MSP 34x8G versions according to this number. To avoid compatibility problems with MSP 3410B and MSP 34x0D, an offset of hex is added to the ROM version code of the chip’s imprint. MSP_PRODUCT MSP_ROM Table 3–11:Read Registers on I2C Subaddress 13hex, continued Register Address Function Name
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 33 3.4. Programming Tips This section describes the preferred method for initial- izing the MSP 34x8G. The initialization is grouped into four sections: analog signal path, demodulator input, input processing for SCART and I 2S, and output pro- cessing. See Fig. 2–1 on page 8 for a complete signal flow. SCART Signal Path 1. Select analog input for the SCART baseband pro- cessing (SCART DSP Input Select) by means of the ACB register. 2. Select the source for each analog SCART output (SCART Output Select) by means of the ACB regis- ter. Demodulator Input For a complete setup of the sound processing from analog IF input to the source selection, the following steps must be performed: 1. Set MODUS register to the preferred mode and Sound IF input. 2. Write STANDARD SELECT register. 3. Choose preferred prescale (FM and NICAM) values. If Automatic Sound Select is not active, the following step has to be done repeatedly: 4. Choose FM matrix according to the sound mode indicated in the STATUS register. SCART and I 2S Inputs 1. Select preferred prescale for SCART. 2. Select preferred prescale for I 2S inputs (set to 0 dB after RESET). Output Channels 1. Select the source channel and matrix for each out- put channel. 2. Set audio baseband features (i.e. AVC, 75ms pre- emphasis) 3. Select volume for each output channel. 3.5. Examples of Minimum Initialization Codes Initialization of the MSP 34x8G according to these list- ings reproduces sound of the selected standard on the loudspeaker output. All numbers are hexadecimal. The examples have the following structure: 1. Perform an I 2C controlled reset of the IC. 2. Write MODUS register (with Automatic Sound Select). 3. Write STANDARD SELECT register. 4. Set Prescale (FM and/or NICAM and dummy FM matrix). 5. Set Source Selection for loudspeaker channel (with matrix set to STEREO). 6. Set Volume loudspeaker channel to 0 dB. 3.5.1. B/G-FM (A2 or NICAM) < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 00 0 2 00 0 0 3 >// Standard Select: A2 B/G or NICAM B/G or < 8 01 00 0 2 00 0 0 8 > < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = MONO/SOUNDA < 8 01 20 0 1 00 0 5 A >// NICAM-Prescale = 5Ahex < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.2. BTSC-Stereo < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 00 0 2 00 0 2 0 >// Standard Select: BTSC-STEREO < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.3. BTSC-SAP with SAP at Loudspeaker Channel < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 00 0 2 00 0 2 1 >// Standard Select: BTSC-SAP < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 20 0 0 80 4 2 0 >// Source Sel. = (St or B) & Ch. Matr. = St < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB
MSP 3438G PRELIMINARY DATA SHEET
34 MICRONAS INTERMETALL
3.5.4. FM-Stereo Radio < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 00 0 2 00 0 4 0 >// Standard Select: FM-STEREO < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.5. Automatic Standard Detection < 8 00 08 0 0 0 > // Softreset < 8 00 00 0 0 0 > < 8 01 00 0 3 02 0 0 3 >// MODUS-Register: Automatic = on < 8 01 00 0 2 00 0 0 1 >// Standard Select: Automatic Standard Detection < 8 01 20 0 0 E2 4 0 3 >// FM/AM-Prescale = 24hex, FM-Matrix = Sound A Mono < 8 01 20 0 1 00 0 5 A >// NICAM-Prescale = 5Ahex < 8 01 20 0 0 80 3 2 0 >// Source Sel. = (St or A) & Ch. Matr. = St // Wait till STANDARD RESULT contains a value £ 07FF // IF STANDARD RESULT contains 0000 // do some error handling // ELSE < 8 01 20 0 0 07 3 0 0 >// Loudspeaker Volume 0 dB 3.5.6. Software Flow for Interrupt driven STATUS Check If the D_CTR_I/O_1 pin of the MSP 34x8G is con- nected to an interrupt input pin of the controller, the fol- lowing interrupt handler can be applied to be automati- cally called with each status change of the MSP 34x8G. The interrupt handler may adjust the TV display according to the new status information. Interrupt Handler: <80 11 02 00 <81 dd dd>// Read STATUS // adjust TV display with given status information // Return from Interrupt
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 35 4. Specifications 4.1. Outline Dimensions Fig. 4–1: 80-Pin Plastic Quad Flat Pack (PQFP80) Weight approximately 1.61 g Dimensions in mm Fig. 4–2: 64-Pin Plastic Low-Profile Quad Flat Pack (PLQFP64) Weight approximately 0.35 g Dimensions in mm 17.2 23.2 9.8 1.8 10.3 23 x 0.8 = 18.4 15 x 0.8 = 12.0 0.8 0.8 4164 241 1.28 2.70 1.8 0.13 –0.2 0.17–0.03 SPGS0025-1/1E 1.75 1.75 11 6 3348 D0025/2E 0.5 0.5 15 x 0.5 = 7.5 15 x 0.5 = 7.5 1.5 1.4 0.145 0.1 0.22
MSP 3438G PRELIMINARY DATA SHEET
36 MICRONAS INTERMETALL
Fig. 4–3: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm Fig. 4–4: 64-Pin Plastic Shrink Dual-Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm x 45°1.1 25.14 0.23 1.2 x 45° 16 x 1.27 = 20.32 24.2 4327 619 0.480.71 1.9 4.05 0.14.75 1.27 1.27 16 x 1.27 = 20.32 24.2 0.923.3 SPGS0027-2/1E 25.14 9 2 7.5 7.5 0.457 1.29 13 2 3364 30.3 1.9 (1) 1.778–0.05 1–0.1 57.7–0.1 3.2–0.4 3.8–0.1 4.8–0.4 19.3–0.1 18–0.1 20.1–0.5 0.27–0.06 SPGS0016-4/3E 31 x 1.778 = 55.118–0.1 2.5 0.3
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 37 4.2. Pin Connections and Short Descriptions NC = not connected (leave vacant for future compatibility reasons) TP = Test Pin (leave vacant - pin is used for production test only) LV = leave vacant OBL = obligatory; connect as described in application circuit diagram Pin No. Pin Name Type Connection (if not used) Short Description PQFP 80-pin PLQFP 64-pin PLCC 68-pin PSDIP 64-pin 1 6 41 08 N C L V N o t c o n n e c t e d 2199I 2 C _ C L I N / O U T O B L I 2C clock 3 2 8 10 I2C_DA IN/OUT OBL I 2C data 4 3 7 11 I2S_CL IN/OUT LV I 2S clock 5 4 6 12 I2S_WS IN/OUT LV I 2S word strobe 6 5 5 13 I2S_DA_OUT OUT LV I 2S data output 7 6 4 14 I2S_DA_IN1 IN LV I 2S1 data input 8 7 3 15 ADR_DA OUT LV ADR data output -- 2 - NC LV Not connected 9 8 1 16 ADR_WS OUT LV ADR word strobe 10 9 68 17 ADR_CL OUT LV ADR clock 11 --- DVSUP OBL Digital power supply +5 V 12 --- DVSUP OBL Digital power supply +5 V 13 10 67 18 DVSUP OBL Digital power supply +5 V 14 --- DVSS OBL Digital ground 15 --- DVSS OBL Digital ground 16 11 66 19 DVSS OBL Digital ground - 12 65 20 I2S_DA_IN2/3 IN LV I 2S2/3-data input 17 --- I2S_DA_IN2 IN LV PQFP80: pin 22 separate I2S_DA_IN3 18 13 64 21 NC LV Not connected 19 14 63 22 I2S_CL3 IN LV I 2S3 clock 20 15 62 23 I2S_WS3 IN LV I 2S3 word strobe 21 16 61 24 RESETQ IN OBL Power-on-reset 22 --- I2S_DA_IN3 IN LV I 2S3-data input 23 --- NC LV Not connected 24 17 60 25 DACA_R OUT LV Aux out, right
MSP 3438G PRELIMINARY DATA SHEET
38 MICRONAS INTERMETALL
25 18 59 26 DACA_L OUT LV Aux out, left 26 19 58 27 VREF2 OBL Reference ground 2 27 20 57 28 DACM_R OUT LV Loudspeaker out, right 28 21 56 29 DACM_L OUT LV Loudspeaker out, left 29 22 55 30 NC LV Not connected 30 23 54 31 NC LV Not connected 31 24 53 32 NC LV Not connected 32 - 52 - NC LV Not connected 33 25 51 33 SC2_OUT_R OUT LV SCART output 2, right 34 26 50 34 SC2_OUT_L OUT LV SCART output 2, left 35 27 49 35 VREF1 OBL Reference ground 1 36 28 48 36 SC1_OUT_R OUT LV SCART output 1, right 37 29 47 37 SC1_OUT_L OUT LV SCART output 1, left 38 30 46 38 CAPL_A OBL Volume capacitor AUX 39 31 45 39 AHVSUP OBL Analog power supply 8.0 V 40 32 44 40 CAPL_M OBL Volume capacitor MAIN 41 --- NC LV Not connected 42 --- NC LV Not connected 43 --- AHVSS OBL Analog ground 44 33 43 41 AHVSS OBL Analog ground 45 34 42 42 AGNDC OBL Analog reference voltage 46 - 41 - NC LV Not connected 47 35 40 43 SC4_IN_L IN LV SCART 4 input, left 48 36 39 44 SC4_IN_R IN LV SCART 4 input, right 49 37 38 45 ASG AHVSS Analog Shield Ground 50 38 37 46 SC3_IN_L IN LV SCART 3 input, left 51 39 36 47 SC3_IN_R IN LV SCART 3 input, right 52 40 35 48 ASG AHVSS Analog Shield Ground 53 41 34 49 SC2_IN_L IN LV SCART 2 input, left 54 42 33 50 SC2_IN_R IN LV SCART 2 input, right 55 43 32 51 ASG AHVSS Analog Shield Ground Pin No. Pin Name Type Connection (if not used) Short Description PQFP 80-pin PLQFP 64-pin PLCC 68-pin PSDIP 64-pin
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 39 56 44 31 52 SC1_IN_L IN LV SCART 1 input, left 57 45 30 53 SC1_IN_R IN LV SCART 1 input, right 58 46 29 54 VREFTOP OBL Reference voltage IF A/D converter 59 --- NC LV Not connected 60 47 28 55 MONO_IN IN LV Mono input 61 --- AVSS OBL Analog ground 62 48 27 56 AVSS OBL Analog ground 63 --- NC LV Not connected 64 --- NC LV Not connected 65 --- AVSUP OBL Analog power supply +5V 66 49 26 57 AVSUP OBL Analog power supply +5V 67 50 25 58 ANA_IN1 + IN LV IF input 1 68 51 24 59 ANA_IN - IN AVSS via 56 pF / LV IF common (Can be left vacant, only if IF input 1 is also not in use) 69 52 23 60 ANA_IN2 + IN AVSS via 56 pF / LV IF input 2 (Can be left vacant, only if IF input 1 is also not in use) 70 53 22 61 TESTEN IN AVSS Test pin 71 54 21 62 XTAL_IN IN OBL Crystal oscillator 72 55 20 63 XTAL_OUT OUT OBL / LV Crystal oscillator (See also 4.3. Pin descriptions) 73 56 19 64 TP LV Test pin 74 57 18 1 AUD_CL_OUT OUT LV Audio clock output (18.432 MHz) -- 17 - NC LV Not connected 75 58 16 2 NC LV Not connected 76 59 15 3 NC LV Not connected 77 60 14 4 D_CTR_I/O_1 IN/OUT LV D_CTR_I/O_1 78 61 13 5 D_CTR_I/O_0 IN/OUT LV D_CTR_I/O_0 79 62 12 6 ADR_SEL IN OBL I 2C Bus address select 80 63 11 7 STANDBYQ IN OBL Stand-by (low-active) Pin No. Pin Name Type Connection (if not used) Short Description PQFP 80-pin PLQFP 64-pin PLCC 68-pin PSDIP 64-pin
MSP 3438G PRELIMINARY DATA SHEET
40 MICRONAS INTERMETALL
4.3. Pin Descriptions Pin numbers refer to the 80-pin PQFP package. Pin 1, NC – Pin not connected. Pin 2, I2C_CL – I2C Clock Input/Output (Fig. 4–10) Via this pin, the I2C-bus clock signal has to be sup- plied. The signal can be pulled down by the MSP in case of wait conditions. Pin 3, I2C_DA – I2C Data Input/Output (Fig. 4–10) Via this pin, the I2C-bus data is written to or read from the MSP. Pin 4, I2S_CL – I2S Clock Input/Output (Fig. 4–13) Clock line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I2S clock has to be supplied. Pin 5, I2S_WS – I2S Word Strobe Input/Output (Fig. 4–13) Word strobe line for the I2S bus. In master mode, this line is driven by the MSP; in slave mode, an external I 2S word strobe has to be supplied. Pin 6, I2S_DA_OUT1 – I2S Data Output (Fig. 4–9) Output of digital serial sound data of the MSP on the I2S bus. Pin 7, I2S_DA_IN1 – I2S Data Input 1 (Fig. 4–11) First input of digital serial sound data to the MSP via the I 2S bus. Pin 8, ADR_DA – ADR Bus Data Output (Fig. 4–9) Output of digital serial data to the DRP 3510A via the ADR bus. Pin 9, ADR_WS – ADR Bus Word Strobe Output (Fig. 4–9) Word strobe output for the ADR bus. Pin 10, ADR_CL – ADR Bus Clock Output (Fig. 4–9) Clock line for the ADR bus. Pins 11, 12, 13, DVSUP* – Digital Supply Voltage Power supply for the digital circuitry of the MSP. Must be connected to a +5 V power supply. Pins 14, 15, 16, DVSS* – Digital Ground Ground connection for the digital circuitry of the MSP. Pin 17, I2S_DA_IN2 – I 2S Data Input 2 (Fig. 4–11) Second input of digital serial sound data to the MSP via the I 2S bus. In all packages except PQFP-80-pin this pin is also connected to the asynchronous I2S interface 3. Pins 18, NC – Pin not connected. Pins 19, I2S_CL3 – I2S Clock Input (Fig. 4–11) Clock line for the I2S bus. Since only a slave mode is available an external I2S clock has to be supplied. Pins 20, I2S_WS3 – I2S Word Strobe Input (Fig. 4–11) Word strobe line for the I2S bus. Since only a slave mode is available an external I2S word strobe has to be supplied. Pin 21, RESETQ – Reset Input (Fig. 4–11) In the steady state, high level is required. A low level resets the MSP 34x8G. Pin 22, I2S_DA_IN3 – I 2S Data Input 3 (Fig. 4–11) Asynchronous input of digital serial sound data to the MSP via the I 2S bus. Pins 23, NC – Pin not connected. Pins 24, 25, DACA_R/L – Aux Outputs (Fig. 4–19) Output of the aux signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC offset on these pins depends on the selected aux volume. Pin 26, VREF2 – Reference Ground 2 Reference analog ground. This pin must be connected separately to the ground (AHVSS). VREF2 serves as a clean ground and should be used as the reference for analog connections to the loudspeaker and head- phone outputs. Pins 27, 28, DACM_R/L – Loudspeaker Outputs (Fig. 4–19) Output of the loudspeaker signal. A 1 nF capacitor to AHVSS must be connected to these pins. The DC off- set on these pins depends on the selected loud- speaker volume. Pin 29, 30, 31, 32 NC – Pin not connected. Pins 33, 34, SC2_OUT_R/L – SCART2 Outputs (Fig. 4–21) Output of the SCART2 signal. Connections to these pins must use a 100-W series resistor and are intended to be AC-coupled. Pin 35, VREF1 – Reference Ground 1 Reference analog ground. This pin must be connected separately to the ground (AHVSS). VREF1 serves as a clean ground and should be used as the reference for analog connections to the SCART outputs. Pins 36, 37, SC1_OUT_R/L – SCART1 Outputs (Fig. 4–21) Output of the SCART1 signal. Connections to these pins must use a 100-W series resistor and are intended to be AC-coupled.
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 41 Pin 38, CAPLA – Volume Capacitor Aux (Fig. 4–16) A 10-mF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for aux volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1-mF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induction. Pin 39, AHVSUP* – Analog Power Supply High Volt- age Power is supplied via this pin for the analog circuitry of the MSP (except IF input). This pin must be connected to the +8 V supply. (+5 V-operation is possible with restrictions in performance) Pin 40, CAPLM – Volume Capacitor Loudspeakers (Fig. 4–16) A 10-mF capacitor to AHVSUP must be connected to this pin. It serves as a smoothing filter for loudspeaker volume changes in order to suppress audible plops. The value of the capacitor can be lowered to 1mF if faster response is required. The area encircled by the trace lines should be minimized; keep traces as short as possible. This input is sensitive for magnetic induc- tion. Pins 41, 42, NC – Pins not connected. Pins 43, 44, AHVSS* – Analog Power Supply High Voltage Ground connection for the analog circuitry of the MSP (except IF input). Pin 45, AGNDC – Internal Analog Reference Voltage This pin serves as the internal ground connection for the analog circuitry (except IF input). It must be con- nected to the VREF pins with a 3.3-mF and a 100-nF capacitor in parallel. This pins shows a DC level of typ- ically 3.73 V. Pin 46, NC – Pin not connected. Pins 47, 48, SC4_IN_L/R – SCART4 Inputs (Fig. 4–18) The analog input signal for SCART4 is fed to this pin. Analog input connection must be AC-coupled. Pin 49, ASG* – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 50, 51, SC3_IN_L/R – SCART3 Inputs (Fig. 4–18) The analog input signal for SCART3 is fed to this pin. Analog input connection must be AC-coupled. Pin 52, ASG* – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 53, 54 SC2_IN_L/R – SCART2 Inputs (Fig. 4–18) The analog input signal for SCART2 is fed to this pin. Analog input connection must be AC-coupled. Pin 55, ASG* – Analog Shield Ground Analog ground (AHVSS) should be connected to this pin to reduce cross-coupling between SCART inputs. Pins 56, 57 SC1_IN_L/R – SCART1 Inputs (Fig. 4–18) The analog input signal for SCART1 is fed to this pin. Analog input connection must be AC-coupled. Pin 58, VREFTOP – Reference Voltage IF A/D Con- verter (Fig. 4–15) Via this pin, the reference voltage for the IF A/D con- verter is decoupled. It must be connected to AVSS pins with a 10-mF and a 100-nF capacitor in parallel. Traces must be kept short. Pin 59, NC – Pin not connected. Pin 60 MONO_IN – Mono Input (Fig. 4–18) The analog mono input signal is fed to this pin. Analog input connection must be AC-coupled. Pins 61, 62, AVSS* – Analog Power Supply Voltage Ground connection for the analog IF input circuitry of the MSP. Pins 63, 64, NC – Pins not connected. Pins 65, 66, AVSUP* – Analog Power Supply Voltage Power is supplied via this pin for the analog IF input circuitry of the MSP . This pin must be connected to the +5 V supply. Pin 67, ANA_IN1 + – IF Input 1 (Fig. 4–15) The analog sound IF signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN1+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 68, ANA_IN - – IF Common (Fig. 4–15) This pins serves as a common reference for ANA_IN1/ 2+ inputs and must be AC-coupled. Pin 69, ANA_IN2 + – IF Input 2 (Fig. 4–15) The analog sound if signal is supplied to this pin. Inputs must be AC-coupled. This pin is designed as symmetrical input: ANA_IN2+ is internally connected to one input of a symmetrical op amp, ANA_IN- to the other. Pin 70, TESTEN – Test Enable Pin (Fig. 4–11) This pin enables factory test modes. For normal opera- tion, it must be connected to ground.
MSP 3438G PRELIMINARY DATA SHEET
42 MICRONAS INTERMETALL
Pins 71, 72 XTAL_IN, XTAL_OUT – Crystal Input and Output Pins (Fig. 4–14) These pins are connected to an 18.432 MHz crystal oscillator which is digitally tuned by integrated capaci- tances. An external clock can be fed into XTAL_IN (leave XTAL_OUT vacant in this case). The audio clock output signal AUD_CL_OUT is derived from the oscillator. External capacitors at each crystal pin to ground (AVSS) are required. It should be verified by layout, that no supply current for the digital circuitry is flowing through the ground connection point. Pin 73, TP – This pin enables factory test modes. For normal operation, it must be left vacant. Pin 74, AUD_CL_OUT – Audio Clock Output (Fig. 4–14) This is the 18.432 MHz main clock output. Pins 75, 76, NC – Pins not connected. Pins 77, 78, D_CTR_I/O_1/0 – Digital Control Input/ Output Pins (Fig. 4–13) These pins serve as general purpose input/output pins. Pin D_CTR_I/O_1 can be used as an interrupt request pin to the controller. Pin 79, ADR_SEL – I 2C Bus Address Select (Fig. 4–12) By means of this pin, one of three device addresses for the MSP can be selected. The pin can be con- nected to ground (I 2C device addresses 80/81hex), to +5 V supply (84/85hex), or left open (88/89hex). Pin 80, STANDBYQ – Stand-by In normal operation, this pin must be High. If the MSP is switched off by first pulling STANDBYQ low and then (after >1ms delay) switching off the 5 V, but keeping the 8-V power supply (‘Stand-by’-mode), the SCART switches maintain their position and function. * Application Note: All ground pins should be connected to one low-resis- tive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as closely as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be extended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10mF. The capacitor with the low- est value should be placed nearest to the pins. The ASG pins should be connected as closely as pos- sible to the MSP ground. They are intended for leading with the SCART signals as shield lines and should not be connected to ground at the SCART-connector.
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 43 4.4. Pin Configurations Fig. 4–5:80-pin PQFP package 1 2 3 4 5 6 7 8 9 1 01 11 21 31 41 51 61 71 81 92 02 12 22 32 4 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AVSUP AVSUP ANA_IN1+ ANA_IN - ANA_IN2+ TESTEN XTAL_IN XTAL_OUT TP AUD_CL_OUT NC NC D_CTR_I/O_1 D_CTR_I/O_0 ADR_SEL STANDBYQ CAPL_M AHVSUP CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R NC NC NC NC DACM_L DACM_R VREF2 DACA_L NC AVSS AVSS MONO_IN NC VREFTOP SC1_IN_R SC1_IN_L ASG NC SC2_IN_R SC2_IN_L ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS AHVSS NC NC I2C_CL I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS ADR_CL NC DVSUP DVSUP DVSUP DVSS DVSS DVSS I2S_DA_IN2 NC I2S_CL3 I2S_WS3 RESETQ I2S_DA_IN3 NC DACA_R MSP 34x8G
MSP 3438G PRELIMINARY DATA SHEET
44 MICRONAS INTERMETALL
Fig. 4–6:64-pin PLQFP package 49AVSUP 50ANA_IN1+ 51ANA_IN - 52ANA_IN2+ 53TESTEN 54XTAL_IN 55XTAL_OUT 56TP 57AUD_CL_OUT 58NC 59NC 60D_CTR_I/O_1 61C_CTR_I/O_0 62ADR_SEL 63STANDBYQ 64NC CAPL_M32 AHVSUP31 CAPL_A30 SC1_OUT_L29 SC1_OUT_R28 VREF127 SC2_OUT_L26 SC2_OUT_R25 NC24 NC23 NC22 DACM_L21 DACM_R20 VREF219 DACA_L18 DACA_R17 MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L AVSS ASG SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L AGNDC AHVSS I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA ADR_WS I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2/3 NC I2S_CL3 I2S_WS3 RESETQ 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MSP 34x8G
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 45 Fig. 4–7:68-pin PLCC package 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 987654321 6 8 6 7 6 6 6 5 6 4 6 3 6 2 6 1 26 44 MSP 34x8G NC STANDBYQ ADR_SEL D_CTR_I/O_0 D_CTR_I/O_1 NC NC NC AUD_CL_OUT TP XTAL_OUT XTAL_IN TESTEN ANA_IN2+ ANA_IN - ANA_IN1+ DACA_R DACA_L VREF2 DACM_R DACM_L NC NC NC NC SC2_OUT_R SC2_OUT_L VREF1 SC1_OUT_R SC1_OUT_L CAPL_A AHVSUP I2C_DA I2S_CL I2S_WS I2S_DA_OUT I2S_DA_IN1 ADR_DA NC ADR_WS I2C_CL ADR_CL DVSUP DVSS I2S_DA_IN2/3 NC I2S_CL3 I2S_WS3 RESETQ MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG SC2_IN_R SC2_IN_L AVSS SC3_IN_R SC3_IN_L ASG SC4_IN_R SC4_IN_L NC AGNDC AHVSS ASG AVSUP CAPL_M
MSP 3438G PRELIMINARY DATA SHEET
46 MICRONAS INTERMETALL
Fig. 4–8:64-pin PSDIP package 1AUD_CL_OUT 2NC 3NC 4D_CTR_I/O_1 5D_CTR_I/O_0 6ADR_SEL 7STANDBYQ 8NC 9I2C_CL 10I2C_DA 11I2S_CL 12I2S_WS 13I2S_DA_OUT 14I2S_DA_IN1 15ADR_DA 16ADR_WS TP64 XTAL_OUT63 XTAL_IN62 TESTEN61 ANA_IN2+60 ANA_IN -59 ANA_IN+58 AVSUP57 AVSS56 MONO_IN55 VREFTOP54 SC1_IN_R53 SC1_IN_L52 ASG51 SC2_IN_R50 SC2_IN_L49 17ADR_CL 18DVSUP 19DVSS 20I2S_DA_IN2/3 21NC 22I2S_CL3 23I2S_WS3 24RESETQ 25DACA_R 26DACA_L ASG48 SC3_IN_R47 SC3_IN_L46 ASG45 SC4_IN_R44 SC4_IN_L43 AGNDC42 AHVSS41 CAPL_M40 AHVSUP39 MSP 34x8G VREF2 DACM_R DACM_L NC NC NC CAPL_A SC1_OUT_L SC1_OUT_R VREF1 SC2_OUT_L SC2_OUT_R
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 47 4.5. Pin Circuits Pin numbers refer to the PQFP80 package. Fig. 4–9:Output Pins 6, 8, 9, and 10 (I2S_DA_OUT, ADR_DA, ADR_WS, ADR_CL) Fig. 4–10:Input/Output Pins 2 and 3 (I2C_CL, I2C_DA) Fig. 4–11:Input Pins 7, 17, 22, 19, 20, 21, 70, and 80 (I2S_DA_IN1..3, I2S_CL3, I2S_WS3, RESETQ, TESTEN, STANDBYQ ) Fig. 4–12:Input Pin 79 (ADR_SEL) Fig. 4–13:Input/Output Pins 4, 5, 77, and 78 (I2S_CL, I2S_WS, D_CTR_I/O_1, D_CTR_I/O_0) Fig. 4–14:Output/Input Pins 71, 72, and 74 (XTAL_IN, XTAL_OUT, AUD_CL_OUT) Fig. 4–15:Input Pins 58, 67, 68, and 69 (VREFTOP, ANA_IN1 +, ANA_IN-, ANA_IN2+) DVSUP P N GND N GND ADR_SEL GND DVSUP 23 kW 23 kW DVSUP P N GND 3-30 pF 2.5 V 500 kW 3-30 pF P N Gain=0.5 D A ANA_IN1+ VREFTOP ANA_IN - ANA_IN2+
MSP 3438G PRELIMINARY DATA SHEET
48 MICRONAS INTERMETALL
Fig. 4–16:Capacitor Pins 38 and 40 (CAPL_A, CAPL_M) Fig. 4–17:Input Pin 60 (MONO_IN ) Fig. 4–18:Input Pins 47, 48, 50, 51, 53, 54, 56, and 57 (SC4-1_IN_L/R) Fig. 4–19:Output Pins 24, 25, 27, and 28 (DACA_R/L, DACM_R/L) Fig. 4–20:Pin 45 (AGNDC) Fig. 4–21:Output Pins 33, 34, 36, and 37 0...2 V » 3.75 V 24 kW » 3.75 V 40 kW AHVSUP 0...1.2 mA 3.3 kW » 3.75 V 125 kW 26 pF 120 kW 300 W » 3.75 V
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 49 4.6. Electrical Characteristics 4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. Symbol Parameter Pin Name Min. Max. Unit TA Ambient Operating Temperature - 07 0 °C TS Storage Temperature -- 40 125 °C VSUP1 First Supply Voltage AHVSUP -0.3 9.0 V VSUP2 Second Supply Voltage DVSUP -0.3 6.0 V VSUP3 Third Supply Voltage AVSUP -0.3 6.0 V dVSUP23 Voltage between AVSUP and DVSUP AVSUP, DVSUP -0.5 0.5 V PLCC68 PSDIP64 PLQFP64 PQFP80 AHVSUP , DVSUP , AVSUP 1200 1300 960 1000 mW mW mW mW V Idig Input Voltage, all Digital Inputs -0.3 V SUP2 +0.3 V IIdig Input Current, all Digital Pins -20 +20 mA 1) VIana Input Voltage, all Analog Inputs SCn_IN_s,2) MONO_IN -0.3 V SUP1 +0.3 V IIana Input Current, all Analog Inputs SCn_IN_s,2) MONO_IN -5 +5m A 1) IOana Output Current, all SCART Outputs SCn_OUT_s2) 3) , 4) 3) , 4) IOana Output Current, all Analog Outputs except SCART Outputs DACp_s 2) 3) 3) ICana Output Current, other pins connected to capacitors CAPL_p,2) AGNDC 3) 3) 1) positive value means current flowing into the circuit 3) The Analog Outputs are short-circuit proof with respect to First Supply Voltage and Ground. 4) Total chip power dissipation must not exceed absolute maximum rating.
MSP 3438G PRELIMINARY DATA SHEET
50 MICRONAS INTERMETALL
4.6.2. Recommended Operating Conditions (TA = 0 to 70 °C) 4.6.2.1. General Recommended Operating Conditions 4.6.2.2. Analog Input and Output Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit VSUP1 First Supply Voltage (8-V Operation) AHVSUP 7.6 8.0 8.7 V First Supply Voltage (5-V Operation) 4.75 5.0 5.25 V VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V tSTBYQ1 STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, DVSUP 1 ms Symbol Parameter Pin Name Min. Typ. Max. Unit C AGNDC AGNDC-Filter-Capacitor AGNDC -20% 3.3 mF Ceramic Capacitor in Parallel -20% 100 nF C inSC DC-Decoupling Capacitor in front of SCART Inputs SCn_IN_s1) -20% 330 nF VinSC SCART Input Level 2.0 V RMS VinMONO Input Level, Mono Input MONO_IN 2.0 V RMS R LSC SCART Load Resistance SCn_OUT_s 1) 10 k W C LSC SCART Load Capacitance 6.0 nF C VMA Main/AUX Volume Capacitor CAPL_M, CAPL_A 10 mF C FMA Main/AUX Filter Capacitor DACM_s, DACA_s 1) -10% 1 +10% nF
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 51 4.6.2.3. Recommendations for Analog Sound IF Input Signal Symbol Parameter Pin Name Min. Typ. Max. Unit C VREFTOP VREFTOP-Filter-Capacitor VREFTOP -20 % 10 mF Ceramic Capacitor in Parallel -20 % 100 nF FIF_FMTV Analog Input Frequency Range for TV Applications ANA_IN1 +, ANA_IN2 +, ANA_IN -
09 M H z
FIF_FMRADIO Analog Input Frequency for FM-Radio Applications
10.7 MHz
VIF_FM Analog Input Range FM/NICAM 0.1 0.8 3 V pp VIF_AM Analog Input Range AM/NICAM 0.1 0.45 0.8 V pp R FMNI Ratio: NICAM Carrier/FM Carrier (unmodulated carriers) BG: -20 -23 -10 dB dB R AMNI Ratio: NICAM Carrier/AM Carrier (unmodulated carriers) -25 -11 0 dB R FM Ratio: FM-Main/FM-Sub Satellite 7 dB R FM1/FM2 Ratio: FM1/FM2 German FM-System 7d B R FC Ratio: Main FM Carrier/ Color Carrier 15 -- dB R FV Ratio: Main FM Carrier/ Luma Components 15 -- dB PR IF Passband Ripple --– 2d B SUP HF Suppression of Spectrum above 9.0 MHz (not for FM Radio) 15 dB FM MAX Maximum FM-Deviation (approx.) normal mode HDEV2: high deviation mode HDEV3: very high deviation mode –180 –360 –540 kHz kHz kHz
MSP 3438G PRELIMINARY DATA SHEET
52 MICRONAS INTERMETALL
4.6.2.4. Crystal Recommendations Symbol Parameter Pin Name Min. Typ. Max. Unit General Crystal Recommendations f P Crystal Parallel Resonance Fre- quency at 12 pF Load Capacitance
18.432 MHz
R R Crystal Series Resistance 8 25 W C 0 Crystal Shunt (Parallel) Capacitance 6.2 7.0 pF C L External Load Capacitance1) XTAL_IN, XTAL_OUT PSDIP approx. 1.5 PLCC approx. 3.3 P(L)QFP approx. 3.3 pF pF pF Crystal Recommendations for Master-Slave Applications (MSP-clock must perform synchronization to I2S clock) fTOL Accuracy of Adjustment -20 +20 ppm D TEM Frequency Variation versus Temperature -20 +20 ppm C 1 Motional (Dynamic) Capacitance 19 24 fF fCL Required Open Loop Clock Frequency (Tamb = 25°C) AUD_CL_OUT 18.431 18.433 MHz Crystal Recommendations for FM / NICAM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment -30 +30 ppm D TEM Frequency Variation versus Temperature -30 +30 ppm C 1 Motional (Dynamic) Capacitance 15 fF fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.4305 18.4335 MHz Crystal Recommendations for all analog FM/AM Applications (No MSP-clock synchronization to I2S clock possible) fTOL Accuracy of Adjustment -100 +100 ppm D TEM Frequency Variation versus Temperature -50 +50 ppm fCL Required Open Loop Clock Frequency (Tamb = 25 °C) AUD_CL_OUT 18.429 18.435 MHz Amplitude Recommendation for Operation with External Clock Input (Cload after reset typ. 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 V pp 1)External capacitors at each crystal pin to ground are required. They are necessary to tune the open-loop fre- quency of the internal PLL and to stabilize the frequency in closed-loop operation. Due to different layouts, the accurate capacitor size should be determined with the customer PCB . The sug- To define the capacitor size, reset the MSP without transmitting any further I2C telegrams. Measure the fre- quency at AUD_CL_OUT-pin. Change the capacitor size until the free running frequency matches 18.432 MHz as closely as possible. The higher the capacity, the lower the resulting clock frequency.
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 53 4.6.3. Characteristics at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel 4.6.3.1. General Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Supply ISUP1A First Supply Current (active) (8-V Operation) Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB AHVSUP 9.6 6.3 17.1 11.2 24.6 16.1 mA mA First Supply Current (active) (5-V Operation) Analog Volume for Main and Aux at 0 dB Analog Volume for Main and Aux at -30 dB 6.4 4.2 11.4 7.5 16.4 10.7 mA mA ISUP2A Second Supply Current (active) DVSUP 50 70 85 mA ISUP3A Third Supply Current (active) AVSUP 20 35 45 mA ISUP1S First Supply Current (8-V Operation) (standby mode) at T j = 27 °C AHVSUP 3.5 5.6 7.7 mA STANDBYQ = low First Supply Current (5-V Operation) (standby mode) at T j = 27 °C 2.3 3.7 5.1 mA STANDBYQ = low Clock fCLOCK Clock Input Frequency XTAL_IN 18.432 MHz D CLOCK Clock High to Low Ratio 45 55 % tJITTER Clock Jitter (Verification not provided in Production Test) 50 ps VxtalDC DC-Voltage Oscillator 2.5 V tStartup Oscillator Startup Time at VDD Slew-rate of 1 V/ms XTAL_IN, XTAL_OUT 0.4 2 ms VACLKAC Audio Clock Output AC Voltage AUD_CL_OUT 1.2 1.8 V pp load = 40 pF VACLKDC Audio Clock Output DC Voltage 0.4 0.6 V SUP3 Imax = 0.2 mA routHF_ACL HF Output Resistance 140 W
MSP 3438G PRELIMINARY DATA SHEET
54 MICRONAS INTERMETALL
4.6.3.2. Digital Inputs, Digital Outputs Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Digital Inputs Levels VDIGIL Digital Input Low Voltage STANDBYQ D_CTR_I/O_0/1
0.2 V SUP2
VDIGIH Digital Input High Voltage 0.5 V SUP2 ZDIGI Input Impedance 5 pF IDLEAK Digital Input Leakage Current -11 mA0 V < U INPUT < DVSUP D_CTR_I/O_0/1: tri-state VDIGIL ADR_SEL Input Low Voltage ADR_SEL 0.2 V SUP2 VDIGIH ADR_SEL Input High Voltage 0.8 V SUP2 IADRSEL Input Current -500 -220 mAU ADR_SEL = DVSS 220 500 mAU ADR_SEL = DVSUP Digital Output Levels VDCTROL Digital Output Low Voltage D_CTR_I/O_0 D_CTR_I/O_1
0.4 V IDDCTR = 1 mA
VDCTROH Digital Output High Voltage 4.0 V IDDCTR = -1 mA
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 55 4.6.3.3. Reset Input and Power-Up Fig. 4–22:Power-up sequence Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions RESETQ Input Levels VRHL Reset High-Low Transition Voltage RESETQ 0.45 0.55 V SUP2 VRLH Reset Low-High Transition Voltage 0.7 0.8 V SUP2 ZRES Input Impedance 5 pF IRES Input Pin Leakage Current -1 1 mA0 V < U INPUT < DVSUP 4.5V Internal Reset t/ms RESETQ AVSUP DVSUP High Low t/ms t/ms 0.7· DVSUP Low-to-High Threshold High-to-Low Threshold Reset Delay >2 ms Note: The reset should not reach high level before the oscillator has started. This requires a reset delay of >2 ms 0.7 x DVSUP means
3.5 Volt with
DVSUP = 5.0 V
MSP 3438G PRELIMINARY DATA SHEET
56 MICRONAS INTERMETALL
4.6.3.4. I2C-Bus Characteristics Fig. 4–23:I2C bus timing diagram Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VI2CIL I2C-BUS Input Low Voltage I2C_CL, I2C_DA
0.3 V SUP2
VI2CIH I2C-BUS Input High Voltage 0.6 V SUP2 tI2C1 I2C START Condition Setup Time 120 ns tI2C2 I2C STOP Condition Setup Time 120 ns tI2C5 I2C-Data Setup Time before Rising Edge of Clock 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns tI2C3 I2C-Clock Low Pulse Time I2C_CL 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns fI2C I2C-BUS Frequency 1.0 MHz VI2COL I2C-Data Output Low Voltage I2C_CL, I2C_DA
0.4 V I I2COL = 3 mA
1.0 mAV I2COH = 5 V tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns f I2C = 1 MHz I2C_CL I2C_DA as input I2C_DA as output TI2C1 TI2C5 TI2C6 TI2C2 TI2C4 TI2C3 1/FI2C TI2COL2 TI2COL1
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 57 4.6.3.5. I2S-Bus Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions VI2SIL Input Low Voltage I2S_DA_IN1..3 I2S_CL I2S_WS I2S_CL3 I2S_WS3 0.2 V SUP2 VI2SIH Input High Voltage 0.5 V SUP2 ZI2SI Input Impedance 5 pF ILEAKI2S Input Leakage Current -11 mA0 V < U INPUT < DVSUP tI2S1 I2S-Data Input Setup Time before Rising Edge of Clock I2S_DA_IN1/2 I2S_CL 20 ns for details see Fig. 4–24 (synchronous I2S inter- face) tI2S2 I2S-Data Input Hold Time after Falling Edge of Clock 0n s fI2SWS I2S-Word Strobe Input Frequency I2S_WS 48.0 kHz fI2SCL I2S-Clock Input Frequency I2S_CL 1.536 MHz R I2SCL I2S-Clock Input Ratio 0.9 1.1 tI2SWS1 I2S-Word Strobe Input Setup Time before Rising Edge of Clock I2S_WS I2S_CL 60 ns tI2SWS2 I2S-Word Strobe Input Hold Time after Falling Edge of Clock 0n s tI2S31 I2S3-Data Input Setup Time before Rising Edge of Clock I2S_DA_IN3 I2S_CL 8 ns for details see Fig. 4–25 (asynchronous I2S inter- face) tI2S32 I2S3-Data Input Hold Time after Falling Edge of Clock 0n s fI2S3WS I2S3-Word Strobe Input Frequency I2S_WS3 5 50 kHz fI2S3CL I2S3-Clock Input Frequency I2S_CL3 12.288 MHz R I2S3CL I2S3-Clock Input Ratio 0.9 1.1 tI2S3WS1 I2S3-Word Strobe Input Setup Time before Rising Edge of Clock I2S_WS3 I2S_CL3 8n s t I2S3WS2 I2S3-Word Strobe Input Hold Time after Falling Edge of Clock 0n s VI2SOL I2S Output Low Voltage I2S_WS I2S_CL I2S_DA_OUT
0.4 V I
I2SOL = 1 mA VI2SOH I2S Output High Voltage 4.0 V I I2SOH = -1 mA fI2SWS I2S-Word Strobe Output Frequency I2S_WS 48.0 kHz fI2SCL I2S-Clock Output Frequency I2S_CL 1.536 MHz tI2S1/I2S2 I2S-Clock High/Low-Ratio 0.9 1.0 1.1 tI2S3 I2S-Data Setup Time before Rising Edge of Clock I2S_CL I2S_DA_OUT 200 ns C L = 30 pF tI2S4 I2S-Data Hold Time after Falling Edge of Clock 180 ns tI2S5 I2S-Word Strobe Setup Time before Rising Edge of Clock I2S_CL I2S_WS 200 ns tI2S6 I2S-Word Strobe Hold Time after Falling Edge of Clock 180 ns
MSP 3438G PRELIMINARY DATA SHEET
58 MICRONAS INTERMETALL
Fig. 4–24:I2S timing diagram (synchronous interface) Fig. 4–25:I2S timing diagram (asynchronous interface) Data: MSB first R LSB L LSB R LSB L LSB 16 bit right channel L LSB L LSB R MSB R MSB Detail C PHILIPS format SONY format I2S_WS I2S_CL I2S_DA_IN Detail A PHILIPS format (MODUS[6]=1) SONY format (MODUS[6]=0) Detail B R LSB R LSB L MSB L MSBI2S_DA_OUT 16 bit right channel16 bit left channel 16 bit left channel 1/FI2SWS I2S_CL Detail C I2S_WS as INPUT I2S_WS as OUTPUT 1/FI2SCL TI2SWS1 TI2SWS2 TI2S5 TI2S6 Detail A,B I2S_CL I2S_DA_IN I2S_DA_OUT TI2S1 TI2S2 TI2S3 TI2S4 I2S_WS3 I2S_CL3 I2S_DA_IN3 MSB 1/FI2S3WS 1/FI2S3CL I2S_CL3 I2S_DA_IN3 I2S_WS3 TI2S31 TI2S3_WS1 Right sample (MODUS[10]=0) Right sample (MODUS[10]=1) Left sample (MODUS[10]=0) Left sample (MODUS[10]=1) MSB LSB MSB MSB LSB I2S_DA_IN3 I2S_DA_IN3 Left aligned, Sony format (MODUS[9]=0) Left aligned, Philips format (MODUS[9]=1) Right aligned (MODUS[11]=1) 16,18...32 Bit data & clocks allowed 16,18...32 Bit data & clocks allowed 16 Bit data & 16...32 clocks allowed
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 59 4.6.3.6. Analog Baseband Inputs and Outputs, AGNDC Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Analog Ground VAGNDC0 AGNDC Open Circuit Voltage 8-V Operation: 5-V Operation: AGNDC 3.77 2.49 V V R load ‡ 10 MW R outAGN AGNDC Output Resistance 8-V Operation: 5-V Operation: 125 180 120 kW kW
3 V £ VAGNDC £ 4 V
R inSC SCART Input Resistance from TA = 0 to 70 °C SCn_IN_s 1) 25 40 58 k W fsignal = 1 kHz, I = 0.05 mA R inMONO MONO Input Resistance from TA = 0 to 70 °C MONO_IN 15 24 35 k W fsignal = 1 kHz, I = 0.1 mA
MSP 3438G PRELIMINARY DATA SHEET
60 MICRONAS INTERMETALL
Audio Analog-to-Digital-Converter VAICL Analog Input Clipping Level for A-D Conversion 8-V Operation: 5-V Operation: SCn_IN_s,1) MONO_IN 2.00 1.13 2.25 1.51 VRM VRMS fsignal = 1 kHz SCART Outputs R outSC SCART Output Resistance at Tj = 27 °C from TA = 0 to 70 °C SCn_OUT_s 1) 200 200 330 460 500 W W fsignal = 1 kHz, I = 0.1 mA dVOUTSC Deviation of DC-Level at SCART Output from AGNDC Voltage -70 +70 mV ASCtoSC Gain from Analog Input to SCART Output SCn_IN_s,1) MONO_IN fi SCn_OUT_s 1) -1.0 +0.5 dB f signal = 1 kHz frSCtoSC Frequency Response from Analog Input to SCART Output (0 to 20000 Hz) -0.5 +0.5 dB with resp. to 1 kHz VoutSC Signal Level at SCART-Output 8-V Operation: 5-V Operation: SCn_OUT_s 1.8 1.17 1.9 1.27 2.0 1.37 VRMS VRMS Full-scale Digital Input Signal from DSP f signal = 1 kHz Main and AUX Outputs R outMA Main/AUX Output Resistance at Tj = 27 °C from TA = 0 to 70 °C DACp_s 1) 2.1 2.1 3.3 4.6 5.0 kW kW fsignal = 1 kHz, I = 0.1 mA VoutDCMA DC-Level at Main/AUX-Output 8-V Operation: 5-V Operation: 1.80 1.12 2.04 1.36 2.28 1.60 V mV V mV Analog Volume at 0 dB Analog Volume at -30 dB Analog Volume at 0 dB Analog Volume at -30 dB VoutMA Signal Level at Main/AUX-Output 8-V Operation: 5-V Operation: 1.23 0.76 1.37 0.90 1.51 1.04 V RMS VRMS Full-scale Digital Input Signal from DSP. Analog Volume at 0 dB f signal = 1 kHz Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 61 4.6.3.7. Sound IF Inputs 4.6.3.8. Power Supply Rejection Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions R IFIN Input Impedance ANA_IN1 + ANA_IN2 + ANA_IN - 1.5 6.8 9.1 2.5 11.4 kW kW Gain AGC = 20 dB Gain AGC = 3 dB DC ANA_IN DC Voltage on IF Inputs 1.3 1.5 1.7 V XTALK IF Crosstalk Attenuation 40 dB f signal = 1 MHz Input Level = -2 dBr BW IF 3 dB Bandwidth 10 MHz AGC AGC Step Width 0.85 dB DC VREFTOP DC Voltage at VREFTOP VREFTOP 2.4 2.6 2.7 V Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions PSRR: Rejection of Noise on AHVSUP at 1 kHz PSRR AGNDC AGNDC 80 dB From Analog Input to I 2S Output MONO_IN, SCn_IN_s 1) 70 dB From Analog Input to SCART Output MONO_IN, SCn_IN_s 1) SCn_OUT_s 1) 70 dB From I2S Input to SCART Output SCn_OUT_s 1) 60 dB From I2S Input to MAIN/AUX Out- put DACp_s 1) 80 dB
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4.6.3.9. Analog Performance Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions Specifications for 8-V Operation SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 85 88 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s fi SCn_OUT_s 1) 93 96 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 85 88 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz from I 2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB DACp_s dB dB THD Total Harmonic Distortion from Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 0.01 0.03 % Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s fi SCn_OUT_s 0.01 0.03 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 0.01 0.03 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from I 2S Input to Main or AUX Out- put DACA_s, DACM_s 1) 0.01 0.03 %
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 63 Specifications for 5-V Operation SNR Signal-to-Noise Ratio from Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 82 85 dB Input Level = -20 dB with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s fi SCn_OUT_s 1) 90 93 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 82 85 dB Input Level = -20 dB, fsig = 1 kHz, equally weighted 20 Hz...15 kHz from I 2S Input to Main/AUX-Output for Analog Volume at 0 dB for Analog Volume at -30 dB DACp_s dB dB THD Total Harmonic Distortion from Analog Input to I2S Output MONO_IN, SCn_IN_s 1) 0.03 0.1 % Input Level = -3 dBr with resp. to VAICL, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from Analog Input to SCART Output MONO_IN, SCn_IN_s fi SCn_OUT_s 0.1 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz from I 2S Input to SCART Output SCn_OUT_s 1) 0.1 % Input Level = -3 dBr, fsig = 1 kHz, equally weighted 20 Hz...16 kHz from I 2S Input to Main or AUX Out- put DACA_s, DACM_s 1) 0.1 % Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
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XTALK Specifications for 8-V and 5-V Operation XTALK Crosstalk Attenuation - PLCC68 - PSDIP64 Input Level = -3 dB, fsig = 1 kHz, unused ana- log inputs connected to ground by Z < 1 kW between left and right channel within SCART Input/Output pair (Lfi R, Rfi L) SCn_IN fi SCn_OUT 1) PLCC68 PSDIP64 SC1_IN or SC2_IN fi I2S Output PLCC68 PSDIP64 SC3_IN fi I2S Output PLCC68 PSDIP64 I2S Input fi SCn_OUT 1) PLCC68 PSDIP64 dB dB dB dB dB dB dB dB equally weighted 20 Hz...20 kHz between left and right channel within Main or AUX Output pair I2S Input fi DACp 1) PLCC68 PSDIP64 dB dB equally weighted 20 Hz...16 kHz between SCART Input/Output pairs1) D = disturbing program O = observed program D: MONO/SCn_IN fi SCn_OUT PLCC68 O: MONO/SCn_IN fi SCn_OUT 1) PSDIP64 D: MONO/SCn_IN fi SCn_OUT or unsel. PLCC68 O: MONO/SCn_IN fi I2S Output PSDIP64 D: MONO/SCn_IN fi SCn_OUT PLCC68 O: I2S Input fi SCn_OUT 1) PSDIP64 D: MONO/SCn_IN fi unselected PLCC68 O: I2S Input fi SC1_OUT 1) PSDIP64 100 100 100 100 100 100 100 dB dB dB dB dB dB dB dB (equally weighted 20 Hz...20 kHz same signal source on left and right disturbing chan- nel, effect on each observed output channel Crosstalk between Main and AUX Output pairs I 2S Input DSP fi DACp 1) PLCC68 PSDIP64 dB dB (equally weighted 20 Hz...16 kHz) same signal source on left and right disturbing chan- nel, effect on each observed output channel XTALK Crosstalk from Main or AUX Output to SCART Output and vice versa D = disturbing program O = observed program D: MONO/SCn_IN/DSP fi SCn_OUT PLCC68 O: I 2S Input fi DACp 1) PSDIP64 D: MONO/SCn_IN/DSP fi SCn_OUT PLCC68 O: I2S Input fi DACp 1) PSDIP64 D: I2S Input fi DACp PLCC68 O: MONO/SCn_IN fi SCn_OUT 1) PSDIP64 D: I2S Input fi DACM PLCC68 O: I2S Input fi SCn_OUT 1) PSDIP64 100 100 dB dB dB dB dB dB dB dB (equally weighted 20 Hz...20 kHz) same signal source on left and right disturbing chan- nel, effect on each observed output channel SCART output load resis- tance 10 kW SCART output load resis- tance 30 kW Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 65 4.6.3.10. Sound Standard Dependent Characteristics Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions NICAM Characteristics (MSP Standard Code = 8) dVNICAMOUT Tolerance of Output Voltage of NICAM Baseband Signal DACp_s SCn_OUT_s 1) -1.5 +1.5 dB 2.12 kHz, Modulator input level = 0 dBref S/NNICAM S/N of NICAM Baseband Signal 72 dB NICAM: -6 dB, 1 kHz, RMS unweighted 0 to 15 kHz, Vol = 9 dB NIC_Presc = 7Fh Output level 1 V RMS at DACp_s THD NICAM Total Harmonic Distortion + Noise of NICAM Baseband Signal 0.1 % 2.12 kHz, Modulator input level = 0 dBref BER NICAM NICAM: Bit Error Rate 1 10 -7 FM +NICAM, norm conditions fRNICAM NICAM Frequency Response, 20...15000 Hz -1.0 +1.0 dB Modulator input level = -12 dB dBref; RMS XTALK NICAM NICAM Crosstalk Attenuation (Dual) 80 dB SEP NICAM NICAM Channel Separation (Stereo) 80 dB FM Characteristics (MSP Standard Code = 3) dVFMOUT Tolerance of Output Voltage of FM Demodulated Signal DACp_s, SCn_OUT_s 1) -1.5 +1.5 dB 1 FM-carrier, 50 ms, 1 kHz, 40 kHz deviation; RMS S/NFM S/N of FM Demodulated Signal 73 dB 1 FM-carrier 5.5 MHz, 50 ms, 1 kHz, 40 kHz devi- ation; RMS, unweighted 0 to 15 kHz (for S/N); full input range, FM-Pres- c a l e=4 6h , V o l=0d B fi Output Level 1 V RMS at DACp_s THD FM Total Harmonic Distortion + Noise of FM Demodulated Signal 0.1 % fRFM FM Frequency Responses, 20...15000 Hz -1.0 +1.0 dB 1 FM-carrier 5.5 MHz, 50 ms, Modulator input level = -14.6 dBref; RMS XTALK FM FM Crosstalk Attenuation (Dual) 80 dB 2 FM-carriers 5.5/5.74 MHz, 50 ms, 1 kHz, 40 kHz deviation; Bandpass 1 kHz SEP FM FM Channel Separation (Stereo) 50 dB 2 FM-carriers 5.5/5.74 MHz, 50 ms, 1 kHz, 40 kHz deviation; RMS AM Characteristics (MSP Standard Code = 9) S/N AM(1) S/N of AM Demodulated Signal measurement condition: RMS/Flat DACp_s, SCn_OUT_s 1) 48 dB SIF level: 0.1 -0.8 Vpp AM-carrier 54% at 6.5 MHz Vol = 0 dB, FM/AM prescaler set for output = 0.5 V RMS at Loudspeaker out; Standard Code = 09 hex S/NAM(2) S/N of AM Demodulated Signal measurement condition: QP/CCIR 35 dB THD AM Total Harmonic Distortion + Noise of AM Demodulated Signal 0.6 % 1) “n” means “1”, “2”, “3”, or “4”; “s” means “L” or “R”; “p” means “Loudspeaker (Main)’’ or ‘‘Headphone (AUX)’’
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BTSC Characteristics (MSP Standard Code = 20hex, 21hex) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R or SAP, 100% modulation, 75ms deem- phasis, RMS unweighted 0 to 15 kHz THD BTSC THD +N of BTSC Stereo Signal THD +N of BTSC SAP Signal 0.1 0.5 1 kHz L or R or SAP, 100% 75 ms EIM2), DBX NR, RMS unweighted 0 to 15 kHz fR BTSC Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP, 50 Hz...9 kHz -0.5 -1.0 0.5 0.6 dB dB L or R or SAP, 1%...66% EIM2), DBX NR XTALK BTSC Stereo fi SAP SAP fi Stereo dB dB 1 kHz L or R or SAP, 100% modulation, 75ms deem- phasis, Bandpass 1 kHz SepBTSC Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz dB dB L or R 1%...66% EIM 2), DBX NR FM ThrPilot Pilot deviation threshold Stereo off fi on Stereo on fi off ANA_IN1+, ANA_IN2+ 3.2 1.2 3.5 1.5 kHz kHz
4.5 MHz carrier modulated
with fh=15.743 kHz SIF level=100mVpp indication: STATUS Bit[6] BTSC Characteristics (MSP Standard Code = 20hex, 21hex) with a minimum IF input signal level of 70 mVpp (measured without any video/chroma signal components) S/NBTSC S/N of BTSC Stereo Signal S/N of BTSC-SAP Signal DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R or SAP, 100% modulation, 75ms deem- phasis, RMS unweighted 0 to 15 kHz THD BTSC THD +N of BTSC Stereo Signal THD +N of BTSC SAP Signal 0.15 0.8 1 kHz L or R or SAP, 100% 75 ms EIM2), DBX NR, RMS unweighted 0 to 15 kHz fR BTSC Frequency Response of BTSC Stereo, 50 Hz...12 kHz Frequency Response of BTSC- SAP, 50 Hz...9 kHz -0.5 -1.0 0.5 0.6 dB dB L or R or SAP, 1%...66% EIM2), DBX NR XTALK BTSC Stereo fi SAP SAP fi Stereo dB dB 1 kHz L or R or SAP, 100% modulation, 75ms deem- phasis, Bandpass 1 kHz SepBTSC Stereo Separation 50 Hz...10 kHz 50 Hz...12 kHz dB dB L or R 1%...66% EIM 2), DBX NR 2) EIM refers to 75-ms Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-ms preemphasis network. Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 67 EIA-J Characteristics (MSP Standard Code = 30hex) S/NEIAJ S/N of EIA-J Stereo Signal S/N of EIAJ Sub-Channel DACp_s, SCn_OUT_s 1) dB dB 1 kHz L or R, 100% modulation, 75 ms deemphasis, RMS unweighted 0 to 15 kHzTHD EIAJ THD +N of EIA-J Stereo Signal THD +N of EIA-J Sub-Channel 0.2 0.3 fREIAJ Frequency Response of EIA-J Stereo, 50 Hz...12 kHz Frequency Response of EIA-J Sub-Channel, 50 Hz...12 kHz -0.5 -1.0 0.5 0.5 dB dB 100% modulation, 75 ms deemphasis XTALK EIAJ Main fi SUB Sub fi MAIN dB dB 1 kHz L or R, 100% modu- lation, 75ms deemphasis, Bandpass 1 kHz SEP EIAJ Stereo Separation 50 Hz...5 kHz 50 Hz...10 kHz dB dB EIA-J Stereo Signal, L or R 100% modulation FM-Radio Characteristics (MSP Standard Code = 40 hex) S/NUKW S/N of FM-Radio Stereo Signal DACp_s, SCn_OUT_s 1) 68 dB 1 kHz L or R, 100% modu- lation, 75ms deemphasis, RMS unweighted 0 to 15 kHz THD UKW THD +N of FM-Radio Stereo Signal 0.1 % fRUKW Frequency Response of FM-Radio Stereo 50 Hz...15 kHz tion, 75ms deemphasis Sep UKW Stereo Separation 50 Hz...15 kHz 45 dB 2) EIM refers to 75-ms Equivalent Input Modulation. It is defined as the audio-signal level which results in a stated percentage modulation, when the DBX encoding process is replaced by a 75-ms preemphasis network. Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions
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- Appendix A: Overview of TV-Sound Standards 5.1. NICAM 728 Table 5–1:Summary of NICAM 728 sound modulation parameters Specification I B/G L D/K Carrier frequency of digital sound 6.552 MHz 5.85 MHz 5.85 MHz 5.85 MHz Transmission rate 728 kbit/s Type of modulation Differentially encoded quadrature phase shift keying (DQPSK) Spectrum shaping Roll-off factor by means of Roll-off filters 1.0 0.4 0.4 0.4 Carrier frequency of analog sound component
6.0 MHz
5.5 MHz
6.5 MHz AM mono 6.5 MHz FM mono terrestrial cable Power ratio between vision carrier and analog sound carrier 10 dB 13 dB 10 dB 16 dB 13 dB Power ratio between analog and modulated digital sound carrier 10 dB 7 dB 17 dB 11 dB China/ Hungary Poland 12 dB 7 dB Table 5–2:Summary of NICAM 728 sound coding characteristics Characteristics Values Audio sampling frequency 32 kHz Number of channels 2 Initial resolution 14 bit/sample Companding characteristics near instantaneous, with compression to 10 bits/sample in 32-samples (1 ms) blocks Coding for compressed samples 2’s complement Preemphasis CCITT Recommendation J.17 (6.5 dB attenuation at 800 Hz) Audio overload level +12 dBm measured at the unity gain frequency of the preemphasis network (2 kHz)
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 69 5.2. A2-Systems Table 5–3:Key parameters for A2 Systems of Standards B/G, D/K, and M Characteristics Sound Carrier FM1 Sound Carrier FM2 TV-Sound Standard B/G D/K M B/G D/K M 6.7421875 4.724212 Vision/sound power difference 13 dB 20 dB Sound bandwidth 40 Hz to 15 kHz Preemphasis 50 ms7 5 ms5 0 ms7 5 ms Frequency deviation (nom/max) –27/–50 kHz –17/–25 kHz –27/–50 kHz –15/–25 kHz Transmission Modes Mono transmission mono mono Stereo transmission (L +R)/2 (L +R)/2 R (L -R)/2 Dual sound transmission language A language B Identification of Transmission Mode Pilot carrier frequency 54.6875 kHz 55.0699 kHz Max. deviation portion –2.5 kHz Type of modulation / modulation depth AM / 50% Modulation frequency mono: unmodulated stereo: 117.5 Hz dual: 274.1 Hz 149.9 Hz 276.0 Hz
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5.3. BTSC-Sound System 5.4. Japanese FM Stereo System (EIA-J) Table 5–4:Key parameters for BTSC-Sound Systems Aural Carrier BTSC-MPX-Components (L+R) Pilot (L-R) SAP Prof. Ch. Carrier frequency (fh = 15.734 kHz) 4.5 MHz Baseband f h 2 fh 5 fh 6.5 fh Preemphasis 75 msD B X D B X 1 5 0 ms Max. deviation to Aural Carrier 73 kHz (total) 25 kHz 1) 5k H z 5 0k H z 1) 15 kHz 3 kHz Max. Freq. Deviation of Subcarrier Modulation Type AM 10 kHz FM 3k H z FM 1) Sum does not exceed 50 kHz due to interleaving effects Table 5–5:Key parameters for Japanese FM-Stereo Sound System EIA-J Aural Carrier FM EIA-J-MPX-Components (L+R) (L-R) Identification Carrier frequency (fh = 15.734 kHz) 4.5 MHz Baseband 2 f h 3.5 fh Sound bandwidth 0.05 - 15 kHz 0.05 - 15 kHz - Preemphasis 75 ms7 5 msn o n e Max. deviation portion to Aural Carrier 47 kHz 25 kHz 20 kHz 2 kHz Max. Freq. Deviation of Subcarrier Modulation Type 10 kHz FM 60% AM Transmitter-sided delay 20 ms0 ms0 ms Mono transmission L +R - unmodulated Stereo transmission L +RL -R 982.5 Hz Bilingual transmission Language A Language B 922.5 Hz
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 71 5.5. FM Satellite Sound 5.6. FM-Stereo Radio Table 5–6:Key parameters for FM Satellite Sound Carrier Frequency Maximum FM Deviation Sound Mode Bandwidth Deemphasis
6.5 MHz 85 kHz Mono 15 kHz 50 ms
7.02/7.20 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.38/7.56 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive 7.74/7.92 MHz 50 kHz Mono/Stereo/Bilingual 15 kHz adaptive Table 5–7:Key parameters for FM-Stereo Radio Systems Aural Carrier FM-Radio-MPX-Components (L+R) Pilot (L-R) RDS/ARI Carrier frequency (fp = 19 kHz) 10.7 MHz Baseband f p 2 fp 3 fp Sound bandwidth in kHz 0.05 - 15 0.05 - 15 Preemphasis: - USA - Europe 75 ms 50 ms 75 ms 50 ms Max. deviation to Aural Carrier 75 kHz (100%) 1) Sum does not exceed 90% due to interleaving effects
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- Appendix B: Manual Mode To adapt the modes of the STANDARD SELECT regis- ter to individual requirements, the MSP 34x8G offers a Manual Mode, which provides sophisticated program- ming of the MSP 34x8G. After the setting of the STANDARD SELECT register, the MSP 34x8G is set up for optimal behavior. There- fore, it is not recommended to use the Manual mode. Only in those cases, where user specific requirements concerning detection, identification, or carrier positioning have to be met, can the Manual Mode be used. Note: In case of Automatic Sound Select (MODUS[0]=1), any modifications of the demodulator write registers listed below, except AUTO_FM/AM, are ignored. 6.1. Demodulator Write and Read Registers for Manual Mode Table 6–1:Demodulator Write Registers; Subaddress: 10 hex; these registers are not readable! Demodulator Write Registers Address (hex) MSP- Version Description Reset Mode Page AUTO_FM/AM 00 21 3418, 34581) 1. MODUS[0]=1 (Automatic Sound Select): Switching Level threshold of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 2. MODUS[0]=0 (Manual Mode): Activation and configuration of Automatic Switching between NICAM and FM/AM in case of bad NICAM reception 00 00 hex page A2_Threshold 00 22 A2 Stereo Identification Threshold 00 19 hex CM_Threshold 00 24 Carrier-Mute Threshold 00 2A hex DCO1_LO DCO1_HI DCO2_LO DCO2_HI 00 93 00 9B 00 A3 00 AB Increment channel 1 Low Part Increment channel 1 High Part Increment channel 2 Low Part Increment channel 2 High Part 00 00hex page 1) not in BTSC, EIA-J, and FM-Radio mode Table 6–2:Demodulator Read Registers; Subaddress: 11hex; these registers are not writable! Demodulator Read Registers Address (hex) MSP- Version Description Page C_AD_BITS 00 23 3410, 3450 NICAM-Sync bit, NICAM-C-Bits, and bit [2...0] of additional data bits page ADD_BITS 00 38 NICAM: bit [10...3] of additional data bits page CIB_BITS 00 3E NICAM: CIB1 and CIB2 control bits page ERROR_RATE 00 57 NICAM error rate, updated with 182 ms page
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 73 6.2. DSP Write and Read Registers for Manual Mode Table 6–3:DSP-Write Registers; Subaddress: 12hex, all registers are readable as well Write Register Address (hex) Bits Operational Modes and Adjustable Range Reset Mode Page Additional Channel Matrix Modes 00 08 00 09 00 0A 00 41 00 0B 00 0C [7..0] [SUM/DIFF, AB_XCHANGE, PHASE_CHANGE_B, PHASE_CHANGE_A, A_ONLY , B_ONLY] hex page FM Fixed Deemphasis 00 0F [15..8] [OFF, 50 ms, 75ms] OFF page FM Adaptive Deemphasis [7..0] [OFF, WP1] OFF page Identification Mode 00 15 [7..0] [B/G, M] B/G page Table 6–4:DSP Read Registers; Subaddress: 13hex, all registers are not writable Additional Read Registers Address (hex) Bits Output Range Page Stereo detection register for A2 Stereo Systems
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6.3. Manual Mode: Description of Demodulator Write Registers 6.3.1. Automatic Switching between NICAM and Analog Sound In case of bad NICAM reception or loss of the NICAM-carrier, the MSP 34x8G offers an Automatic Switching (fall back) to the analog sound (FM/AM- Mono), without the necessity of the controller reading and evaluating any parameters. If a proper NICAM sig- nal returns, switching back to this source is performed automatically as well. The feature evaluates the NICAM ERROR_RATE and switches, if necessary, all output channels which are assigned to the NICAM source, to the analog source, and vice versa. An appropriate hysteresis algorithm avoids oscillating effects (see Fig. 6–1). STATUS[9] and C_AD_BITS[11] (Addr: 0023 hex) provide information about the actual NICAM-FM/AM-status. 6.3.1.1. Function in Automatic Sound Select Mode The Automatic Sound Select feature (MODUS[0]=1) includes the procedure mentioned above. By default, the internal ERROR_RATE threshold is set to 700dec. i.e.: –N I C A M fi analog sound if ERROR_RATE > 700 – analog sound fi NICAM if ERROR_RATE < 700/2 The ERROR_RATE value of 700 corresponds to a BER of approximately 5.46*10-3/s. Individual configuration of the threshold can be done using Table 6–5, whereby the bits [0] and [11] of AUTO_FM are ignored. It is recommended to use the internal setting used by the standard selection. The optimum NICAM sound can be assigned to the MSP output channels by selecting one of the “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels. 6.3.1.2. Function in Manual Mode If the manual mode (MODUS[0]=0) is required, the activation and configuration of the Automatic Switching feature has to be done as described in Table 6–5. Note, that the channel matrix of the corresponding out- put channels must be set according to the NICAM mode and need not to be changed in the FM/AM-fallback case. Example: Required threshold = 500: bits [10..1]=00 1111 1010 Fig. 6–1:Hysteresis for automatic switching ERROR_RATE Selected Sound NICAM analog Sound thresholdthreshold/2 Table 6–5:Coding of Automatic NICAM/Analog Sound Switching; Reset Status: Mode 0 Mode Description AUTO_FM [11..0] Addr. = 00 21hex ERROR_RATE- Threshold/dec Source Select: Input at NICAM Path
0 Forced NICAM
(Automatic Switching disabled) Bit [0] = 0 Bits [10..1] = 0 Bit [11] = 0 none always NICAM; Mute in case of no NICAM available
1 Automatic Switching with
(Default, if Automatic Sound Select is on) Bit [0] = 1 Bit [10..1] = 0 Bit [11] = 0
700 NICAM or FM/AM,
ERROR_RATE
2 Automatic Switching with
(Customizing of Automatic Sound Select) Bit [0] = 1 = threshold/2 Bit [11] = 0 set by customer; recommended range: 50...2000
3 Forced Analog Mono
(Automatic Switching disabled) Bit [0] = 1 Bit [10..1] = 0 Bit [11] = 1 none always FM/AM 1) In case of Automatic Sound Select (MODUS[0] = 1), the NICAM path may be assigned to “Stereo or A/B”, “Stereo or A”, or “Stereo or B” source channels (see Table 2–2 on page 11). In case of Automatic Sound Select (MODUS[0] = 1), bit [0] of AUTO_FM is ignored
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 75 6.3.2. A2 Threshold The threshold between Stereo/Bilingual and Mono Identification for the A2 Standard has been made pro- grammable according to the user’s preferences. An internal hysteresis ensures robustness and stabil- ity. 6.3.3. Carrier-Mute Threshold The Carrier-Mute threshold has been made program- mable according to the users preferences. An internal hysteresis ensures stable behavior. Table 6–6:Write Register on I2C Subaddress 10hex: A2 Threshold Register Address Function Name THRESHOLDS 00 22hex (write) A2 THRESHOLD Register Defines threshold of all A2 and EIA_J standards for Stereo and Bilingual detection bit [11...0] 7F0hex force Mono Identification ... 190 hex default setting after reset ... 0A0hex minimum Threshold for stable detection recommended range: 0Ahex...3Chex A2_THRESH Table 6–7:Write Register on I2C Subaddress 10hex: Carrier-Mute Threshold Register Address Function Name THRESHOLDS 00 24hex (write) Carrier-Mute THRESHOLD Register Defines threshold for the carrier mute feature bit [6..0] 00hex Carrier-Mute always ON (both channels muted) ... 2Ahex default setting after reset ... FF hex Carrier-Mute always OFF (both channels forced on) recommended range: 14 hex...50hex CM_THRESH
MSP 3438G PRELIMINARY DATA SHEET
76 MICRONAS INTERMETALL
6.3.4. DCO-Registers Note: The use of this register is not recommended. It should be used only in cases where non-standard car- rier frequencies have to be processed. Please note, that the usage of user specific demodulation frequen- cies is not possible in combination with the Automatic Sound Select (MODUS[0]=1). When selecting a TV-sound standard by means of the STANDARD SELECT register, all frequency tuning is performed automatically. If manual setting of the tuning frequency is required, a set of 24-bit registers determining the mixing frequen- cies of the quadrature mixers can be written manually into the MSP. In Table 6–8, examples for DCO register programming are listed. It is necessary to separate these registers into two categories: low part and high part. The formula for the calculation of the INCR val- ues for any chosen IF frequency is as follows: INCR dec = int (f / fs × 224) with: int = integer function f = IF frequency in MHz f S = sampling frequency (18.432 MHz) Conversion of INCR into hex-format and separation of the 12-bit low and high parts lead to the required regis- ter values (DCO1_HI and _LO for MSP-Ch1, DCO2_HI and _LO for MSP-Ch2). Table 6–8: DCO registers for the MSP 34x8G; reset status: DCO_HI/LO = “00 00” DCO1_LO 00 93 hex, DCO1_HI 00 9Bhex; DCO2_LO 00 A3hex, DCO2_HI 00 ABhex IF-Freq. [MHz] DCO_HI [hex] DCO_LO [hex] IF-Freq. [MHz] DCO_HI [hex] DCO_LO [hex] 4.5 03 E8 00 00 5.04 5.5 5.58 5.7421875 04 60 04 C6 04 D8 04 FC 00 00 03 8E 00 00 00 AA 5.76 5.85 5.94 05 00 05 14 05 28 00 00 00 00 00 00 6.0 6.2 6.5 6.552 05 35 05 61 05 A4 05 B0 05 55 0C 71 07 1C 00 00 6.6 6.65 6.8 05 BA 05 C5 05 E7 0A AA 0C 71 01 C7 7.02 06 18 00 00 7.2 06 40 00 00 7.38 06 68 00 00 7.56 06 90 00 00
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 77 6.4. Manual Mode: Description of Demodulator Read Registers Note: This register should be used only in cases where software compatibility to the MSP 34x0D is required. Using the STANDARD SELECTION register together with the STATUS register provides a more economic way to program the MSP 34x8G and to retrieve information from the MSP. All registers except C_AD_BITs are 8 bits wide. They can be read out of the RAM of the MSP 34x8G. All transmissions take place in 16-bit words. The valid 8-bit data are the 8 LSBs of the received data word. If the Automatic Sound Select feature is not used, the NICAM or FM-identification parameters must be read and evaluated by the controller in order to enable appropriate switching of the channel select matrix of the baseband processing part. The FM-identification registers are described in Section 6.6.1. To handle the NICAM-sound and to observe the NICAM-quality, at least the registers C_AD_BITS and ERROR_RATE must be read and evaluated by the controller. Addi- tional data bits and CIB bits, if supplied by the NICAM transmitter, can be obtained by reading the registers ADD_BITS and CIB_BITS. 6.4.1. NICAM Mode Control/Additional Data Bits Register NICAM operation mode control bits and A[2..0] of the additional data bits. Format: Important: “S” = Bit[0] indicates correct NICAM-syn- chronization (S = 1). If S = 0, the MSP 3418/3458G has not yet synchronized correctly to frame and sequence, or has lost synchronization. The remaining read registers are therefore not valid. The MSP mutes the NICAM output automatically and tries to synchro- nize again as long as any NICAM standard is selected by the STANDARD SELECT register. The operation mode is coded by C4-C1 as shown in Table 6–9. Note: It is not necessary to read out and evaluate the C_AD_BITS. All evaluation is performed in the MSP and indicated in the STATUS register. 6.4.2. Additional Data Bits Register Contains the remaining 8 of the 11 additional data bits. The additional data bits are not yet defined by the NICAM 728 system. Format: 6.4.3. CIB Bits Register CIB bits 1 and 2 (see NICAM 728 specifications). Format: MSB C_AD_BITS 00 23hex LSB 1 1 . . . 76543210 Auto _FM ... A[2] A[1] A[0] C4 C3 C2 C1 S Table 6–9: NICAM operation modes as defined by the EBU NICAM 728 specification C4 C3 C2 C1 Operation Mode 0 0 0 0 Stereo sound (NICAMA/B), independent mono sound (FM1) 0 0 0 1 Two independent mono signals (NICAMA, FM1) 0 0 1 0 Three independent mono channels (NICAMA, NICAMB, FM1) 0 0 1 1 Data transmission only; no audio 1 0 0 0 Stereo sound (NICAMA/B), FM1 carries same channel 1 0 0 1 One mono signal (NICAMA). FM1 carries same channel as NICAMA 1 0 1 0 Two independent mono channels (NICAMA, NICAMB). FM1 carries same channel as NICAMA 1 0 1 1 Data transmission only; no audio x 1 x x Unimplemented sound coding option (not yet defined by EBU NICAM 728 specification) AUTO_FM: monitor bit for the AUTO_FM Status: 0: NICAM source is NICAM 1: NICAM source is FM MSB ADD_BITS 00 38hex LSB 76543210 MSB CIB_BITS 00 3Ehex LSB 76543210 xxxxxx C I B 1 C I B 2
MSP 3438G PRELIMINARY DATA SHEET
78 MICRONAS INTERMETALL
6.4.4. NICAM Error Rate Register Average error rate of the NICAM reception in a time interval of 182 ms, which should be close to 0. The ini- tial and maximum value of ERROR_RATE is 2047. This value is also active if no NICAM-standard is selected. Since the value is achieved by filtering, a cer- tain transition time (approx. 0.5 sec) is unavoidable. Acceptable audio may have error rates up to a value of 700 dec. Individual evaluation of this value by the con- troller and an appropriate threshold may define the fall- back mode from NICAM to FM/AM-Mono in case of poor NICAM reception. The bit error rate per second (BER) can be calculated by means of the following formula: BER = ERROR_RATE * 12.3*10 -6 /s 6.4.5. Automatic Search Function for FM-Carrier Detection in Satellite Mode The AM demodulation ability of the MSP family offers the possibility to calculate the “field strength” of the momentarily selected FM carrier, which can be read out by the controller. In SAT receivers, this feature can be used to imple- ment an automatic FM carrier search. For this, the MSP has to be switched to AM-mode (Standard Select Register = 09 hex), FM-Prescale must be set to 7Fhex = +127dec, and the FM DC notch must be switched off (see Section 6.6.2. on page 80). The sound-IF frequency range must now be “scanned” in the MSP-channel 2 by means of the programmable quadrature mixer (see Section 6.3.4. on page 76) with an appropriate incremental frequency (i.e. 10 kHz). After each incrementation, a field strength value is available at the quasi-peak detector output (quasi- peak detector source must be set to FM), which must be examined for relative maxima by the controller. This results in either continuing search or switching the MSP back to FM demodulation mode. The absolute field strength value (can be read out of “quasi-peak detector output FM1”) gives information on whether a main FM carrier or a subcarrier was detected. As a practical consequence, the appropriate standard can be selected (Astra/Eutelsat Subcarrier = Standard 51 hex, Astra Main Carrier = 50hex, Eutelsat Main Carrier = 06hex). If the DCO setting for the selected standard differs from the preset, the correct DCO coefficients must be transmitted afterwards (e.g. 7.38/7.56 MHz Radio on Astra). Due to the fact that a constant demodulation frequency offset of a few kHz leads to a DC level in the demodu- lated signal, further fine tuning of the found carrier can be achieved by evaluating the “DC Level Readout FM1”. Therefore, the FM DC Notch must be switched on in FM demodulation mode. An example of the automatic search function is real- ized in the MSPX Windows software. ERROR_RATE 00 57hex Error free 0000 hex maximum error rate 07FF hex
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 79 6.5. Manual Mode: Description of DSP Write Registers 6.5.1. Additional Channel Matrix Modes This table shows additional modes for the channel matrix registers. The sum/difference mode can be used together with the quasi-peak detector to determine the sound mate- rial mode. If the difference signal on channel B (right) is near to zero, and the sum signal on channel A (left) is high, the incoming audio signal is mono. If there is a significant level on the difference signal, the incoming audio is stereo. 6.5.2. FM Fixed Deemphasis 6.5.3. FM Adaptive Deemphasis Note: The Adaptive Deemphasis WP1 requires setting of fixed deemphasis to 75ms. 6.5.4. NICAM Deemphasis A J17 Deemphasis is always applied to the NICAM signal. It is not switchable. Loudspeaker Matrix 00 08hex L Headphone Matrix 00 09hex L SCART1 Matrix 00 0Ahex L SCART2 Matrix 00 41hex L I2S Matrix 00 0Bhex L Quasi-Peak Detector Matrix 00 0Chex L SUM/DIFF 0100 0000 40 hex AB_XCHANGE 0101 0000 50 hex PHASE_CHANGE_B 0110 0000 60 hex PHASE_CHANGE_A 0111 0000 70 hex A_ONLY 1000 0000 80 hex B_ONLY 1001 0000 90 hex FM Deemphasis 00 0Fhex H 50 ms 0000 0000 00 hex RESET 75 ms 0000 0001 01 hex OFF 0011 1111 3F hex FM Adaptive Deemphasis WP1 00 0Fhex L OFF 0000 0000 00 hex RESET WP1 0011 1111 3F hex
MSP 3438G PRELIMINARY DATA SHEET
80 MICRONAS INTERMETALL
6.5.5. Identification Mode for A2 Stereo Systems To shorten the response time of the identification algo- rithm after a program change between two FM-Stereo capable programs, the reset of the ident-filter can be applied. Sequence: 1. Program change 2. Reset ident-filter 3. Set identification mode back to standard B/G or M 4. Read stereo detection register 6.6. Manual Mode: Description of DSP Read Registers All readable registers are 16-bit wide. Transmissions via I 2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writable. 6.6.1. Stereo Detection Register for A2 Stereo Systems Note: It is not necessary to read out and evaluate the A2 identification level. All evaluation is performed in the MSP and indicated in the STATUS register. 6.6.2. DC Level Register The DC level register measures the DC component of the incoming FM signals (FM1 and FM2). This can be used for seek functions in satellite receivers and for IF FM frequencies fine tuning. A too low demodulation frequency (DCO) results in a positive DC-level and vice versa. For further processing, the DC content of the demodulated FM signals is suppressed. The time constant t, defining the transition time of the DC Level Register, is approximately 28 ms. 6.7. Demodulator Source Channels in Manual Mode 6.7.1. Terrestrial Sound Standards Table 6–10 shows the source channel assignment of the demodulated signals in case of manual mode for all terrestrial sound standards. See Table 2–2 for the assignment in the Automatic Sound Select mode. In manual mode for terrestrial sound standards, only two demodulator sources are defined. 6.7.2. SAT Sound Standards Table 6–11 shows the source channel assignment of the demodulated signals for SAT sound standards. Identification Mode 00 15hex L Standard B/G (German Stereo) 0000 0000 00 hex RESET Standard M (Korean Stereo) 0000 0001 01 hex Reset of Ident-Filter 0011 1111 3F hex Stereo Detection Register 00 18hex H Stereo Mode Reading (two’s complement) MONO near zero STEREO positive value (ideal reception: 7Fhex) BILINGUAL negative value (ideal reception: 80hex) DC Level Readout FM1 (MSP-Ch2) 00 1Bhex H +L DC Level Readout FM2 (MSP-Ch1) 00 1Chex H +L DC Level [8000 hex ... 7FFFhex] values are 16 bit two’s complement
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 81 Table 6–10:Manual Sound Select Mode for Terrestrial Sound Standards Source Channels of Sound Select Block Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM Matrix FM/AM (use 0 for channel select) Stereo or A/B (use 1 for channel select) B/G-FM D/K-FM M-Korea M-Japan 04, 05 MONO Sound A Mono Mono Mono STEREO German Stereo Korean Stereo Stereo Stereo BILINGUAL, Languages A and B No Matrix Left = A Right = B Left = A Right = B B/G-NICAM L-NICAM I-NICAM D/K-NICAM D/K-NICAM (with high deviation FM) NICAM not available or NICAM error rate too high Sound A Mono analog Mono no sound with AUTO_FM: analog Mono MONO Sound A Mono analog Mono NICAM Mono STEREO Sound A Mono analog Mono NICAM Stereo BILINGUAL, Languages A and B Sound A Mono analog Mono Left = NICAM A Right = NICAM B M-BTSC MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo MONO + SAP Sound A Mono Mono Mono STEREO + SAP Korean Stereo Stereo Stereo MONO Sound A Mono Mono Mono STEREO MONO + SAP No Matrix Left = Mono Right = SAP Left = Mono Right = SAPSTEREO + SAP FM-Radio 40 MONO Sound A Mono Mono Mono STEREO Korean Stereo Stereo Stereo Table 6–11:Manual Sound Select Modes for SAT-reception (FM Matrix is set automatically) Source Channels of Sound Select Block for SAT-Modes Broadcasted Sound Standard Selected MSP Standard Code Broadcasted Sound Mode FM/AM (source select: 0) Stereo or A/B (source select: 1) Stereo or A (source select: 3) Stereo or B (source select: 4) FM SAT 6, 50hex MONO Mono Mono Mono Mono 51hex STEREO Stereo Stereo Stereo Stereo BILINGUAL Left = A (FM1) Right = B (FM2) Left = A (FM1) Right = B (FM2) A (FM1) B (FM2)
MSP 3438G PRELIMINARY DATA SHEET
82 MICRONAS INTERMETALL
6.8. Exclusions of Audio Baseband Features In general, all functions can be switched independently. Two exceptions exist: 1. NICAM cannot be processed simultaneously with secondary channel (see Fig. 2–2 and Fig. 2–3 on page 10). 2. FM adaptive deemphasis cannot be processed simultaneously with FM-identification. 6.9. Phase Relationship of Analog Outputs The analog output signals: Loudspeaker, Aux, and SCART2 all have the same phases. The SCART1 out- put has opposite phase. Using the I2S-outputs for other DSPs or D/A convert- ers, care must be taken to adjust for the correct phase. Fig. 6–2:Phase diagram of the MSP 34x8G SCART2-Ch. SCART1 SCART1 SCART2 SCART4 SCART3 MONO Loudspeaker Audio SCART DSP Input Select SCART Output Select Baseband Processing Aux SCART1-Ch. SCART2 I2S_OUT1/2I2S_IN1/2/3 MONO, SCART1...4
PRELIMINARY DATA SHEET MSP 3438G MICRONAS INTERMETALL 83 7. Appendix C: Application Circuit SC1_OUT_L (37) 47 SC1_OUT_R (36) 48 SC2_OUT_L (34) 50 SC2_OUT_R (33) 51 45 (39) AHVSUP 43 (44) AHVSS 26 (66) AVSUP 67 (13) DVSUP 66 (16) DVSS 61 (21) RESETQ 27 (62) AVSS 49 (35) VREF1 58 (26) VREF2
5 V 5 V 8 V
CAPL_M (40) 44 CAPL_A (38) 46 VREFTOP (58) 29 AGNDC (45) 42 ANA_IN1+ (67) 25 ANA_IN2+ (69) 23 ANA_IN - (68) 24 XTAL_IN (71) 21 XTAL_OUT (72) 20 MSP 34x8G D_CTR_I/O_0 (78) 13 D_CTR_I/O_1 (77) 14 AUD_CL_OUT (74) 18 TESTEN (70) 22 100 W 100 W 100 W 100 W 22 mF 22 mF 22 mF 22 mF DACA_R (24) 60 1 nF 1 nF 1 nF 1 nF DACA_L (25) 59 DACM_R (27) 57 DACM_L (28) 56 1 mF 1 mF 1 mF 1 mF Loudspeaker Tuner 1 Tuner 2 IF 2 IN Signal GND IF 1 IN 56 pF 56 pF 56 pF + 3.3 mF 100 nF 100 nF mF if ANA_IN2+ 8V ( 5V ) 18.432 MHz 10 mF1 0 mF 28 (60) MONO_IN 31 (56) SC1_IN_L 30 (57) SC1_IN_R 32 (55) ASG1 34 (53) SC2_IN_L 33 (54) SC2_IN_R 35 (52) ASG2 37 (50) SC3_IN_L 36 (51) SC3_IN_R 38 (49) ASG3 40 (47) SC4_IN_L 39 (48) SC4_IN_R 11 (80) STANDBYQ 12 (79) ADR_SEL 8 (3) I2C_DA 9 (2) I2C_CL 1 (75) ADR_WS 68 (10) ADR_CL 3 (8) ADR_DA 6 (5) I2S_WS 7 (4) I2S_CL 4 (7) I2S_DA_IN1 65 (17) I2S_DA_IN2/3 5 (6) I2S_DA_OUT 220 pF Alternative circuit for ANA_IN1+ for more attenuation of video 100 pF 56 pF 1 kW ANA_IN1+ AHVSS AHVSS AHVSS 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF 330 nF DVSS DVSS AVSS components: C s. section 4.6.2. RESETQ (from Controller, see section 4.6.3.3.) Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PQFP80 package. 1.5 nF 470 pF mF 1.5 nF 470 pF mF 1.5 nF 470 pF mF - (22) I2S_DA_IN3 62 (20) I2S_WS_3 63 (19) I2S_CL_3 FM- Modulator Headphone DVSS AHVSS(5 V) not used AHVSS AHVSS
MSP 3438G PRELIMINARY DATA SHEET
84 MICRONAS INTERMETALL
All information and data contained in this data sheet is without any commitment, is not to be considered as an offer for conclu- sion of a contract nor shall it be construed as to create any lia- bility. Any new issue of this data sheet invalidates previous issues. Product availability and delivery dates are exclusively subject to our respective order confirmation form; the same ap- plies to orders based on development samples delivered. By this publication, MICRONAS INTERMETALL GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Reprinting is generally permitted, indicating the source. However, our prior consent must be obtained in all cases. MICRONAS INTERMETALL GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@intermetall.de Internet: http://www.intermetall.de Printed in Germany Order No. 6251-494-1PD 8. Data Sheet History 1. Preliminary data sheet: “MSP 3438G Multistandard Sound Processor Family”, Edition July 27, 1999, 6251-494-1PD. First release of the preliminary data sheet.