BSP3505D

Micronas

Baseband Sound Processor

Manufacturer: Micronas

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2 Micronas

Edition Oct. 21, 1998 6251-481-1PD PRELIMINA RY DATA SHEET MIC R ONAS MICRONAS

PRELIMINARY DATA SHEET BSP 3505D 3Micronas Contents, continued Page Section Title 21 5. Specifications 21 5.1. Outline Dimensions 23 5.2. Pin Connections and Short Descriptions 26 5.3. Pin Configurations 30 5.4. Pin Circuits 31 5.5. Electrical Characteristics 31 5.5.1. Absolute Maximum Ratings 32 5.5.2. Recommended Operating Conditions 34 5.5.3. Characteristics 37 6. Application Circuit 40 7. Appendix A: BSP 3505D Version History 40 8. Data Sheet History

BSP 3505D PRELIMINARY DATA SHEET

4 Micronas

Release Notes: The hardware description in this document is valid for the BSP 3505D version A2. 1. Introduction The BSP 3505D is designed as a single-chip Baseband Sound Processor for applications in analog and digital TV sets, video recorders, and satellite receivers. The IC is produced in submicron CMOS technology, and is fully pin and software compatible to the MSP 34xx family. The BSP 3505D is available in a PLCC68, PSDIP64, PSDIP52, PQFP80, and in a PQFP44 pack- age. Note: The BSP 3505D version has reduced control reg- isters and less functional pins. The remaining registers are software compatible to the MSP 34xxD. The pinning is compatible to the MSP 34xxD. 1.1. BSP 3505D Integrated Functions – Stereo baseband input via integrated A/D converters – Two stereo D/A converters – AVC: Automatic Volume Correction – Bass, treble, volume, loudness processing – Full SCART in/out matrix without restrictions – spatial effect (pseudostereo / basewidth enlargement) – Digital control output pins D_CTR_OUT0/1 – Reduction of necessary controlling – Less external components 1.2. Features of the DSP-Section – flexible selection of audio sources to be processed – digital baseband processing: volume, bass, treble, loudness, and spatial effects – simple controlling of volume, bass, treble, loudness, and spatial effects 1.3. Features of the Analog Section – two selectable analog stereo audio baseband inputs (= two SCART inputs) input level: ≤2 V RMS, input impedance: ≥25 kΩ – one selectable analog mono input: input level: ≤2 V RMS, input impedance: ≥15 kΩ – stereo high-quality A/D converter, S/N-Ratio: ≥85 dB – 20 Hz to 20 kHz bandwidth for SCART-to-SCART- copy facilities – loudspeaker: stereo four-fold oversampled D/A-con- verter output level per channel: max. 1.4 VRMS output resistance: max. 5 kΩ S/N-ratio: ≥85 dB at maximum volume max. noise voltage in mute mode: ≤10 µV (BW: 20 Hz ...16 kHz) – stereo four-fold oversampled D/A converter supplying a stereo SCART-output output level per channel: max. 2 V RMS, output resistance: max. 0.5 kΩ , S/N-Ratio: ≥85 dB (20 Hz...16 kHz) Fig. 1–2: Main I/O Signals BSP 3505D MONO IN SCART1 IN 2 SCART2 IN 2 BSP 3505D I2C2 SCART OUT Loudspeaker OUT Tuner SIF VIF SCART1 BSP 3505D Loudspeaker SCART Inputs SCART Output SCART1 SCART2 Fig. 1–1: Typical BSP 3505D application FM/AM Mono

BSP 3505DPRELIMINARY DATA SHEET 5Micronas 2. Architecture of the BSP 3505D Fig. 2–2 shows a simplified block diagram of the IC. Its architecture is split into two main functional blocks: 1. DSP (digital signal processing) section performing audio baseband processing 2. analog section containing two A/D-converters, four D/A-converters, and SCART-switching facilities. 2.1. Analog Section and SCART Switching Facilities The analog input and output sections include full matrix switching facilities, which are shown in Fig. 2–1. The switches are controlled by the ACB bits defined in the audio processing interface (see section 4. Program- ming the BSP 3505D). 2.1.1. Standby Mode If the BSP 3505D is switched off by first pulling STAND- BYQ low, and then disconnecting the 5 V, but keeping the 8 V power supply (‘Standby’-mode ), the switches S1 and S2 (see Fig. 2–1) maintain their position and function. This facilitates the copying from selected SCART-inputs to SCART-output in the TV-set’s standby mode. In case of power-on start or starting from standby, the IC switches automatically to the default configuration, shown in Fig. 2–1. This action takes place after the first I 2C transmission into the DSP part. By transmitting the ACB register first, the individual default setting mode of the TV set can be defined. Fig. 2–1: SCART-Switching Facilities (see 4.4.12.) positions show the default configuration after Power On Reset. Note: SCART_OUT is undefined after RESET! SCART_IN SC1_IN_L/R SC2_IN_L/R from Audio Baseband Processing (DSP_OUT) SCART_OUT SC1_OUT_L/R to Audio Baseband Processing (DSP_IN) A D D A MONO_IN SCART1_L/R SCARTL/R Pins intern. Sig- nal Lines DSP Loudspeaker DACM_L SC1_OUT_L Mono SCART1 SCART2 D/A D/A D/A D/A SCART SCARTL SCARTR SCART1_L SCART1_R LOUD- SPEAKER R LOUD- SPEAKER L A/D A/D DACM_R SC1_OUT_R MONO_IN SC1_IN_L SC1_IN_R SC2_IN_L SC2_IN_R Fig. 2–2: Architecture of the BSP 3505D SCART Switching Facilities XTAL_IN Clock XTAL_OUT D_CTR_OUT0/1

BSP 3505D PRELIMINARY DATA SHEET

6 Micronas

2.2. BSP 3505D Audio Baseband Processing All audio baseband functions are performed by digital signal processing (DSP). The DSP functions are grouped into three processing parts: input preproces- sing, channel source selection, and channel postpro- cessing (see Fig. 2–3). The input preprocessing is intended to form a standard- ized signal level. All input and output signals can be processed simulta- neously. 2.3. Clock and Crystal Specifications Remark on using the crystal: External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match the center of the tolerance range between 18.433 and 18.431 MHz as closely as possible. 2.4. Digital Control Output Pins The static level of two output pins of the BSP 3505D (D_CTR_OUT0/1) is switchable between HIGH and LOW by means of the I 2C-bus. This enables the control- ling of external hardware controlled switches or other devices via I 2C-bus (see section 4.4.11.) Beeper Prescale SCART Fig. 2–3: Audio Baseband Processing (DSP-Firmware) Internal signal lines (see Fig. 2–1)SCART Analog Inputs Loudspeaker Channel Matrix Bass Treble Volume SCART1 Channel Matrix Volume Loudspeaker L Loudspeaker R SCART1_L SCART1_R Channel Souce Select Loudspeaker Outputs SCART Output Balance SCARTL SCARTR Quasi-Peak Detector Quasi peak readout R Quasi peak readout L AVC Loudness/C0525

BSP 3505DPRELIMINARY DATA SHEET 7Micronas 3. I2C Bus Interface: Device and Subaddresses As a slave receiver, the BSP 3505D can be controlled via I2C bus. Access to internal memory locations is achieved by subaddressing. The DSP processor part has its own subaddressing register bank. In order to allow for more BSP or MSP ICs to be con- nected to the control bus, an ADR_SEL pin has been im- plemented. With ADR_SEL pulled to high, low, or left open, the BSP 3505D responds to changed device ad- dresses. Thus, three identical devices can be selected. By means of the RESET bit in the CONTROL register, all devices with the same device address are reset. The IC is selected by asserting a special device address in the address part of an I 2C transmission. A device ad- dress pair is defined as a write address (80, 84, or 88hex) and a read address (81, 85, or 89hex). Writing is done by sending the device write address first, followed by the subaddress byte, two address bytes, and two data by- tes. Reading is done by sending the device write ad- dress, followed by the subaddress byte and two address bytes. Without sending a stop condition, reading of the addressed data is completed by sending the device read address (81, 85, or 89 hex) and reading two bytes of data. Refer to Fig. 3–1: I2C Bus Protocol and section 3.2. Pro- posal for BSP 3505D I2C Telegrams. Due to the internal architecture of the BSP 3505D the IC cannot react immediately to an I2C request. The typical response time is about 0.3 ms for the DSP processor part. If the receiver (BSP) can’t receive another com- plete byte of data until it has performed some other func- tion; for example, servicing an internal interrupt, it can hold the clock line I 2C_CL LOW to force the transmitter into a wait state. The positions within a transmission where this may happen are indicated by ’Wait’ in section 3.1. The maximum Wait-period of the BSP during normal operation mode is less than 1 ms. I 2C-Bus conditions caused by BSP hardware problems: In case of any internal error, the BSPs wait-period is ex- tended to 1.8 ms. Afterwards, the BSP does not ac- knowledge (NAK) the device address. The data line will be left HIGH by the BSP and the clock line will be re- leased. The master can then generate a STOP condition to abort the transfer. By means of NAK, the master is able to recognize the er- ror state and to reset the IC via I 2C-Bus. While transmit- ting the reset protocol (s. 5.2.4.) to ‘CONTROL ’, the master must ignore the not acknowledge bits (NAK) of the BSP. A general timing diagram of the I2C Bus is shown in Fig. 3–2. Table 3–1: I2C Bus Device Addresses ADR_SEL Low High Left Open Mode Write Read Write Read Write Read BSP device address 80hex 81hex 84hex 85hex 88hex 89hex Table 3–2: I2C Bus Subaddresses Name Binary Value Hex Value Mode Function CONTROL 0000 0000 00 Write software reset TEST 0000 0001 01 Write only for internal use WR_DSP 0001 0010 12 Write write address DSP RD_DSP 0001 0011 13 Write read address DSP

BSP 3505D PRELIMINARY DATA SHEET

8 Micronas

Table 3–3: Control Register (Subaddress: 00hex) Name Subaddress MSB 14 13..1 LSB CONTROL 00hex 1 : RESET 0 : normal 0 0 0 3.1. Protocol Description Write to DSP S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte lowACK data-byte highACK data-byte lowACK P Read from DSP S write device address Wait ACK sub-addr ACK addr-byte high ACK addr-byte low ACK S read device address Wait ACK data-byte high ÇÇÇ Ç Ç Ç ÇÇÇ ACK data-byte low ÇÇÇ Ç Ç Ç ÇÇÇ NAK P Write to Control or Test Registers S write device address Wait ACK sub-addr ACK data-byte high ACK data-byte low ACK P Note:S = I 2C-Bus Start Condition from master P = I 2C-Bus Stop Condition from master ACK = Acknowledge-Bit: LOW on I2C_DA from slave (=BSP , gray) or master (=CCU, hatched) NAK = Not Acknowledge-Bit: HIGH on I2C_DA from master (=CCU, hatched) to indicate ‘End of Read’ or from BSP indicating internal error state Wait = I2C-Clock line held low by the slave (=BSP) while interrupt is serviced (<1.8 ms) Fig. 3–1: I2C bus protocol I2C_DA I2C_CL SP (MSB first; data must be stable while clock is high) (Data: MSB first)

BSP 3505DPRELIMINARY DATA SHEET 9Micronas I2C_CL I2C_DA as input I2C_DA as output FI2C TI2C3 TI2C1 TI2C5 TI2C6 TI2C2 TI2COL2 TI2COL1 TI2C4 Fig. 3–2: I2C bus timing diagram 3.2. Proposal for BSP 3505D I2C Telegrams 3.2.1. Symbols daw write device address dar read device address < Start Condition > Stop Condition aa Address Byte dd Data Byte 3.2.2. Write Telegrams <daw 00 d0 00>write to CONTROL register <daw 12 aa aa dd dd>write data into DSP 3.2.3. Read Telegrams <daw 13 aa aa <dar dd dd> read data from DSP 3.2.4. Examples <80 00 80 00>RESET BSP statically <80 00 00 00>clear RESET <80 12 00 08 02 20>set loudspeaker channel source to SCART, stereo

BSP 3505D PRELIMINARY DATA SHEET

10 Micronas

3.3. Start Up Sequence: Power Up and I2C-Controlling After power on or RESET (see Fig. 3–3), the IC is in an inactive state. The CCU has to transmit the required co- efficient set for a given operation via the I 2C bus. Initial- ization must start with the MODE Register. The reset pin should not be >0.45*DVSUP (see recom- mended conditions) before the 5 Volt digital power sup- ply (DVSUP) and the analog power supply (AVSUP) are >4.75 Volt AND the BSP clock is running. (Delay: 0.5 ms typ, 2 ms max) This means, if the reset low–high edge starts with a delay of 2 ms after DVSUP and AVSUP >4,75 Volt, even under worst case conditions, the reset is ok. DVSUP/V AVSUP/V time / ms 4.75 Oscillator time / ms 0.45 * DVSUP min. 2 time / ms RESETQ max. 2 Fig. 3–3: Power-up sequence Note: The reset should not reach high level be- fore the oscillator has started. This requires a reset delay of >2 ms

BSP 3505DPRELIMINARY DATA SHEET 11Micronas 4. Programming the BSP 3505D 4.1. Register ‘MODE_REG ’ The register ‘MODE_REG ’ contains the control bits de- termining the operation mode of the BSP 3505D; Table 4–1 explains all bit positions. Table 4–1: Control word ‘MODE_REG ’: All bits are “0” after power-on-reset Register Protocol Write Address (hex) Function MODE_REG long 0083 mode register Bit Function Comment Definition [0] not used must be 0 [1] DCTR_TRI Digital_Control_Output tristate 0 : active 1 : tristate [2] not used must be 1 [3–4] not used must be 0 [5] not used must be 1 [6–9] not used must be 0 [10–15] not used must be 0

BSP 3505D PRELIMINARY DATA SHEET

12 Micronas

4.2. DSP Write Registers: Table and Addresses Table 4–2: DSP Write Registers; Subaddress: 12hex; if necessary these registers are readable as well. DSP Write Register Address High/ Low Adjustable Range, Operational Modes Reset Mode Volume loudspeaker channel 0000hex H [+12 dB ... –114 dB, MUTE] MUTE Volume / Clipping Mode loudspeaker L 1/8 dB Steps / Reduce Vol., Tone, Comprom.00hex Balance loudspeaker channel [L/R]0001hex H [0..100 / 100 % and vv][–127..0 / 0 dB and vv]100%/100% Balance Mode loudspeaker L [Linear mode / logarithmic mode] linear mode Bass loudspeaker channel 0002hex H [+12 dB ... –12 dB] 0 dB Treble loudspeaker channel 0003hex H [+12 dB ... –12 dB] 0 dB Loudness loudspeaker channel 0004hex H [0 dB ... +17 dB] 0 dB Loudness Filter Characteristic L [NORMAL, SUPER_BASS] NORMAL Spatial effect mode/customize L [SBE, SBE+PSE] SBE+PSE Volume / Mode SCART1 channel L [Linear mode / logarithmic mode] linear mode Loudspeaker channel source 0008hex H [SCART] FM/AM Loudspeaker channel matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA SCART1 channel source 000Ahex H [SCART] FM/AM SCART1 channel matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA ÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉ Quasi-peak detector source ÉÉÉÉ ÉÉÉÉ 000C hex ÉÉÉ ÉÉÉ H ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ ÉÉÉÉÉÉÉÉÉÉÉÉÉÉ [SCART] ÉÉÉÉÉÉ ÉÉÉÉÉÉ FM/AM Quasi-peak detector matrix L [SOUNDA, SOUNDB, STEREO, MONO] SOUNDA Prescale SCART 000D hex H [00hex ... 7Fhex] 00hex ACB Register (SCART Switching Facilities) 0013hex H/L Bits [15..0] 00hex Automatic Volume Correction 0029hex H [off, on, decay time] off 4.3. DSP Read Registers: Table and Addresses Table 4–3: DSP Read Registers; Subaddress: 13hex DSP Read Register Address High/Low Output Range Quasi peak readout left 0019hex H&L [00hex ... 7FFFhex] 16 bit two’s complement Quasi peak readout right 001Ahex H&L [00hex ... 7FFFhex] 16 bit two’s complement

BSP 3505DPRELIMINARY DATA SHEET 13Micronas 4.4. DSP Write Registers: Functions and Values Write registers are 16 bit wide, whereby the MSB is de- noted bit [15]. Transmissions via I2C bus have to take place in 16-bit words. Some of the defined 16-bit words are divided into low [7..0] and high [15..8] byte, or in an other manner, thus holding two different control entities. All write registers are readable. Unused parts of the 16-bit registers must be zero. Addresses not given in this table must not be written at any time! 4.4.1. Volume Loudspeaker Channel Volume Loudspeaker 0000hex [15..4] +12 dB 0111 1111 0000 7F0 hex +11.875 dB 0111 1110 1110 7EE hex +0.125 dB 0111 0011 0010 732 hex 0 dB 0111 0011 0000 730 hex –0.125 dB 0111 0010 1110 72E hex –113.875 dB 0000 0001 0010 012 hex –114 dB 0000 0001 0000 010 hex Mute 0000 0000 0000 000 hex RESET Fast Mute 1111 1111 1110 FFE hex The highest given positive 8-bit number (7Fhex) yields in a maximum possible gain of 12 dB. Decreasing the vol- ume register by 1 LSB decreases the volume by 1 dB. Volume settings lower than the given minimum mute the output. With large scale input signals, positive volume settings may lead to signal clipping. The BSP 3505D loudspeaker volume function is divided up in a digital and an analog section. With Fast Mute, volume is reduced to mute position by digital volume only. Analog volume is not changed. This reduces any audible DC plops. Going back from Fast Mute should be done to the volume step before Fast Mute was activated. Clipping Mode Loudspeaker 0000hex [3..0] Reduce Volume 0000 0 hex RESET Reduce Tone Control 0001 1 hex Compromise Mode 0010 2 hex If the clipping mode is set to “Reduce Volume”, the fol- lowing clipping procedure is used: To prevent severe clipping effects with bass or treble boosts, the internal volume is automatically limited to a level where, in com- bination with either bass or treble setting, the amplifica- tion does not exceed 12 dB. If the clipping mode is “Reduce Tone Control”, the bass or treble value is reduced if amplification exceeds 12 dB. If the clipping mode is “Compromise Mode”, the bass or treble value and volume are reduced half and half if am- plification exceeds 12 dB. Example: Vol.: +6 dB Bass: +9 dB Treble: +5 dB Red. Volume 3 9 5 Red. Tone Con. 6 6 5 Compromise 4.5 7.5 5

BSP 3505D PRELIMINARY DATA SHEET

14 Micronas

4.4.2. Balance Loudspeaker Channel Positive balance settings reduce the left channel without affecting the right channel; negative settings reduce the right channel leaving the left channel unaffected. In lin- ear mode, a step by 1 LSB decreases or increases the balance by about 0.8% (exact figure: 100/127). In loga- rithmic mode, a step by 1 LSB decreases or increases the balance by 1 dB. Balance Mode Loudspeaker 0001hex [3..0] linear 0000 0 hex RESET logarithmic 0001 1 hex Linear Mode Balance Loudspeaker Channel [L/R] 0001hex H Left muted, Right 100%0111 1111 7F hex Left 0.8%, Right 100% 0111 1110 7E hex Left 99.2%, Right 100%0000 0001 01 hex Left 100%, Right 100% 0000 0000 00 hex RESET Left 100%, Right 99.2%1111 1111 FF hex Left 100%, Right 0.8% 1000 0010 82 hex Left 100%, Right muted1000 0001 81 hex Logarithmic Mode Balance Loudspeaker Channel [L/R] 0001hex H Left –127 dB, Right 0 dB 0111 1111 7F hex Left –126 dB, Right 0 dB 0111 1110 7E hex Left –1 dB, Right 0 dB 0000 0001 01 hex Left 0 dB, Right 0 dB 0000 0000 00 hex RESET Left 0 dB, Right –1 dB 1111 1111 FF hex Left 0 dB, Right –127 dB 1000 0001 81 hex Left 0 dB, Right –128 dB 1000 0000 80 hex 4.4.3. Bass Loudspeaker Channel Bass Loudspeaker 0002hex H +20 dB 0111 1111 7F hex +18 dB 0111 1000 78 hex +16 dB 0111 0000 70 hex +14 dB 0110 1000 68 hex +12 dB 0110 0000 60 hex +11 dB 0101 1000 58 hex +1 dB 0000 1000 08 hex +1/8 dB 0000 0001 01 hex 0 dB 0000 0000 00 hex RESET –1/8 dB 1111 1111 FF hex –1 dB 1111 1000 F8 hex –11 dB 1010 1000 A8 hex –12 dB 1010 0000 A0 hex With positive bass settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recom- mended to set bass to a value that, in conjunction with volume, would result in an overall positive gain.

BSP 3505DPRELIMINARY DATA SHEET 15Micronas 4.4.4. Treble Loudspeaker Channel Treble Loudspeaker 0003hex H +15 dB 0111 1000 78 hex +14 dB 0111 0000 70 hex +1 dB 0000 1000 08 hex +1/8 dB 0000 0001 01 hex 0 dB 0000 0000 00 hex RESET –1/8 dB 1111 1111 FF hex –1 dB 1111 1000 F8 hex –11 dB 1010 1000 A8 hex –12 dB 1010 0000 A0 hex With positive treble settings, internal overflow may occur even with overall volume less than 0 dB. This will lead to a clipped output signal. Therefore, it is not recom- mended to set treble to a value that, in conjunction with volume, would result in an overall positive gain. 4.4.5. Loudness Loudspeaker Channel Loudness Loudspeaker 0004hex H +17 dB 0100 0100 44 hex +16 dB 0100 0000 40 hex +1 dB 0000 0100 04 hex 0 dB 0000 0000 00 hex RESET Mode Loudness Loudspeaker 0004hex L Normal (constant volume at 1 kHz) 0000 0000 00 hex RESET Super Bass (constant volume at 2 kHz) 0000 0100 04 hex Loudness increases the volume of low and high frequen- cy signals, while keeping the amplitude of the 1 kHz ref- erence frequency constant. The intended loudness has to be set according to the actual volume setting. Be- cause loudness introduces gain, it is not recommended to set loudness to a value that, in conjunction with vol- ume, would result in an overall positive gain. By means of ‘Mode Loudness’, the corner frequency for bass amplification can be set to two different values. In Super Bass mode, the corner frequency is shifted up. The point of constant volume is shifted from 1 kHz to 2 kHz.

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4.4.6. Spatial Effects Loudspeaker Channel Spatial Effect Strength Loudspeaker 0005hex H Enlargement 100% 0111 1111 7F hex Enlargement 50% 0011 1111 3F hex Enlargement 1.5% 0000 0001 01 hex Effect off 0000 0000 00 hex RESET Reduction 1.5% 1111 1111 FF hex Reduction 50% 1100 0000 C0 hex Reduction 100% 1000 0000 80 hex Spatial Effect Mode Loudspeaker 0005hex [7..4] Stereo Basewidth En- largement (SBE) and Pseudo Stereo Effect (PSE). (Mode A) 0000 0 hex RESET 0000 0 hex Stereo Basewidth En- largement (SBE) only. (Mode B) 0010 2 hex Spatial Effect Cus- tomize Coefficient Loudspeaker 0005hex [3..0] max high pass gain 0000 0 hex RESET 2/3 high pass gain 0010 2 hex 1/3 high pass gain 0100 4 hex min high pass gain 0110 6 hex automatic 1000 8 hex There are several spatial effect modes available: Mode A (low byte = 00hex) is compatible to the formerly used spatial effect. Here, the kind of spatial effect de- pends on the source mode. If the incoming signal is in mono mode, Pseudo Stereo Effect is active; for stereo signals, Pseudo Stereo Effect and Stereo Basewidth Enlargement is effective. The strength of the effect is controllable by the upper byte. A negative value reduces the stereo image. A rather strong spatial effect is recom- mended for small TV sets where loudspeaker spacing is rather close. For large screen TV sets, a more moderate spatial effect is recommended. In mode A, even in case of stereo input signals, Pseudo Stereo Effect is active, which reduces the center image. In Mode B, only Stereo Basewidth Enlargement is effec- tive. For mono input signals, the Pseudo Stereo Effect has to be switched on. It is worth mentioning, that all spatial effects affect ampli- tude and phase response. With the lower 4 bits, the fre- quency response can be customized. A value of 0000 bin yields a flat response for center signals (L = R) but a high pass function of L or R only signals. A value of 0110 bin has a flat response for L or R only signals but a lowpass function for center signals. By using 1000 bin, the fre- quency response is automatically adapted to the sound material by choosing an optimal high pass gain.

BSP 3505DPRELIMINARY DATA SHEET 17Micronas 4.4.7. Volume SCART1 Volume Mode SCART1 0007hex [3..0] linear 0000 0 hex RESET logarithmic 0001 1 hex Linear Mode Volume SCART1 0007hex H OFF 0000 0000 00 hex RESET 0 dB gain (digital full scale (FS) to 2 V RMS output) 0100 0000 40 hex +6 dB gain (–6 dBFS to 2 VRMS output) 0111 1111 7F hex Logarithmic Mode Volume SCART1 0007hex [15..4] +12 dB 0111 1111 0000 7F0 hex +11.875 dB 0111 1110 1110 7EE hex +0.125 dB 0111 0011 0010 732 hex 0 dB 0111 0011 0000 730 hex –0.125 dB 0111 0010 1110 72E hex –113.875 dB 0000 0001 0010 012 hex –114 dB 0000 0001 0000 010 hex Mute 0000 0000 0000 000 hex RESET 4.4.8. Channel Source Modes Loudspeaker Source 0008hex H SCART1 Source 000A hex H Quasi-Peak Detector Source 000C hex H NONE (MSP3410: FM) 0000 0000 00 hex RESET NONE (MSP3410: NICAM) 0000 0001 01 hex SCART 0000 0010 02 hex 4.4.9. Channel Matrix Modes Loudspeaker Matrix 0008hex L SCART1 Matrix 000A hex L Quasi-Peak Detector Matrix 000C hex L SOUNDA / LEFT 0000 0000 00 hex RESET SOUNDB / RIGHT 0001 0000 10 hex STEREO 0010 0000 20 hex MONO 0011 0000 30 hex 4.4.10. SCART Prescale Volume Prescale SCART 000D hex H OFF 0000 0000 00 hex RESET 0 dB gain (2 VRMS in- put to digital full scale) 0001 1001 19 hex +14 dB gain (400 mV RMS input to digital full scale) 0111 1111 7F hex

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4.4.11. Definition of Digital Control Output Pins ACB Register 0013hex [15..14] D_CTR_OUT0 low (RESET) high D_CTR_OUT1 low (RESET) high 4.4.12. Definition of SCART-Switching Facilities ACB Register 0013hex [13..0] DSP IN Selection of Source: * SC1_IN_L/R MONO_IN SC2_IN_L/R Mute xx xx00 xx00 0000 xx xx01 xx00 0000 xx xx10 xx00 0000 xx xx11 xx10 0000 SC1_OUT_L/R Selection of Source: SC2_IN_L/R MONO_IN SCART1 via D/A SC1_IN_L/R Mute xx 01xx x0x0 0000 xx 10xx x0x0 0000 xx 11xx x0x0 0000 xx 01xx x1x0 0000 xx 11xx x1x0 0000 * = RESET position, which becomes active at the time of the first write transmission on the control bus to the audio processing part (DSP). By writing to the ACB register first, the RESET state can be redefined. Note: After RESET, SC1_OUT_L/R is undefined! Note: If “MONO_IN ” is selected at the DSP_IN selec- tion, the channel matrix mode of the corresponding out- put channel(s) must be set to “sound A”. 4.4.13. Beeper Beeper Volume 0014hex H OFF 0000 0000 00 hex RESET Maximum Volume (full digital scale FDS) 0111 1111 7F hex Beeper Frequency 0014hex L

16 Hz (lowest) 0000 0001 01 hex

4 kHz (highest) 1111 1111 FF hex A squarewave beeper can be added to the loudspeaker channel. The addition point is just before volume adjust- ment.

BSP 3505DPRELIMINARY DATA SHEET 19Micronas 4.4.14. Automatic Volume Correction (AVC) AVC on/off 0029hex [15.12] AVC off and Reset of int. variables 0000 0 hex RESET AVC on 1000 8 hex AVC Decay Time 0029hex [11..8] 8 sec (long) 4 sec (middle) 2 sec (short) 20 ms (very short) 1000 8 hex 0100 4 hex 0010 2 hex 0001 1 hex Different sound sources fairly often do not have the same volume level. Advertisement during movies, as well, usually has a different (higher) volume level than the movie itself. The Automatic Volume Correction (AVC) solves this problem and equalizes the volume lev- els. The absolute value of the incoming signal is fed into a filter with 16 ms attack time and selectable decay time. The decay time must be adjusted as shown in the table above. This attack/decay filter block works similar to a peak hold function. The volume correction value with its quasi continuous step width is calculated using the at- tack/decay filter output. The Automatic Volume Correction works with an internal reference level of –18 dBFS. This means, input signals with a volume level of –18 dBFS will not be affected by the AVC. If the input signals vary in a range of –24 dB to 0 dB, the AVC compensates this. Example: A static input signal of 1 kHz on Scart has an output level as shown in the table below. Scart Input 0 dbr = 2 Vrms Volume Correc- tion Main Output 0 dBr = 1.4 Vrms 0 dBr –18 dB –18 dBr –6 dBr –12 dB –18 dBr –12 dBr –6 dB –18 dBr –18 dBr –0 dB –18 dBr –24 dBr + 6 dB –18 dBr –30 dBr + 6 dB –24 dBr Loudspeaker Volume = 73hex = 0 dBFS Scart Prescale = 20hex i.e. 2.0 Vrms = 0 dBFS To reset the internal variables, the AVC should be switched off and on during any channel or source change. For standard applications, the recommended decay time is 4 sec. Note: AVC should not be used in any Dolby Prologic mode, except PANORAMA, where no other than the loudspeaker output is active. 4.5. DSP Read Registers: Functions and Values All readable registers are 16-bit wide. Transmissions via I 2C bus have to take place in 16-bit words. Single data entries are 8 bit. Some of the defined 16-bit words are divided into low and high byte, thus holding two different control entities. These registers are not writeable. 4.5.1. Quasi-Peak Detector Quasi-Peak Readout Left 0019hex H+L Quasi-Peak Readout Right 001A hex H+L Quasi peak readout [0hex ... 7FFFhex] values are 16 bit two’s complement The quasi peak readout register can be used to read out the quasi peak level of any input source, in order to ad- just all inputs to the same normal listening level. The re- fresh rate is 32 kHz. The feature is based on a filter time constant: attack-time: 1.3 ms decay-time: 37 ms

BSP 3505D PRELIMINARY DATA SHEET

20 Micronas

4.5.2. BSP Hardware Version Code Hardware Version 001Ehex H Hardware Version [00hex ... FFhex] BSP 3505D – A 2 01hex A change in the hardware version code defines hard- ware optimizations that may have influence on the chip’s behavior. The readout of this register is identical to the hardware version code in the chip’s imprint. 4.5.3. BSP Major Revision Code Major Revision 001Ehex L BSP 3505D 04hex 4.5.4. BSP Product Code Product 001Fhex H BSP 3505D 05hex 4.5.5. BSP ROM Version Code ROM Version 001Fhex L Major software revision[00hex ... FFhex] BSP 3505D – A2 02hex A change in the ROM version code defines internal soft- ware optimizations, that may have influence on the chip’s behavior, e.g. new features may have been in- cluded. While a software change is intended to create no compatibility problems, customers that want to use the new functions can identify new BSP 3505D versions ac- cording to this number.

BSP 3505DPRELIMINARY DATA SHEET 21Micronas 5. Specifications 5.1. Outline Dimensions Fig. 5–1: 68-Pin Plastic Leaded Chip Carrier Package (PLCC68) Weight approximately 4.8 g Dimensions in mm x 45°1.1 25.125 0.125± 0.22 0.07± 1.2 x 45° 24.22 0.1± 4327 619 0.480.711 1.9 4.05 0.1 4.75±0.15 1.27 0.1± 1.27 0.1± 24.22 0.1± 0.923.4 SPGS7004-3/5E 25.125 0.125± 1.6 0.457 1.29 13 2 3364 30.3 1.9 (1) 1.778±0.05 1±0.1 57.7±0.1 3.2±0.4 3.8±0.1 4.8±0.4 19.3±0.1 18±0.1 20.1±0.5 0.27±0.06 SPGS0016-4/3E 31 x 1.778 = 55.118±0.1 2.5 0.3 Fig. 5–2: 64-Pin Plastic Shrink Dual Inline Package (PSDIP64) Weight approximately 9.0 g Dimensions in mm 0.24 0.3 14±0.1 1.778±0.05 Fig. 5–3: 52-Pin Plastic Shrink Dual In Line Package (PSDIP52) Weight approximately 5.5 g Dimensions in mm 12 6 2752 0.457 0°...15° 47±0.1 0.4±0.2 4±0.1 3.2±0.2 1±0.1 15.6±0.1 0.27±0.06 25 x 1.778 = 44.47±0.1 SPGS0015-1/2E

BSP 3505D PRELIMINARY DATA SHEET

22 Micronas

17.2 23.2 9.8 1.8 10.3 23 x 0.8 = 18.4 15 x 0.8 = 12.0 0.8 0.8 4164 241 1.28 2.70 1.8 0.13 ±0.2 0.17±0.03 SPGS0025-1/1EFig. 5–4: 80-Pin Plastic Quad Flat Package (PQFP80) Weight approximately 1.6 g Dimensions in mm Fig. 5–5: 44-Pin Plastic Quad Flat Package (PQFP44) Weight approx. 0.4 g Dimensions in mm SPGS0006-1/1E 2333 13.2 13.2 1.3 1.75 1.75 2.0 0.12.15 0.18 0.8 0.8 10 x 0.8 = 8 10 x 0.8 = 8 3.0 0.375

BSP 3505DPRELIMINARY DATA SHEET 23Micronas 5.2. Pin Connections and Short Descriptions NC = not connected; leave vacant LV = if not used, leave vacant DVSS: if not used, connect to DVSS X = obligatory; connect as described in circuit diagram AHVSS: connect to AHVSS Pin No. Pin Name Type Connection (if not sed) Short Description PLCC 68-pin PSDIP 64-pin PSDIP 52-pin PQFP 80-pin PQFP 44-pin (if not used) 1 16 14 9 – TP OUT LV Test pin 2 – – – – NC LV Not connected 3 15 13 8 – TP OUT LV Test pin 4 14 12 7 17 TP IN LV Test pin 5 13 11 6 16 TP OUT LV Test pin 6 12 10 5 15 TP IN/OUT LV Test pin 7 11 9 4 14 TP IN/OUT LV Test pin 8 10 8 3 13 I2C_DA IN/OUT X I2C data 9 9 7 2 12 I2C_CL IN/OUT X I2C clock 10 8 – 1 – NC LV Not connected 11 7 6 80 11 STANDBYQ IN X Standby (low-active) 12 6 5 79 10 ADR_SEL IN X I2C Bus address select 13 5 4 78 9 D_CTR_OUT0 OUT LV Digital control output 0 14 4 3 77 8 D_CTR_OUT1 OUT LV Digital control output 1 15 3 – 76 – NC LV Not connected 16 2 – 75 – NC LV Not connected 17 – – – – NC LV Not connected 18 1 2 74 – NC LV Not connected 19 64 1 73 7 TP LV Test pin 20 63 52 72 6 XTAL_OUT OUT X Crystal oscillator 21 62 51 71 5 XTAL_IN IN X Crystal oscillator 22 61 50 70 4 TESTEN IN X Test pin 23 60 49 69 – NC LV Not connected 24 59 48 68 3 TP IN LV Test pin 25 58 47 67 2 TP IN LV Test pin 26 57 46 66 1 AVSUP X Analog power supply +5 V – – – 65 – AVSUP X Analog power supply +5 V – – – 64 – NC LV Not connected – – – 63 – NC LV Not connected

BSP 3505D PRELIMINARY DATA SHEET

24 Micronas

Short DescriptionConnection (if not used) TypePin NamePin No. Short DescriptionConnection (if not used) PQFP 44-pin PQFP 80-pin PSDIP 52-pin PSDIP 64-pin PLCC 68-pin 27 56 45 62 44 AVSS X Analog ground – – – 61 – AVSS X Analog ground 28 55 44 60 43 MONO_IN IN LV Mono input – – – 59 – NC LV Not connected 29 54 43 58 42 VREFTOP X Reference voltage 30 53 42 57 41 SC1_IN_R IN LV Scart input 1 in, right 31 52 41 56 40 SC1_IN_L IN LV Scart input 1 in, left 32 51 – 55 39 ASG1 AHVSS Analog shield ground 1 33 50 40 54 38 SC2_IN_R IN LV Scart input 2 in, right 34 49 39 53 37 SC2_IN_L IN LV Scart input 2 in, left 35 48 – 52 – TP LV Test Pin 36 47 38 51 – NC LV Not connected 37 46 37 50 – NC LV Not connected 38 45 – 49 – NC LV Not connected 39 44 – 48 – NC LV Not connected 40 43 – 47 – NC LV Not connected 41 – – 46 – NC LV Not connected 42 42 36 45 36 AGNDC X Analog reference volt- age high voltage part 43 41 35 44 35 AHVSS X Analog ground – – – 43 – AHVSS X Analog ground – – – 42 – NC LV Not connected – – – 41 – NC LV Not connected 44 40 34 40 34 CAPL_M X Volume capacitor MAIN 45 39 33 39 33 AHVSUP X Analog power supply 8.0 V 46 38 32 38 32 NC LV Not connected 47 37 31 37 31 SC1_OUT_L OUT LV Scart output 1, left 48 36 30 36 30 SC1_OUT_R OUT LV Scart output 1, right 49 35 29 35 29 VREF1 X Reference ground 1 high voltage part 50 34 28 34 28 NC LV Not connected 51 33 27 33 – NC LV Not connected 52 – – 32 – NC LV Not connected

BSP 3505DPRELIMINARY DATA SHEET 25Micronas Short DescriptionConnection (if not used) TypePin NamePin No. Short DescriptionConnection (if not used) PQFP 44-pin PQFP 80-pin PSDIP 52-pin PSDIP 64-pin PLCC 68-pin 53 32 – 31 – NC LV Not connected 54 31 26 30 – NC LV Not connected 55 30 – 29 – NC LV Not connected 56 29 25 28 27 DACM_L OUT LV Loudspeaker out, left 57 28 24 27 26 DACM_R OUT LV Loudspeaker out, right 58 27 23 26 25 VREF2 X Reference ground 2 high voltage part 59 26 22 25 24 NC LV Not connected 60 25 21 24 23 NC LV Not connected – – – 23 – NC LV Not connected – – – 22 – NC LV Not connected 61 24 20 21 22 RESETQ IN X Power-on-reset 62 23 – 20 – NC LV Not connected 63 22 – 19 – NC LV Not connected 64 21 19 18 21 NC LV Not connected 65 20 18 17 – TP IN LV Test pin 66 19 17 16 – DVSS X Digital ground – – – 15 – DVSS X Digital ground – – – 14 20 DVSS X Digital ground 67 18 16 13 19 DVSUP X Digital power supply +5 V – – – 12 – DVSUP X Digital power supply +5 V – – – 11 – DVSUP X Digital power supply +5 V 68 17 15 10 18 TP OUT LV Test pin

BSP 3505D PRELIMINARY DATA SHEET

26 Micronas

5.3. Pin Configurations 78910 29 30 31 32 33 34 35 36 37 38 39 27 28 654321 43424140 68 67 66 65 64 63 62 61 TP NC TP TP TP TP I2C_DA TP I2C_CL NC STANDBYQ ADR_SEL D_CTR_OUT0 D_CTR_OUT1 NC NC NC NC TP XTAL_OUT XTAL_IN TESTEN NC TP TP AVSUP AVSS MONO_IN VREFTOP SC1_IN_R SC1_IN_L ASG1 SC2_IN_R SC2_IN_L TP NC NC NC NC NC NC AGNDC AHVSS CAPL_M AHVSUP NC SC1_OUT_L SC1_OUT_R VREF1 NC NC NC NC NC NC DACM_L DACM_R VREF2 NC NC RESETQ NC NC NC TP DVSS DVSUP TP Fig. 5–6: 68-pin PLCC package BSP 3505D

BSP 3505DPRELIMINARY DATA SHEET 27Micronas Fig. 5–7: 64-pin PSDIP package 20 45 NC D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA TP TP TP TP TP TP DVSUP DVSS TP NC TESTEN TP AVSUP AVSS VREFTOP SC1_IN_L SC1_IN_R TP NC NC TP SC2_IN_R XTAL_IN XTAL_OUT MONO_IN D_CTR_OUT1 SC2_IN_L ASG1 TP NC NC NC VREF2 DACM_R DACM_L RESETQ AHVSS NC SC1_OUT_L SC1_OUT_R NC NC AGNDC NC VREF1 AHVSUP CAPL_M NC NC NC NC NC NC NC NC NC TP BSP 3505D 20 33 D_CTR_OUT0 ADR_SEL STANDBYQ I2C_CL I2C_DA TP TP TP TP TP TP DVSUP DVSS TP TESTEN TP AVSUP AVSS VREFTOP SC1_IN_L SC1_IN_RTP NC NC SC2_IN_R XTAL_IN XTAL_OUT MONO_IN D_CTR_OUT1 SC2_IN_L TP NC NC VREF2 DACM_R DACM_L NC NC AHVSS NC SC1_OUT_L SC1_OUT_R NC NC AGNDC VREF1 AHVSUP CAPL_M Fig. 5–8: 52-pin PSDIP package NC RESETQ NC TP BSP 3505D

BSP 3505D PRELIMINARY DATA SHEET

28 Micronas

SC1_IN_R VREFTOP NC MONO_IN AVSS NC AVSS NC AVSUP AVSUP TP TP NC TESTEN XTAL_OUT XTAL_IN TP NC NC NC D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ NC I2C_CL I2C_DA TP TP TP TP TP TP NC NC NC RESETQ NC NC NC NC VREF2 DACM_R DACM_L NC NC NC NC NC NC VREF1 SC1_OUT_R SC1_OUT_L NC AHVSUP CAPL_M NC NC AHVSS AHVSS AGNDC NC NC NC Fig. 5–9: 80-pin PQFP package 47 46 45 44 43 42 41 18 19 20 21 22 23 24 SC2_IN_L SC2_IN_R ASG1 SC1_IN_L NC NC NC TP DVSUP DVSS DVSS DVSSTP TP DVSUP DVSUP BSP 3505D

BSP 3505DPRELIMINARY DATA SHEET 29Micronas 34CAPL_M 35AHVSS 36AGNDC 37SC2_IN_L 38SC2_IN_R 39ASG1 40SC1_IN_L 41SC1_IN_R 42VREFTOP 43MONO_IN 44AVSS RESETQ22 NC21 DVSS20 DVSUP19 TP18 TP17 TP16 TP15 TP14 I2C_DA13 I2C_CL12 NC SC1_OUT_L SC1_OUT_R VREF1 NC AHVSUP DACM_L DACM_R VREF2 NC NC TP TP TESTEN XTAL_IN XTAL_OUT AVSUP TP D_CTR_OUT1 D_CTR_OUT0 ADR_SEL STANDBYQ 123456789 1 0 1 1 33 32 31 30 29 28 27 26 25 24 23 BSP 3505D Fig. 5–10: 44-pin PQFP package

BSP 3505D PRELIMINARY DATA SHEET

30 Micronas

5.4. Pin Circuits (pin numbers refer to PLCC68 package) Fig. 5–11: Input/Output Pins 8 and 9 (I2C_DA, I2C_CL) N GND Fig. 5–12: Input Pins 11, 12, and 61 (STANDBYQ, ADR_SEL, RESETQ) Fig. 5–13: Output Pins 13, and 14 (D_CTR_OUT0/1) P DV SUP N GND Fig. 5–14: Input/Output Pins 20 and 21 (XTALIN/OUT) P N 500 k3–30 pF 3–30 pF Fig. 5–15: Pin 29 (VREFTOP) VREFTOP ≈2.6V Fig. 5–16: Input Pin 28 (MONO_IN) 24 k ≈ 3.75 V Fig. 5–17: Input Pins 30, 31, 33, and 34 (SC1–2_IN_L/R) 40 k ≈ 3.75 V Fig. 5–18: Pin 42 (AGNDC) 125 k ≈ 3.75 V Fig. 5–19: Capacitor Pin 44 (CAPL_M) 0...2 V Fig. 5–20: Output Pins 47, 48 (SC1_OUT_L/R) 300 40 pF 80 k ≈ 3.75 V Fig. 5–21: Output Pins 56, 57 (DACM_L/R) 3.3 k 0...1.2 mA AHV SUP

BSP 3505DPRELIMINARY DATA SHEET 31Micronas 5.5. Electrical Characteristics 5.5.1. Absolute Maximum Ratings Symbol Parameter Pin Name Min. Max. Unit TA Ambient Operating Temperature – 0 701) °C TS Storage Temperature – –40 125 °C VSUP1 First Supply Voltage AHVSUP –0.3 9.0 V VSUP2 Second Supply Voltage DVSUP –0.3 6.0 V VSUP3 Third Supply Voltage AVSUP –0.3 6.0 V dVSUP23 Voltage between AVSUP and DVSUP AVSUP , DVSUP –0.5 0.5 V PTOT Chip Power Dissipation PLCC68 without Heat Spreader PSDIP64 without Heat Spreader PSDIP52 without Heat Spreader PQFP44 without Heat Spreader AHVSUP , DVSUP , AVSUP 1200 1300 1200 960 mW VIdig Input Voltage, all Digital Inputs –0.3 VSUP2 +0.3 V IIdig Input Current, all Digital Pins– –20 +20 mA 2) VIana Input Voltage, all Analog InputsSCn_IN_s,3) MONO_IN –0.3 VSUP1 +0.3 V IIana Input Current, all Analog InputsSCn_IN_s,3) MONO_IN –5 +5 mA 2) IOana Output Current, all SCART OutputsSC1_OUT_s 4), 5) 4), 5) IOana Output Current, all Analog Outputs except SCART Outputs DACM_s 3) 4) 4) ICana Output Current, other pins connected to capacitors CAPL_M AGNDC 4) 4) 1) For PQFP44 package, max. ambient operating temperature is 65 °C. 2) positive value means current flowing into the circuit 4) The Analog Outputs are short circuit proof with respect to First Supply Voltage and Ground. 5) Total chip power dissipation must not exceed absolute maximum rating. Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi- mum ratings conditions for extended periods may affect device reliability.

BSP 3505D PRELIMINARY DATA SHEET

32 Micronas

5.5.2. Recommended Operating Conditions at TA = 0 to 70 °C (65 °C for PQFP44) Symbol Parameter Pin Name Min. Typ. Max. Unit VSUP1 First Supply Voltage AHVSUP 7.6 8.0 8.4 V VSUP2 Second Supply Voltage DVSUP 4.75 5.0 5.25 V VSUP3 Third Supply Voltage AVSUP 4.75 5.0 5.25 V VREIL RESET Input High-Low and Low- High Transition Voltage RESETQ 0.45 0.8 VSUP2 tREIL RESET Low Time after DVSUP Stable and Oscillator Startup 5 µs VDIGIL Digital Input Low Voltage STANDBYQ, ADR SEL

0.2 VSUP2

VDIGIH Digital Input High Voltage ADR _SEL , TESTEN 0.8 VSUP2 tSTBYQ1 STANDBYQ Setup Time before Turn-off of Second Supply Voltage STANDBYQ, DVSUP 1 µs I2C-Bus Recommendations VI2CIL I2C-BUS Input Low Voltage I2C_CL, I2CD A

0.3 VSUP2

VI2CIH I2C-BUS Input High Voltage I2C _DA

0.6 VSUP2

fI2C I2C-BUS Frequency I2C_CL 1.0 MHz tI2C1 I2C START Condition Setup Time I2C_CL, I2CD A 120 ns tI2C2 I2C STOP Condition Setup Time I2C _DA 120 ns tI2C3 I2C-Clock Low Pulse Time I2C_CL 500 ns tI2C4 I2C-Clock High Pulse Time 500 ns tI2C5 I2C-Data Setup Time Before Rising Edge of Clock I2C_CL, I2C_DA 55 ns tI2C6 I2C-Data Hold Time after Falling Edge of Clock 55 ns Crystal Recommendations fP Parallel Resonance Frequency at 12 pF Load Capacitance

18.432 MHz

fTOL Accuracy of Adjustment –100 +100 ppm D TEM Frequency Variation versus Temperature –50 +50 ppm R R Series Resistance 8 25 Ω C 0 Shunt (Parallel) Capacitance 6.2 7.0 pF

BSP 3505DPRELIMINARY DATA SHEET 33Micronas UnitMax.Typ.Min.Pin NameParameterSymbol Load Capacitance Recommendations C L External Load Capacitance1) XTAL_IN, XTAL_OUT PSDIP 1.5 PLCC 3.3 pF pF Amplitude Recommendation for Operation with External Clock Input (Cload after reset = 22 pF) VXCA External Clock Amplitude XTAL_IN 0.7 Vpp Analog Input and Output Recommendations C AGNDC AGNDC-Filter-Capacitor AGNDC –20% 3.3 µF Ceramic Capacitor in Parallel –20% 100 nF C inSC DC-Decoupling Capacitor in front of SCART Inputs SCn_IN_s2) –20% 330 +20% nF VinSC SCART Input Level 2.0 VRMS VinMONO Input Level, Mono Input MONO_IN 2.0 VRMS R LSC SCART Load Resistance SC1_OUT_s 2) 10 kΩ C LSC SCART Load Capacitance 6.0 nF C VMA Main Volume Capacitor CAPL_M 10 µF C FMA Main Filter Capacitor DACM_s 2) –10% 1 +10% nF Recommendations for Reference Voltage Pin C VREFTOP VREFTOP-Filter-Capacitor VREFTOP –20% 10 µF Ceramic Capacitor in Parallel –20% 100 nF 1) External capacitors at each crystal pin to ground are required. The higher the capacitors, the lower the clock frequency results. The nominal free running frequency should match 18.432 MHz as closely as possible. Due to different layouts of customer PCBs, the matching capacitor size should be defined in the application. The sug- gested values (1.5 pF/3.3 pF) are figures based on experience with various PCB layouts.

BSP 3505D PRELIMINARY DATA SHEET

34 Micronas

5.5.3. Characteristics at TA = 0 to 70 °C (65 °C for PQFP44), fCLOCK = 18.432 MHz, at TA = 60 °C, fCLOCK = 18.432 MHz, VSUP1 = 8 V, VSUP2 = 5 V for typical values, TJ = Junction Temperature MAIN (M) = Loudspeaker Channel, AUX (A) = Headphone Channel Symbol Parameter Pin Name Min. Typ. Max. Unit Test Conditions fCLOCK Clock Input Frequency XTAL_IN 18.432 MHz D CLOCK Clock High to Low Ratio 45 55 % tJITTER Clock Jitter (Verification not provided in Production test) 50 ps VxtalDC DC-Voltage Oscillator 2.5 V tStartup Oscillator Startup Time at VDD Slew-rate of 1 V/1 µs XTAL_IN, XTAL_OUT 0.4 2 ms ISUP1A First Supply Current (active) Analog Volume for Main and Aux at 0dB Analog Volume for Main and Aux at –30dB AHVSUP 9.6 6.3 17.1 11.2 24.6 16.1 mA mA ISUP2A Second Supply Current (active)DVSUP 86 95 102 mA ISUP3A Third Supply Current (active) AVSUP 15 25 35 mA ISUP1S First Supply Current (standby mode) at T j = 27 °C AHVSUP 3.5 5.6 7.7 mA STANDBYQ = low VI2COL I2C-Data Output Low Voltage I2C_DA 0.4 V II2COL = 3 mA II2COH I2C-Data Output High Current 1.0 µA VI2COH = 5 V tI2COL1 I2C-Data Output Hold Time after Falling Edge of Clock I2C_DA, I2C_CL 15 ns tI2COL2 I2C-Data Output Setup Time before Rising Edge of Clock 100 ns fI2C = 1 MHz Analog Ground VAGNDC0 AGNDC Open Circuit Voltage AGNDC 3.63 3.73 3.83 V R load ≥ 10 MΩ R outAGN AGNDC Output Resistance 70 125 180 kΩ 3 V ≤ VAGNDC ≤ 4 V Analog Input Resistance R inSC SCART Input Resistance from TA = 0 to 70 °C SCn_IN_s1) 25 40 58 kΩ fsignal = 1 kHz, I = 0.05 mA R inMONO MONO Input Resistance from TA = 0 to 70 °C MONO_IN 15 24 35 kΩ fsignal = 1 kHz, I = 0.1 mA Audio Analog-to-Digital-Converter VAICL Effective Analog Input Clipping Level for Analog-to-Digital- Conversion SCn_IN_s,1) MONO_IN 2.00 2.25 VRMS fsignal = 1 kHz

BSP 3505DPRELIMINARY DATA SHEET 35Micronas Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol SCART Outputs R outSC SCART Output Resistance at Tj = 27 °C from TA = 0 to 70 °C SC1_OUT_s 1) 200 200 330 460 500 Ω Ω fsignal = 1 kHz, I = 0.1 mA dVOUTSC Deviation of DC-Level at SCART Output from AGNDC Voltage –70 +70 mV ASCtoSC Gain from Analog Input to SCART Output SCn_IN_s1) MONO_IN –1.0 +0.5 dB fsignal = 1 kHz frSCtoSC Frequency Response from Analog Input to SCART Output bandwidth: 0 to 20000 Hz SC1_OUT_s 1) –0.5 +0.5 dB with resp. to 1 kHz VoutSC Effective Signal Level at SCART- Output during full-scale digital in- put signal from DSP SC1_OUT_s 1) 1.8 1.9 2.0 VRMS fsignal = 1 kHz Main Outputs R outMA Main Output Resistance at T j = 27 °C from TA = 0 to 70 °C DACM_s 1) 2.1 2.1 3.3 4.6 5.0 kΩ kΩ fsignal = 1 kHz, I = 0.1 mA VoutDCMA DC-Level at Main-Output for Analog Volume at 0 dB for Analog Volume at –30 dB 1.8 2.04 2.28 V mV VoutMA Effective Signal Level at Main-Out- put during full-scale digital input signal from DSP for Analog Vol- ume at 0 dB 1.23 1.37 1.51 VRMS fsignal = 1 kHz Analog Performance SNR Signal-to-Noise Ratio from Analog Input to SCART Output MONO_IN, SCn_IN_s SC1_OUT_s 1) 93 96 dB Input Level = –20 dB, fsig = 1 kHz, equally weighted 20 Hz...20 kHz THD Total Harmonic Distortion from Analog Input to SCART Output MONO_IN, SCn_IN_s SC1_OUT_s 1) 0.01 0.03 % Input Level = –3 dBr, fsig = 1 kHz, equally weighted 20 Hz...20 kHz

BSP 3505D PRELIMINARY DATA SHEET

36 Micronas

Test ConditionsUnitMax.Typ.Min.Pin NameParameterSymbol XTALK Crosstalk attenuation – PLCC68 – PSDIP64 Input Level = –3 dB, fsig = 1 kHz, unused ana- log inputs connected to ground by Z < 1 kΩ between left and right channel within SCART Input/Output pair (L→ R, R→ L) equally weighted 20 Hz...20 kHz SCn_IN 1) → SC1_OUT PLCC68 PSDIP64 dB dB PSRR: rejection of noise on AHVSUP at 1 kHz AGNDC AGNDC 80 dB From Analog Input to SCART Output MONO_IN, SCn_IN_s SC1_OUT_s 1) 70 dB DC VREFTOP DC voltage at VREFTOP VREFTOP 2.4 2.6 2.7 V

BSP 3505DPRELIMINARY DATA SHEET 37Micronas 6. Application Circuit DACM_L (29) 56 DACM_R (28) 57 SC1_OUT_L (37) 47 SC1_OUT_R (36) 48 TESTEN (61) 22 32 (51) ASG1 8 (10) I2C_DA 9 (9) I2C_CL 12 (6) ADR_SEL 31 (52) SC1_IN_L BSP 3505D 28 (55) MONO_IN 11 (7) STANDBYQ 30 (53) SC1_IN_R 33 (50) SC2_IN_R 34 (49) SC2_IN_L 45 (39) AHVSUP 43 (41) AHVSS 26 (57) AVSUP 67 (18) DVSUP 66 (19) DVSS 61 (24) RESETQ 27 (56) AVSS 49 (35) VREF1 58 (27) VREF2 18.432 MHz MAIN +8.0 V 1 µF 5 V 5 V 8.0 V 3.3 µF 330 nF 330 nF 330 nF 330 nF 330 nF 1 µF1 nF 22 µF 22 µF 10 µF µF 100 nF 100 nF 100 nF 100 nF AHVSS AVSS 100 nF + 100Ω 100Ω AVSS DVSS DVSS ResetQ (from CCU, see section.3.3.) CAPL_M (40) 44 VREFTOP (54) 29 AGNDC (42) 42 XTAL_IN (62) 21 XTAL_OUT (63) 20 C s. section 5.5.2. 10 µF D_CTR_OUT1 (4) 14 D_CTR_OUT0 (5) 13 Note: Pin numbers refer to the PLCC68 package, numbers in brackets refer to the PSDIP64 package. Application Note: All ground pins should be connected to one low-resistive ground plane. All supply pins should be connected separately with short and low-resistive lines to the power supply. Decoupling capacitors from DVSUP to DVSS, AVSUP to AVSS, and AHVSUP to AHVSS are recommended as close as possible to these pins. Decoupling of DVSUP and DVSS is most important. We recommend using more than one capacitor. By choosing different values, the frequency range of active decoupling can be ex- tended. In our application boards we use: 220 pF, 470 pF, 1.5 nF, and 10 µF. The capacitor with lowest val- ue should be placed nearest to the DVSUP and DVSS pins. The ASG1 pin should be connected as closely as pos- sible to the MSP to ground. If it is lead with the SC1 input- lines as shielding line, it should NOT be conneted to ground at the SCART connector.

BSP 3505D PRELIMINARY DATA SHEET

38 Micronas

BSP 3505DPRELIMINARY DATA SHEET 39Micronas

BSP 3505D PRELIMINARY DATA SHEET

40 Micronas

Appendix A: BSP 3505D Version History First hardware release BSP 3505D 8. Data Sheet History 1. Preliminary Data Sheet: “BSP 3505D Baseband Sound Processor”, Oct. 21, 1998, 6251-481-1PD. First release of the preliminary data sheet. Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-481-1PD All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirma- tion form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume re- sponsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.

Product Information

BSP3505D specifications and overview.

Summary

Baseband Sound Processor

Description

Baseband Sound Processor

Source title BSP3505D Datasheet(PDF) - Micronas

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